GPLB52640A-NnnV-C [GENERALPLUS]
1000/2000 Dots Mono/4-Gray-Level LCD Controller/Driver with 8-CH SPU;
| 型号： | GPLB52640A-NnnV-C |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 1000/2000 Dots Mono/4-Gray-Level LCD Controller/Driver with 8-CH SPU CD |
| 文件： | 总28页 (文件大小：5784K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPLB52640A
GPLB52320A
GPLB51640A
1000/2000 Dots Mono/4-Gray-Level
LCD Controller/Driver with 8-CH SPU
Sep 12, 2013
Version 2.2
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 4
2. BLOCK DIAGRAM ...................................................................................................................................................................................... 4
2.1. GPLB52640A....................................................................................................................................................................................... 4
2.2. GPLB52320A....................................................................................................................................................................................... 4
2.3. GPLB51640A....................................................................................................................................................................................... 5
2.4. GPLB51320A....................................................................................................................................................................................... 5
3. FEATURES.................................................................................................................................................................................................. 5
4. APPICATION FIELD.................................................................................................................................................................................... 6
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 7
5.1. GPLB52640A/GPLB52320A................................................................................................................................................................ 7
5.2. GPLB51640A/GPLB51320A................................................................................................................................................................ 8
6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 9
6.1. MEMORIES ............................................................................................................................................................................................ 9
6.2. MAP OF MEMORY AND I/OS .................................................................................................................................................................... 9
6.3. OPERATING STATES ............................................................................................................................................................................. 10
6.4. SPEECH AND MELODY, PWM AND DAC .................................................................................................................................................11
6.5. LCD CONTROLLER/DRIVER...................................................................................................................................................................11
6.6. LCD VOLTAGE GENERATION..................................................................................................................................................................11
6.7. LOW VOLTAGE DETECTION....................................................................................................................................................................11
6.8. WATCHDOG TIMER (WDT) ....................................................................................................................................................................11
6.9. SPI CONTROLLER.................................................................................................................................................................................11
6.10.MASK OPTIONS.................................................................................................................................................................................... 12
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 13
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 13
7.2. DC CHARACTERISTICS (VDD5V=5.0V, FOR 3-BATTERY APPLICATION, INTERNAL REGULATOR ENABLED OUTPUT, TA=25℃) ...................... 13
7.3. DC CHARACTERISTICS (VDD5V=VDD=3.0V, FOR 2-BATTERY APPLICATION, INTERNAL REGULATOR OUTPUT DISABLED, TA=25℃) ........... 14
7.4. THE RELATIONSHIP BETWEEN THE ROSC AND THE FOSC........................................................................................................................... 15
7.5. THE RELATIONSHIP BETWEEN THE F32K AND THE R32K........................................................................................................................ 15
7.6. THE RELATIONSHIPS BETWEEN THE FCPU AND THE IOP ............................................................................................................................ 15
7.7. DAC CHARACTERISTICS (VDD5V = 5.0V, TA = 25℃) ........................................................................................................................... 16
8. APPLICATION CIRCUITS......................................................................................................................................................................... 17
8.1. 2048 DOTS LCD DRIVER, USING GPLB52640A OR GPLB52320A, 64 SEGMENTS × 32 COMMONS, FOR 3-BATTERY APPLICATION,
INTERNAL 3.3V REGULATOR ENABLED, 10-BIT PWM DRIVER ENABLED, ROSC14M XTAL32K SELECTED- (1) ............................................... 17
8.2. 2048 DOTS LCD DRIVER, USING GPLB52640A OR GPLB52320A, 64 SEGMENTS × 32 COMMONS, INTERNAL 3.3V REGULATOR DISABLED,
FOR 2-BATTERY APPLICATION, 12-BIT DAC ENABLED, ROSC14M XTAL32K SELECTED - (2).......................................................................... 18
8.3. 2048 DOTS LCD DRIVER, USING GPLB52640A OR GPLB52320A, 64 SEGMENTS × 32 COMMONS, FOR 3-BATTERY APPLICATION,
INTERNAL 3.3V REGULATOR ENABLED, 10-BIT PWM DRIVER ENABLED, XTAL12M ROSC32K SELECTED - (3) .............................................. 19
8.4. 1628 DOTS LCD DRIVER, USING GPLB51640A OR GPLB51320A, 74 SEGMENTS × 22 COMMONS, FOR 3-BATTERY APPLICATION,
INTERNAL 3.3V REGULATOR ENABLED, 10-BIT PWM DRIVER ENABLED, ROSC14M XTAL32K SELECTED- (1) ............................................... 20
8.5. 1628 DOTS LCD DRIVER, USING GPLB51640A OR GPLB51320A, 74 SEGMENTS × 22 COMMONS, FOR 2-BATTERY APPLICATION,
INTERNAL 3.3V REGULATOR DISABLED, 12-BIT DAC ENABLED, ROSC14M XTAL32K SELECTED - (2) ........................................................... 21
© Generalplus Technology Inc.
Proprietary & Confidential
2
Sep 12, 2013
Version: 2.2
GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
8.6. 1628 DOTS LCD DRIVER, USING GPLB51640A OR GPLB51320A, 74 SEGMENTS × 22 COMMONS, FOR 3-BATTERY APPLICATION,
INTERNAL 3.3V REGULATOR ENABLED, 10-BIT PWM DRIVER ENABLED, XTAL12M ROSC32K SELECTED - (3) .............................................. 22
8.7. DAC OUTPUT WITH GENERALPLUS AUDIO DRIVER GPY0030B (FOR HIGH QUALITY AUDIO OUTPUT) - (4) ................................................ 23
8.8. CURRENT MODE DAC SPEAKER DRIVER WITH BJT- (5) ........................................................................................................................ 24
8.9. SERIAL COMMUNICATIONS BETWEEN GPLB52640A/GPLB52320A/GPLB51640A/GPLB51320AAND GPUSB101A USB CONTROLLER-
(6) 25
9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 26
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 26
10.DISCLAIMER............................................................................................................................................................................................. 27
11. REVISION HISTORY ................................................................................................................................................................................. 28
© Generalplus Technology Inc.
Proprietary & Confidential
3
Sep 12, 2013
Version: 2.2
GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
1000/2000 DOTS MONO/4-GRAY-LEVEL LCD
CONTROLLER/DRIVER WITH 8CH SPU
1. GENERAL DESCRIPTION
2. BLOCK DIAGRAM
2.1. GPLB52640A
The GPLB52640A/GPLB52320A/GPLB51640A/GPLB51320A, an
8-bit CMOS microprocessor, contain 1536 bytes working RAM, 16
I/Os, interrupt/wakeup controller, two 16-bit timers, SPI interface,
one 12-bit DAC, one 10-bit PWM, and automatic display
controller/driver for mono/4-gray-level LCD. The GPLB52640A/
GPLB51640A contains 640K bytes ROM memory and the
GPLB52320A/GPLB51320A features 320K bytes ROM memory.
The GPLB52640A/GPLB52320A contains up to 64 segments and
32 commons, forming a maximum of 2048 dots LCD resolution,
and the GPLB51640A/GPLB51320A has up to 74 segments and
22 commons, forming a maximum of 1628 dots LCD. The
microprocessor can implement software for audio processing,
functional control and others. For audio processing, melody and
speech can be mixed into one output. The GPLB52640A/
GPLB52320A/ GPLB51640A/ GPLB51320A implement a high
performance SPU voice engine to achieve 8-channel voice with
ADPCM/PCM data. It operates over a wide voltage range from
2.4V through 5.5V and a Low Voltage Reset function to assure
CPU operation properly under a low voltage condition. It also
features one 10-bit PWM driver and one 12-bit DAC with 8 audio
channels to produce attractive sound effects easily. Its large
ROM area can be used to store both program and audio data.
There is a Serial Peripheral Interface (SPI) controller built-in to
facilitate communicating with other devices. Furthermore, a
SLEEP (power-down) function is also built-in to extend battery life.
The GPLB52640A/ GPLB52320A/ GPLB51640A/ GPLB51320A
are designed with state-of-the-art technology to fulfill LCD
application needs, especially for hand-held products.
32KHz
ROSC/XI
XO
32KHz
10-bit PWM
Driver
R-Oscillator/Xtal
AUDA
AUDB
32 KHz
Oscillator
&
System Clock Gen.
12-bit DAC
Driver
DACO
Time base
CSN/PB4
Power Supply
Voltage Detector
SCK/PB5
SDO/PB6
SDI/PB7
SPI
Two 16-bit /
Auto-reload
Timers
640K
bytes
ROM
SPU
8-bit
micro-processor
1536 bytes
RAM
(I/O)
8
8
PA7-0
PB7-0
Max.16
I/O Ports
LCD RAM 512 bytes
32 Commons X 64 Segments 4-gray-level/mono LCD
Driver
COM31-0
SEG63-0
2.2. GPLB52320A
32KHz
ROSC/XI
XO
32KHz
10-bit PWM
Driver
R-Oscillator/Xtal
AUDA
AUDB
32 KHz
Oscillator
&
System Clock Gen.
12-bit DAC
Driver
DACO
Time base
CSN/PB4
Power Supply
Voltage Detector
SCK/PB5
SDO/PB6
SDI/PB7
SPI
320K
bytes
Two 16-bit /
Auto-reload
Timers
ROM
SPU
8-bit
micro-processor
1536 bytes
RAM
(I/O)
8
8
PA7-0
PB7-0
Max.16
I/O Ports
LCD RAM 512 bytes
32 Commons X 64 Segments 4-gray-level/mono LCD
Driver
COM31-0
SEG63-0
© Generalplus Technology Inc.
Proprietary & Confidential
4
Sep 12, 2013
Version: 2.2
GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
2.3. GPLB51640A
Max. CPU operating speed:
– 8.0MHz @ 2.4V with 16MHz X’TAL
– 8.0MHz @ 2.4V with 16MHz ROSC
Programmable CPU clock: /2, /4, /8, /16, /32, /64 and /128
R-oscillator clock frequency
32KHz
ROSC/XI
XO
32KHz
10-bit PWM
Driver
R-Oscillator/Xtal
AUDA
AUDB
32 KHz
Oscillator
&
System Clock Gen.
12-bit DAC
Driver
DACO
Six wake-up sources
Time base
CSN/PB4
Nine IRQ & two NMI Interrupts
Power Supply
Voltage Detector
SCK/PB5
SDO/PB6
SDI/PB7
SPI
Internal built-in regulator to supply core power (3.3V, for
3-battery application). Also it can turn off internal built-in
regulator, and use external 3.6V power to supply core power
(for 2-battery application).
Two 16-bit /
Auto-reload
Timers
640K
bytes
ROM
SPU
Programmable LCD driver
8-bit
micro-processor
– LCD Size Table:
1536 bytes
RAM
(I/O)
8
8
PA7-0
GPLB52640A GPLB52320A GPLB51640A GPLB51320A
PB7-0
Max.16
I/O Ports
LCD RAM 512 bytes
Segment
Common
LCD
64
32
64
32
74
22
74
22
22 Commons X 74 Segments 4-gray-level/mono LCD
Driver
COM21-0
SEG73-0
2048
2048
1628
1628
Dots
– 4-gray-level or mono LCD, 1/3, 1/4, 1/5, 1/6, 1/7 bias
capability
2.4. GPLB51320A
32KHz
– Supports from 1/2 duty up to 1/32 duty
– 512 bytes dedicated LCD RAM
– Supports normal type-B & type-C LCD waveform with or
without key scan
ROSC/XI
XO
32KHz
10-bit PWM
Driver
R-Oscillator/Xtal
AUDA
AUDB
32 KHz
Oscillator
&
System Clock Gen.
12-bit DAC
Driver
DACO
Time base
– Built-in voltage regulator to generate VLCD for LCD driver
– 32-level contrast control (VLCD=2.95V~6.85V)
– Power saving SLEEP mode
CSN/PB4
Power Supply
Voltage Detector
SCK/PB5
SDO/PB6
SDI/PB7
SPI
Two 16-bit /
Auto-reload
Timers
320K bytes
ROM
Low Voltage Detector
4-level (2.4V/2.6V/3.0V/3.3V) voltage detector
2.2V Low Voltage Reset
SPU
8-bit
Peripherals
micro-processor
1536 bytes
RAM
(I/O)
– Max. 16 I/O pins (PA[7:0], PB[7:0])
– Built-in 32.768KHz oscillator circuit for real time clock
function (X’tal or R-osc)
8
8
PA7-0
PB7-0
Max.16
I/O Ports
LCD RAM 512 bytes
22 Commons X 74 Segments 4-gray-level/mono LCD
Driver
– Built-in R-oscillator for system operating clock (X’tal or
R-osc)
COM21-0
SEG73-0
– Internal time base generator
– Two 16-bit reloadable timer/counters
– Watchdog timer
3. FEATURES
– 12-bit DAC output and 10-bit PWM audio outputs
– Key scan function
8-bit micro-processor
1536 bytes SRAM
ROM Size Table:
– SEG[15:0] can be used to send key scan output
– IR carrier output
– One SPI serial interface I/O
GPLB52640A GPLB52320A GPLB51640A GPLB51320A
Powerful 8-ch Sound Processing Unit (SPU)
– Variable tone-color sampling rate: maximum
54KHz@CPU_Clock=7MHz
ROM
Size
640K bytes 320K bytes 640K bytes 320K bytes
Operating voltage: 2.4V – 5.5V
– 8-voice polyphony
© Generalplus Technology Inc.
Proprietary & Confidential
5
Sep 12, 2013
Version: 2.2
GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
4. APPICATION FIELD
– Supports PCM/ADPCM tone-color table
Handheld LCD game
Educational toys (Electronic Learning Aid)
Data bank
Dictionary
Translator
© Generalplus Technology Inc.
Proprietary & Confidential
6
Sep 12, 2013
Version: 2.2
GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
5. SIGNAL DESCRIPTIONS
5.1. GPLB52640A/GPLB52320A
Mnemonic
PIN No.
Type
Description
SEG63 – 55
SEG54 – 0
COM22 – 31
COM21 – 16
COM15 – 0
PA7 – 0
131-139
1-55
O
LCD driver segment output. SEG15 - 0 share pin with key scan port.
121-130
120-115
56-71
O
O
LCD driver common output.
LCD driver common output.
92-85
I/O
PA7-0 is a bi-directional I/O port, which can be software programmed as
wake up I/O.
PB0/ECLK
PB1/EXTI
PB2
77
78
79
80
81
82
83
84
97
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PB0 is shared pin with external timer clock input ECLK.
PB1 is shared pin with external timer clock input EXTI.
PB2 is a bi-directional I/O port.
PB3
PB3 is shared pin with IR carrier output IRO.
PB4 is shared pin with SPI chip select SPI_CSN.
PB5 is shared pin with SPI clock output SCK.
PB6 is shared pin with SPI data output SDO.
PB7 is shared pin with SPI data input SDI.
Crystal input or ROSC input, connect to VDD (3V) through a resistor
(option).
PB4/SPI_CSN
PB5/SCK
PB6/SDO
PB7/SDI
ROSC/XI
XO
96
99
O
I
Crystal output.
RESETB
AUDA, AUDB
DACO
System reset input, low active.
76, 73
72
O
O
I
PWM audio output.
DAC output.
X32I
100
32.768KHz crystal input or connects to VDD (3V) through a resistor
(option).
X32O
101
102
O
I
32.768KHz crystal output.
TEST
Test input. Reserved for Generalplus testing.
LCD voltage generator. Charge pump capacitor interconnection pins.
LCD voltage generator. Charge pump capacitor interconnection pins.
LCD voltage generator. Voltage generated by charge pump.
LCD voltage generator.
CAP1P, CAP1N
CAP2P, CAP2N
VOUT
V4
105, 106
107, 108
109
P
P
P
P
P
P
P
P
P
P
P
P
P
111
V3
112
LCD voltage generator.
V2
113
LCD voltage generator.
V1
114
LCD voltage generator.
VLCD
VDD5V
VSSO
VDDA
VSSA
VDD
110
LCD voltage generator. The highest voltage for LCD display.
Positive supply for regulator input.
94
93
Ground for regulator.
104
Power for Charge pump and IO pins.
Ground for Charge pump and IO pins.
3.3V power output from regulator. Regulator can be turned off when
external 3.3V is supplied.
103
95
VSS
98
75
74
P
P
P
Ground reference for logic.
PVDD
PVSS
Positive supply for PWM driver.
Ground reference for PWM driver.
Legend: I = Input, O = Output, P = Power
© Generalplus Technology Inc.
Proprietary & Confidential
7
Sep 12, 2013
Version: 2.2
GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
5.2. GPLB51640A/GPLB51320A
Mnemonic
PIN No.
Type
Description
SEG63 – 55
SEG54 – 0
SEG73 – 64
COM21 – 16
COM15 – 0
PA7 – 0
131-139
1-55
O
LCD driver segment output. SEG15 - 0 share pin with key scan port.
121-130
120-115
56-71
O
O
LCD driver segment output.
LCD driver common output.
92-85
I/O
PA7-0 is a bi-directional I/O port, which can be software programmed as
wake up I/O.
PB0/ECLK
PB1/EXTI
PB2
77
78
79
80
81
82
83
84
97
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PB0 is shared pin with external timer clock input ECLK.
PB1 is shared pin with external timer clock input EXTI.
PB2 is a bi-directional I/O port.
PB3
PB3 is shared pin with IR carrier output IRO.
PB4 is shared pin with SPI chip select SPI_CSN.
PB5 is shared pin with SPI clock output SCK.
PB6 is shared pin with SPI data output SDO.
PB7 is shared pin with SPI data input SDI.
Crystal input or ROSC input, connect to VDD (3V) through a resistor
(option).
PB4/SPI_CSN
PB5/SCK
PB6/SDO
PB7/SDI
ROSC/XI
XO
96
99
O
I
Crystal output.
RESETB
AUDA, AUDB
DACO
System reset input, low active.
76, 73
72
O
O
I
PWM audio output.
DAC output.
X32I
100
32.768KHz crystal input or connects to VDD (3V) through a resistor
(option).
X32O
101
102
O
I
32.768KHz crystal output.
TEST
Test input. Reserved for Generalplus testing.
LCD voltage generator. Charge pump capacitor interconnection pins.
LCD voltage generator. Charge pump capacitor interconnection pins.
LCD voltage generator. Voltage generated by charge pump.
CAP1P, CAP1N
CAP2P, CAP2N
VOUT
V4
105, 106
107, 108
109
P
P
P
P
P
P
P
P
P
P
P
P
P
111
LCD voltage generator.
LCD voltage generator.
LCD voltage generator.
LCD voltage generator.
.
.
.
.
V3
112
V2
113
V1
114
VLCD
VDD5V
VSSO
VDDA
VSSA
VDD
110
LCD voltage generator. The highest voltage for LCD display.
Positive supply for regulator input.
94
93
Ground for regulator.
104
Power for charge pump and IO pins.
Ground for Charge pump and IO pins.
3.3V power output from regulator. Regulator can be turned off when
external 3.3V is supplied.
103
95
VSS
98
75
74
P
P
P
Ground reference for logic.
PVDD
PVSS
Positive supply for PWM driver.
Ground reference for PWM driver.
Legend: I = Input, O = Output, P = Power
© Generalplus Technology Inc.
Proprietary & Confidential
8
Sep 12, 2013
Version: 2.2
GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
6. FUNCTIONAL DESCRIPTIONS
6.1. Memories
The GPLB52640A and GPLB51640A contain 640K-byte ROM and 1536-byte SRAM.
The GPLB52320A and GPLB51320A contain 320K-byte ROM and 1536-byte SRAM.
6.2. Map of Memory and I/Os
6.2.1. GPLB52640A/GPLB51640A
*NMI SOURCE:
- LV DETECT
C P U View
$00000 - $03FFF
0L
- TIMER1
S P U R A M
0
$04000 - $07FFF
$08000 - $0B FFF
$0C 000 - $0FFFF
$10000 - $13FFF
$14000 - $17FFF
0H
1L
G P R A M
$0000-$0600
$1000-$1FFF
*INT SOURCE:
- TBL (2/4/8/16Hz)
- TBH (128/256/512/1KHz)
- TIMER0
1
1H
D PR AM
2L
2
2H
- TIMER1
IO R eg
$3000-$3FFF
- SPI
. . .
- SPU
R O M
$4000-
$7FFF
- FP (LCD frame)
(Bank)L
$98000 - $9BFFF
$9C 000 - $9FFFF
19L
19H
19
256
R O M
$8000-
$BFFF
(B ank)H
SPU table , Test
program
$C 000-$C BB F
$C B C 0-C BFF
TEST interrupt
vector
R O M
$C C 00-$FFBF
$FFC 0-$FFE F
interrupt vector
N M I and reset
vector
$FFFA -$FFFD
$FFFE -$FFFF
B ank A ddress: $0
$C 000-$FFFF alw ays m apping into 0L
1. User program starts from $CC00. $C000-$CBFF is the test program area. $C000-$C103 is SPU ADPCM table data.
2. User program interrupt vector: $FFC0 ~ $FFEF.
3. Test program interrupt vector: $CBC0 ~ $CBFF.
© Generalplus Technology Inc.
Proprietary & Confidential
9
Sep 12, 2013
Version: 2.2
GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
6.2.2. GPLB52320A/GPLB51320A
*NMI SOURCE:
- LV DETECT
- TIMER1
C P U
V iew
$00000 - $03FFF
0L
S P U R A M
G P R A M
0
$04000 - $07FFF
$08000 - $0B FFF
$0C 000 - $0FFFF
$10000 - $13FFF
$14000 - $17FFF
0H
1L
$0000-$0600
*INT SOURCE:
- TBL (2/4/8/16Hz)
- TBH (128/256/512/1KHz)
- TIMER0
1
1H
$1000-$1FFF
$3000-$3FFF
D P R A M
IO R eg
2L
2
2H
- TIMER1
- SPI
. . .
- SPU
R O M
$4000-
$7FFF
- FP (LCD frame)
(B ank)L
$48000 - $4B FFF
$4C 000 - $4FFFF
9L
9H
9
256
R O M
$8000-
$B FFF
(B ank)H
S P U table , Test
program
$C 000-$C BB F
$C B C 0-C BFF
TE S T interrupt
vector
R O M
$C C 00-$FFB F
$FFC 0-$FFE F
interrupt vector
N M I and reset
vector
$FFFA -$FFFD
$FFFE -$FFFF
B ank A ddress: $0
$C 000-$FFFF alw ays m apping into 0L
1. User program starts from $CC00. $C000-$CBFF is the test program area. $C000-$C103 is SPU ADPCM table data.
2. User program interrupt vector: $FFC0 ~ $FFEF.
3. Test program interrupt vector: $CBC0 ~ $CBFF.
6.3. Operating States
6.3.2. Standby Mode
There are three operation modes in GPLB52640A/ GPLB52320A/
GPLB51640A/ GPLB51320A: standby, halt and operating mode.
The following table shows the differences between these modes.
Write “07H” to P_3001H_ClkCtrl Register ($3001) and activate
standby mode by turning off 32768Hz oscillator. The standby
mode is a mode where the device is placed in its lowest current
consumption state. In standby mode, all functions are turned off;
in addition, RAM and I/Os will remain in their previous states.
Operating
ON
Halt
OFF
Standby
OFF
CPU
32768Hz oscillator
LCD driver
ON
ON
OFF
6.3.3. Halt Mode
ON
ON/OFF
OFF
Write “07H” to P_3001H_ClkCtrl Register ($3001) but still keeps
32768Hz oscillator running to enter halt mode. In halt mode,
CPU clock halts and waits for an event (e.g. key press, timer
overflow) to wake up. The 32768Hz related functions, such as
timer/counter and LCD driver, may remain active in the halt mode.
The following figure is the GPLB52640A/GPLB52320A/
GPLB51640A/ GPLB51320A state diagram:
6.3.1. Operating Mode
In operating state, all functions (CPU, 32768Hz oscillator,
timer/counter, LCD driver…) are activated. Generally speaking,
this mode consumes the highest power.
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GPLB52640A/GPLB52320A/
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provide LCD panel’s power supply, VLCD. The level of VLCD
can be adjusted by software. It is suggested that VLCD must be
0.7V higher than VDD or abnormal operation will occur.
Write $07h to
CPU_Clk_Ctrl register,
32768 oscillator OFF
OPERATING
STANDBY
Wake-up or user reset
6.7. Low Voltage Detection
The GPLB52640A/ GPLB52320A/ GPLB51640A/ GPLB51320A
provide a 4-level (Software programmable) low voltage detector to
detect low voltage events. Users can turn on the low voltage
detection to monitor VDD periodically, checking if it is lower than
the given value. In addition, if LV NMI is enabled, an NMI will be
issued to notify CPU if power voltage drops below the given value.
Also, the voltage detector will generate a system reset if power
supply voltage drops below 2.2V.
HALT
GPLB52640A/GPLB52320A/GPLB51640A/GPLB51320A State Diagram
6.4. Speech and Melody, PWM and DAC
6.8. Watchdog Timer (WDT)
The GPLB52640A/ GPLB52320A/ GPLB51640A/ GPLB51320A
use a high performance SPU voice engine to archive 8-channel
voice with ADPCM/PCM code. The SPU also supports automatic
zero-crossing concatenate function. A hardware multiplier is also
embedded in this SPU for software usage. The fixed address of
RAM area $0000 - $007F is designed as address pointers and a
data buffer for the 8-channel speech/melody generator. There is
one 12-bit D/A converter with 4mA driving current capability for
audio output, DACO. There is one 10-bit PWM for audio outputs,
AUDA and AUDB.
An on-chip watchdog timer is also available in the GPLB52640A/
GPLB52320A/ GPLB51640A/ GPLB51320A.
The WDT is
designed to recover system from unexpected operations. In
some cases, if WDT is not cleared within one second, the WDT
will generate a system reset to restart system. If WDT is enabled,
the WDT should be cleared periodically to avoid accidental reset.
The WDT can be cleared through software programming. Note
that the WDT only works when 32768Hz clock is activated.
6.9. SPI Controller
A
Serial Peripheral Interface (SPI) controller is built in
6.5. LCD Controller/Driver
GPLB52640A/ GPLB52320A/ GPLB51640A/ GPLB51320A to
facilitate communication with other devices. There are four
control signals on SPI, including SPICSN, SPICLK (SCK), SPIRX
(SDI), and SPITX (SDO). The four signals are shared with
PortB4, PortB5, PortB6 and PortB7. While SPI module is
enabled by corresponding control bit, these four pins cannot be
GPIOs, and any setting on corresponding GPIO control register
will have no effect. Four types of operation modes are supported
as follows:
The GPLB52640A/ GPLB52320A/ GPLB51640A/ GPLB51320A
contain a LCD controller/driver and support monochrome and 4
gray LCD control. The GPLB52640A/GPLB52320A contain up to
64 segments and 32 commons, forming a maximum of 2048 dots
LCD resolution, and the GPLB51640A/GPLB51320A contain up to
74 segments and 22 commons, forming a maximum of 1628 dots
LCD. Programmers are able to define the LCD configuration by
setting up the LCD Control Register. Once the LCD configuration
is completed, the desired pattern can be displayed by filling the
LCD buffer with proper data. The LCD driver can also operate
during sleep by keeping 32768Hz oscillator running. The LCD
driver in GPLB52640A/GPLB52320A/GPLB51640A/GPLB51320A
supports 1/2 – 1/32 duty and 1/3 - 1/7 bias.
6.6. LCD Voltage Generation
To achieve highly integrated circuit and save external components
as possible, the GPLB52640A/ GPLB52320A/ GPLB51640A/
GPLB51320A has built-in charge pump circuit and operational
amplifiers to generate LCD’s bias voltages VLCD, V4, V3, V2 and
V1. The charge pump circuit can generate VPP approx. to 8V.
With VPP as power source, an operational amplifier is further to
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GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
SPICLK
SPICLK
SPICSN
SPIRX
SPICSN
SPIRX
MSB
MSB
LSB
LSB
Q
MSB
MSB
LSB MSB
LSB MSB
SPITX
SPIOE
SPITX
SPIOE
8 bits
8 bits
Master Mode, SPO = 1, SPH=0
Master Mode, SPO = 0, SPH=0
SPICLK
SPICLK
SPICSN
SPIRX
SPICSN
SPIRX
Q
MSB
LSB
Q
Q
MSB
LSB
LSB
Q
SPITX
SPIOE
SPITX
SPIOE
LSB
MSB
MSB
8 bits
8 bits
Master Mode, SPO = 1, SPH=1
Master Mode, SPO = 0, SPH=1
6.10. Mask Options
6.10.1. 32768 Oscillator
1). X’TAL
2). R-oscillator
6.10.2. System Clock Oscillator
1). R-oscillator
2). X’TAL
6.10.3. Internal VDD Regulator
1). Internal VDD regulator on
2). Internal VDD regulator off
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GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
DC Supply Voltage
Input Voltage Range
Operating Temperature
Storage Temperature
Symbol
V+
Ratings
< 7.0V
VIN
-0.5V to V+ + 0.5V
0℃ to +70℃
TA
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions
see AC/DC Electrical Characteristics.
7.2. DC Characteristics (VDD5V=5.0V, for 3-battery application, internal regulator enabled output, TA=25℃)
Limit
Characteristics
Operating Voltage
Symbol
Unit
Test Condition
Min.
Typ.
Max.
VDD5V
2.7
-
5.5
V
For 3-battery
F
CPU = 6.0MHz @ 5.0V
XTAL = 12.0MHz, no load, DAC disabled,
IOP1
-
-
-
4
5
-
-
-
mA
mA
μA
F
PWM disabled.
CPU = 8.0MHz @ 5.0V
FROSC 16.0MHz, no load, DAC
Operating Current
F
IOP2
=
disabled, PWM disabled.
VDD5V = 5.0V, 32K X’tal ON, Strobe off,
LCD ON, 1/7 Bias, VLCD=6.85V, no
LCD panel
Halt Current
IHALT
100
Standby Current (Regulator on)
PWM Audio Output Current
ISTBYR
IOH
-
-
-30
-60
30
60
-
10
μA
mA
mA
mA
mA
V
VDD5V = 5.0V, VDD regulator on, all off
VDD5V = 5.0V, VOH = 4.5V
VDD5V = 5.0V, VOH = 4.0V
VDD5V = 5.0V, VOL = 0.5V
VDD5V = 5.0V, VOL = 1.0V
VDD5V = 5.0V
-
-
-
-
-
-
PWM Audio Output Current
IOL
-
0.7VDD
-
-
Input High Level
Input Low Level
Output High Current (I/O)
Output Sink Current (I/O)
Input Pull-Low Resistor
PA(weak pull)
VIH
VIL
IOH
IOL
-
-
0.3VDD
V
VDD5V = 5.0V
-1.0
1.0
-
-
-
mA
mA
VDD5V = 5.0V, VOH = 4.5V
VDD5V = 5.0V, VOL = 0.5V
-
250
100
80
RPL
-
-
-
-
KΩ
KΩ
VIN = 5.0V
PA(strong pull)
PB,PC
Input Pull-High Resistor
PA(weak pull)
160
50
50
-
RPH
VIN = 0V
PA(strong pull)
PB,PC
LCD Driver Voltage
(VLCD - VSS)
2.98
5.75
6.85
-
V
V
VDD5V = 5.0V, 1/5 bias, no load
VDD5V = 5.0V, 1/6 bias, no load
FOSC = 14MHz @ 5.0V
VLCD
2.95
-
OSC Resistor
ROSC
FCPU
-
-
33
-
KΩ
MHz
CPU Clock
8.0
FCPU = FOSC/2 @ 2.4V
Note: VLCD should be higher than VDD to prevent forward biasing the p-n junction of I/O output PMOS.
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7.3. DC Characteristics (VDD5V=VDD=3.0V, for 2-battery application, internal regulator output disabled, TA=25℃)
Limit
Characteristics
Operating Voltage
Symbol
Unit
Test Condition
Min.
Typ.
Max.
VDD5V
2.4
-
3.6
V
For 2-battery
CPU = 6.0MHz @ 3.0V
F
IOP1
-
-
-
4
5
-
-
-
mA
mA
μA
FXTAL = 12.0MHz, no load, DAC disabled,
PWM disabled.
Operating Current
FCPU = 8.0MHz @ 3.0V
IOP2
FROSC 16.0MHz, no load, DAC
=
disabled, PWM disabled.
VDD5V = 3.0V, 32K X’tal ON, Strobe off,
LCD ON, 1/7 Bias, VLCD=6.85V, no
LCD panel
Halt Current
IHALT
80
Standby Current (Regulator off)
PWM Audio Output Current
ISTBY
IOH
-
-
-20
-40
20
40
-
1.0
μA
mA
mA
mA
mA
V
VDD5V = 3.0V, all off
-
-
VDD5V = 3.0V, VOH = 2.5V
VDD5V = 3.0V, VOH = 2.0V
VDD5V = 3.0V, VOL = 0.5V
VDD5V = 3.0V, VOL = 1.0V
VDD5V = 3.0V
-
-
-
-
PWM Audio Output Current
IOL
-
0.7VDD
-
-
Input High Level
Input Low Level
Output High Current (I/O)
Output Sink Current (I/O)
Input Pull-Low Resistor
PA(weak pull)
VIH
VIL
IOH
IOL
-
-
0.3VDD
V
VDD5V = 3.0V
-1.0
1.0
-
-
-
mA
mA
VDD5V = 3.0V, VOH = 2.5V
VDD5V = 3.0V, VOL = 0.5V
-
180
60
RPL
-
-
-
-
KΩ
KΩ
VIN = 3.0V
PA(strong pull)
PB,PC
60
Input Pull-High Resistor
PA(weak pull)
300
70
100
-
RPH
VIN = 0V
PA(strong pull)
PB,PC
LCD Driver Voltage
(VLCD - VSS)
2.98
5.75
6.85
-
V
V
VDD5V = 3.0V, 1/5 bias, no load
VDD5V = 3.0V, 1/6 bias, no load
FOSC = 14MHz @ 3.0V
VLCD
2.95
-
OSC Resistor
ROSC
FCPU
-
-
33
-
KΩ
MHz
CPU Clock
8.0
FCPU = FOSC/2 @ 2.4V
Note: VLCD should be higher than VDD to prevent forward biasing the p-n junction of I/O output PMOS.
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GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
7.5.2. VDD = 4.5V, TA = 25℃
7.4. The Relationship between the ROSC and the FOSC
7.4.1. VDD = 3.0V, TA = 25℃
R32K v.s F32K (VDD=4.5V)
120
100
80
60
40
20
0
0
0.5
1
1.5
2
2.5
3
3.5
R32K (MΩ)
7.6. The Relationships between the FCPU and the IOP
7.4.2. VDD = 4.5V, TA = 25℃
Rosc vs Fosc (VDD=4.5v)
7.6.1. VDD = 3.0V, TA = 25℃
Fcpu vs Iop (3.0v)
20
15
10
5
5
4
3
2
1
0
0
0
50
100
150
200
Rosc(KΩ)
0
5
10
15
20
Fcpu(MHz)
7.5. The Relationship between the F32K and the R32K
7.5.1. VDD = 3.0V, TA = 25℃
R32K v.s F32K (VDD=3.0V)
120
100
80
60
40
20
0
0
0.5
1
1.5
2
2.5
3
3.5
R32K (MΩ)
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GPLB52640A/GPLB52320A/
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7.7. DAC Characteristics (VDD5V = 5.0V, TA = 25℃)
Limit
Typ.
-
Characteristics
Resolution of DAC
Symbol
Unit
Min.
Max.
RESO
-
-
-
-
-
12
bit
dB
THD+N
SNR
<-60
-80
-75
-
-
Noise at no signal
Dynamic range(-60dB)
Sample Rate
-
-
-
-
dBr A
dBr A
Hz
FS
400K
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8. APPLICATION CIRCUITS
8.1. 2048 Dots LCD Driver, using GPLB52640A or GPLB52320A, 64 Segments × 32 Commons, for 3-battery
application, Internal 3.3V Regulator Enabled, 10-bit PWM Driver Enabled, ROSC14M XTAL32K Selected- (1)
LCD Panel (32x64)
VDDB
AUDA
AUDB
PVDD
PVSS
(PWM Power)
(PWM Ground)
0.1μF
20pF * 1
X32I
VDD5V
VDDA
X32O
20pF * 1
GPLB52640A
VSSB
GPLB52320A
VDD
0.1u
47u
10u
VSSO
VSS
RESET
VSSA
VSSB
0.1μF
8
VSSB
VSSB
SEG0
* 2
SEG1
SEG2
SEG14
SEG15
1/3, 1/4, 1/5,1/6, 1/7 Bias
0.1 F
V1
0.1 F
V2
.....
0.1 F
V3
0.1 F
0.1 F
1uF
V4
VLCD
VOUT
.....
PA1
PA2
PA3
PA4
CAP1P
0.1 F
0.1 F
CAP1N
CAP2P
CAP2N
VSSB
.....
.....
.....
.....
Note*1: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading; for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
Note*2: These capacitor values are for design guidance only. The ratio of capacitance of VOUT to the capacitance of CAP1N/CAP1P/CAP2N/CAP2P is
recommended to be 10:1. Generally, capacitance of VLCD and V1~V4 is 0.1uF and can’t be greater than capacitance of VOUT. But in a larger LCD panel,
1uF capacitance for VLCD and V1~V4, 2.2uF capacitance for VOUT and 0.22uF capacitance for CAP1P/CAP1N/CAP2P/CAP2N is recommended.
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GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
8.2. 2048 Dots LCD Driver, using GPLB52640A or GPLB52320A, 64 Segments × 32 Commons, Internal 3.3V
Regulator Disabled, for 2-battery application, 12-bit DAC Enabled, ROSC14M XTAL32K Selected - (2)
LCD Panel (32x64)
* 1
VDDB
VDD5V
VDD
GPLB52640A
GPLB52320A
20pF * 2
VDDA
X32I
47u
VSSO
VSS
Speaker
SPN
SPP
VSS
INN
VDD
X32O
IO port
DACO
20pF * 2
VSSB
CE
VSSA
VSSB
VSSB
GPY0030B
0.1
0.22u
VREF
ACIN
RESET
DACO
VSSB
R3
R4
1K
0.01u
470
C12
0.1μF
8
VSSB
VSSB
SEG0
SEG1
SEG2
SEG14
SEG15
* 3
1/3, 1/4, 1/5,1/6, 1/7 Bias
.....
0.1
0.1
0.1
0.1
0.1
1uF
F
V1
V2
V3
V4
VLCD
VOUT
F
F
F
F
.....
PA1
.....
.....
CAP1P
CAP1N
CAP2P
CAP2N
PA2
PA3
PA4
PA5
0.1
0.1
F
VSSB
F
.....
.....
Note*1: VDD should not exceed 3.6V.
Note*2: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading; for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
Note*3: These capacitor values are for design guidance only. The ratio of capacitance of VOUT to the capacitance of CAP1N/CAP1P/CAP2N/CAP2P is
recommended to be 10:1. Generally, capacitance of VLCD and V1~V4 is 0.1uF and can’t be greater than capacitance of VOUT. But in a larger LCD panel,
1uF capacitance for VLCD and V1~V4, 2.2uF capacitance for VOUT and 0.22uF capacitance for CAP1P/CAP1N/CAP2P/CAP2N is recommended.
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Version: 2.2
GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
8.3. 2048 Dots LCD Driver, using GPLB52640A or GPLB52320A, 64 Segments × 32 Commons, for 3-battery
application, Internal 3.3V Regulator Enabled, 10-bit PWM Driver Enabled, XTAL12M ROSC32K Selected - (3)
Note*1: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
Note*2: These capacitor values are for design guidance only. The ratio of capacitance of VOUT to the capacitance of CAP1N/CAP1P/CAP2N/CAP2P is
recommended to be 10:1. Generally, capacitance of VLCD and V1~V4 is 0.1uF and can’t be greater than capacitance of VOUT. But in a larger LCD panel,
1uF capacitance for VLCD and V1~V4, 2.2uF capacitance for VOUT and 0.22uF capacitance for CAP1P/CAP1N/CAP2P/CAP2N is recommended.
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Version: 2.2
GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
8.4. 1628 Dots LCD Driver, using GPLB51640A or GPLB51320A, 74 Segments × 22 Commons, for 3-battery
application, Internal 3.3V Regulator Enabled, 10-bit PWM Driver Enabled, ROSC14M XTAL32K Selected- (1)
LCD Panel (22x74)
VDDB
AUDA
AUDB
PVDD
PVSS
(PWM Power)
(PWM Ground)
0.1μF
20pF* 1
X32I
VDD5V
VDDA
X32O
20pF* 1
GPLB51640A
VSSB
GPLB51320A
VDD
0.1u
47u
10u
VSSO
VSS
RESET
VSSA
VSSB
0.1μF
8
VSSB
VSSB
SEG0
SEG1
SEG2
SEG14
SEG15
.....
* 2
1/3, 1/4, 1/5,1/6, 1/7 Bias
0.1 F
V1
.....
0.1 F
V2
PA1
0.1 F
V3
0.1 F
V4
VLCD
VOUT
.....
.....
0.1 F
1uF
PA2
PA3
PA4
PA5
CAP1P
CAP1N
CAP2P
CAP2N
0.1 F
0.1 F
VSSB
.....
.....
Note*1: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading; for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
Note*2: These capacitor values are for design guidance only. The ratio of capacitance of VOUT to the capacitance of CAP1N/CAP1P/CAP2N/CAP2P is
recommended to be 10:1. Generally, capacitance of VLCD and V1~V4 is 0.1uF and can’t be greater than capacitance of VOUT. But in a larger LCD panel,
1uF capacitance for VLCD and V1~V4, 2.2uF capacitance for VOUT and 0.22uF capacitance for CAP1P/CAP1N/CAP2P/CAP2N is recommended.
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Version: 2.2
GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
8.5. 1628 Dots LCD Driver, using GPLB51640A or GPLB51320A, 74 Segments × 22 Commons, for 2-battery
application, Internal 3.3V Regulator Disabled, 12-bit DAC Enabled, ROSC14M XTAL32K Selected - (2)
LCD Panel (22x74)
* 1
VDDB
VDD5V
VDD
20pF * 2
GPLB51640A
GPLB51320A
VDDA
X32I
47u
VSSO
VSS
Speaker
SPN
SPP
VSS
INN
VDD
X32O
IO port
DACO
20pF * 2
VSSB
CE
VSSA
VSSB
VSSB
GPY0030B
0.1
0.22u
VREF
ACIN
RESET
DACO
VSSB
R3
R4
1K
0.01u
470
C12
0.1μF
8
VSSB
VSSB
SEG0
SEG1
SEG2
SEG14
SEG15
* 3
1/3, 1/4, 1/5,1/6, 1/7 Bias
.....
0.1
0.1
0.1
0.1
0.1
1uF
F
V1
V2
V3
V4
VLCD
F
F
F
F
.....
PA1
VOUT
.....
.....
CAP1P
PA2
PA3
PA4
PA5
0.1
0.1
F
VSSB
CAP1N
CAP2P
CAP2N
F
.....
.....
Note*1: VDD should not exceed 3.6V.
Note*2: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading; for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
Note*3: These capacitor values are for design guidance only. The ratio of capacitance of VOUT to the capacitance of CAP1N/CAP1P/CAP2N/CAP2P is
recommended to be 10:1. Generally, capacitance of VLCD and V1~V4 is 0.1uF and can’t be greater than capacitance of VOUT. But in a larger LCD panel,
1uF capacitance for VLCD and V1~V4, 2.2uF capacitance for VOUT and 0.22uF capacitance for CAP1P/CAP1N/CAP2P/CAP2N is recommended.
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Version: 2.2
GPLB52640A/GPLB52320A/
GPLB51640A/GPLB51320A
8.6. 1628 Dots LCD Driver, using GPLB51640A or GPLB51320A, 74 Segments × 22 Commons, for 3-battery
application, Internal 3.3V Regulator Enabled, 10-bit PWM Driver Enabled, XTAL12M ROSC32K Selected - (3)
Note*1: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
Note*2: These capacitor values are for design guidance only. The ratio of capacitance of VOUT to the capacitance of CAP1N/CAP1P/CAP2N/CAP2P is
recommended to be 10:1. Generally, capacitance of VLCD and V1~V4 is 0.1uF and can’t be greater than capacitance of VOUT. But in a larger LCD panel,
1uF capacitance for VLCD and V1~V4, 2.2uF capacitance for VOUT and 0.22uF capacitance for CAP1P/CAP1N/CAP2P/CAP2N is recommended.
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8.7. DAC Output with Generalplus Audio Driver GPY0030B (for high quality audio output) - (4)
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8.8. Current Mode DAC Speaker Driver with BJT- (5)
VDD5V
RB1: 10K ~ 50K
RB2: 820 ~ 1.5K
VDD5V
C1: 0.1 F ~ 1 F
RB1: 680 ~ 1.5K
C1: 0.1 F ~ 1
F
4
~ 8
32
~ 64
RB1
C1
DACO
C1
DACO
RB2
8050
8050
RB1
Figure 1
Figure 2
VDD5V
VDD5V
RB1: 2K~10K C1: 1 F~10
RB2: ~ 1K C2: ~ 0.1 F
F
RB1: 2K~10K C1: 1 F~10 F
RB2: ~ 1K
C2: ~ 0.1 F
4
~8
4
~64
RB
C2
Enable
C2
DACO
RB1
DACO
8050
8050
C1
C1
RB2
RB2
Figure 3
Figure 4
VDD5V
RB1: ~ 360 (Vol)
RE1: ~ 4.7
4
~64
DACO
8050
RE1
1N4148
RB1
Figure 5
Figure 1: The simplest CKT uses with low impedance speaker. It has high operation current, but the cost is the cheapest.
Figure 2: It is the same as Figure 1 but a high impedance speaker is used.
Figure 3: The CKT has low pass filter. It can provide higher speech quality, but it always takes high operation current.
Figure 4: Improved version of Figure 3. The standby current can be controlled by enable pin.
Figure 5: The current mirror mode. It is able to control the volume. In addition, it has more stable and lower operation current than Figure 1-3.
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8.9. Serial Communications between GPLB52640A/GPLB52320A/GPLB51640A/GPLB51320A and GPUSB101A USB
Controller- (6)
PB5
PB7
SPI_CLK
SPI_TX
GPLB52640A
GPLB52320A
GPLB51640A
GPLB51320A
GPUSB101A
SPI_RX
PB6
PB4
SPI_CSN
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9. PACKAGE/PAD LOCATIONS
9.1. Ordering Information
Product Number
Package Type
GPLB52640A - NnnV - C
GPLB52320A - NnnV - C
GPLB51640A - NnnV - C
GPLB51320A - NnnV - C
Chip form
Chip form
Chip form
Chip form
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
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10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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11. REVISION HISTORY
Date
Revision #
Description
update capacitance value of Xtal 32K in APCKT.
Page
Sep 12, 2013
Jul 12, 2012
Nov. 23, 2011
Dec. 30, 2010
Sep. 21, 2009
2.2
2.1
2.0
1.9
1.8
Modify note for application circuit about recommended capacitor's value.
Modify 7.2 & 7.3 DC Characteristics.
Modify 3. FEATURES.
17-22
13, 14
5
1. Modify 3. FEATURES.
5
2. Add 6.5 LCD Controller/Driver.
15
3. Add 6.6 LCD Voltage Generation.
15
4. Modify 8. APPLICATION CIRCUITS.
1. Modify 1.GENERAL DESCRIPTION.
2. Modify 6.2. Map of Memory and I/Os.
Modify 5. SIGNAL DESCRIPTION.
21, 22
4
Aug. 06, 2009
1.7
13-14
6, 7
17
May 19, 2009
Apr. 02, 2009
Mar. 10, 2009
Dec. 8, 2008
1.6
1.5
1.4
1.3
Modify the Absolute Maximum Ratings in section 7.1.
Modify section 8. APPLICATION CIRCUITS.
1. Modify section 3. FEATURES.
21-26
5
2. Modify section 7.2 and 7.3 DC Characteristics.
3. Modify section 8. APPLICATION CIRCUITS.
1. Modify section 5. SIGNAL DESCRIPTION.
2. Modify section 8.3 and 8.6 Application Circuits.
Modify section 8. APPLICATION CIRCUITS.
Release to 1.0
17
21-26
6, 7
23, 26
21
Oct. 24, 2008
1.2
Aug. 29, 2008
Jul. 22, 2008
Mar. 20, 2008
JAN. 08, 2008
1.1
1.0
0.2
0.1
31
Add body: GPLB52320A/GPLB51640A/GPLB51320A.
Preliminary data sheet.
24
17
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