GPM8F3108A-QL01x [GENERALPLUS]
44-Pin 8-bit Microcontroller with 32/16/8KB Flash Memory;
| 型号： | GPM8F3108A-QL01x |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 44-Pin 8-bit Microcontroller with 32/16/8KB Flash Memory 微控制器 |
| 文件： | 总114页 (文件大小：2183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPM8F3132A/3116A/3108A
44-Pin 8-bit Microcontroller with
32/16/8KB Flash Memory
Preliminary
Nov. 07, 2014
Version 0.6
Generalplus Technology Inc. reserves the right to change this documentation without prior notice. Information provided by Generalplus Technology Inc. is
believed to be accurate and reliable. However, Generalplus Technology Inc. makes no warranty for any errors which may appear in this document. Contact
Generalplus Technology Inc. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by Generalplus
Technology Inc. for any infringement of patent or other rights of third parties which may result from its use. In addition, Generalplus products are not
authorized for use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of the product may
reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
Preliminary
GPM8F3132A/3116A/3108A
Table of Contents
PAGE
Table of Contents ............................................................................................................................................................................................ 2
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 5
2. FEATURES.................................................................................................................................................................................................. 5
3. BLOCK DIAGRAM...................................................................................................................................................................................... 7
3.1. GPM8F3132A ..................................................................................................................................................................................... 7
3.2. GPM8F3116A ..................................................................................................................................................................................... 8
3.3. GPM8F3108A ..................................................................................................................................................................................... 9
4. SIGNAL DESCRIPTIONS ......................................................................................................................................................................... 10
4.1. PIN DESCRIPTIONS ............................................................................................................................................................................. 10
4.1.1. GPM8F3132A/3116A .............................................................................................................................................................. 10
4.1.2. GPM8F3108A ..........................................................................................................................................................................11
4.2. PIN MAP ............................................................................................................................................................................................ 12
5. FUNCTIONAL DESCRIPTIONS................................................................................................................................................................ 14
5.1. CENTRAL PROCESSING UNIT ............................................................................................................................................................... 14
5.1.1. CPU Introduction..................................................................................................................................................................... 14
5.1.2. CPU Features ......................................................................................................................................................................... 14
5.1.3. Arithmetic Logic Unit (ALU)..................................................................................................................................................... 14
5.1.4. Accumulator A register............................................................................................................................................................ 14
5.1.5. B register................................................................................................................................................................................. 14
5.1.6. Program Status Word (PSW) .................................................................................................................................................. 14
5.1.7. Program Counter (PC)............................................................................................................................................................ 14
5.2. MEMORY ORGANIZATION..................................................................................................................................................................... 15
5.2.1. Introduction ............................................................................................................................................................................. 15
5.2.2. Program Memory Allocation.................................................................................................................................................... 15
5.2.3. Data Memory Allocation.......................................................................................................................................................... 17
5.2.4. Memory Related SFR ............................................................................................................................................................. 18
5.2.4.1. Program write enable bit .............................................................................................................................................. 18
5.2.4.2. Data pointer registers................................................................................................................................................... 19
5.2.4.3. Stack pointer ................................................................................................................................................................ 19
5.3. SPECIAL FUNCTION REGISTERS(SFR) ................................................................................................................................................. 21
5.4. CLOCK SOURCE.................................................................................................................................................................................. 25
5.5. POWER SAVING MODE ........................................................................................................................................................................ 27
5.5.1. Introduction ............................................................................................................................................................................. 27
5.5.2. IDLE mode.............................................................................................................................................................................. 27
5.5.3. STOP mode ............................................................................................................................................................................ 27
5.6. INTERRUPT SYSTEM............................................................................................................................................................................ 29
5.6.1. Introduction ............................................................................................................................................................................. 29
5.7. RESET SOURCES ................................................................................................................................................................................ 34
5.7.1. Introduction ............................................................................................................................................................................. 34
5.7.2. Power-On Reset (POR) .......................................................................................................................................................... 34
5.7.3. Low Voltage Reset (LVR)........................................................................................................................................................ 34
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Preliminary Version: 0.6
Preliminary
GPM8F3132A/3116A/3108A
5.7.4. Pad Reset (PAD_RST)............................................................................................................................................................ 34
5.7.5. Watchdog Timer Reset (WDT_RST)....................................................................................................................................... 35
5.7.6. Other Reset Sources .............................................................................................................................................................. 35
5.8. I/O PORTS.......................................................................................................................................................................................... 40
5.8.1. Introduction ............................................................................................................................................................................. 40
5.9. TIMER MODULE................................................................................................................................................................................... 48
5.9.1. Introduction ............................................................................................................................................................................. 48
5.9.2. Timer 0/1 ................................................................................................................................................................................. 48
5.9.2.1. Timer 0: Mode 0 (13-Bit Timer/Counter)....................................................................................................................... 50
5.9.2.2. Timer 0: Mode 1 (16-Bit Timer/Counter)....................................................................................................................... 52
5.9.2.3. Timer 0: Mode 2 (8-bit Timer/Counter with Auto-reload Function) ............................................................................... 52
5.9.2.4. Timer 0: Mode 3 (Two 8-Bit Timers/Counters) ............................................................................................................. 54
5.9.2.5. Timer 1: Mode 0 (13-Bit Timer/Counter)....................................................................................................................... 55
5.9.2.6. Timer 1: Mode 1 (16-Bit Timer/Counter)....................................................................................................................... 56
5.9.2.7. Timer 1: Mode 2 (8-Bit Timer/Counter with Auto-reload Function)............................................................................... 57
5.9.2.8. Timer 1: Mode 3 ........................................................................................................................................................... 57
5.9.3. Timer 2 .................................................................................................................................................................................... 58
5.9.3.1. Timer mode .................................................................................................................................................................. 58
5.9.3.2. Reload of Timer 2......................................................................................................................................................... 59
5.9.3.3. Compare functions....................................................................................................................................................... 60
5.9.3.4. Capture functions......................................................................................................................................................... 61
5.9.3.5. Timer 2 Related Registers............................................................................................................................................ 63
5.10. UART0 .............................................................................................................................................................................................. 67
5.10.1. UART0: Mode 0 (Synchronous Shift register) .................................................................................................................... 67
5.10.2. UART0: Mode 1 (8-Bit UART, Variable Baud Rate, Timer1 Clock Source) ........................................................................ 67
5.10.3. UART0: Mode 2 (9-Bit UART, Fixed Baud Rate)................................................................................................................ 68
5.10.4. UART0: Mode 3 (9-Bit UART, Variable Baud Rate, Timer1 Clock Source) ........................................................................ 68
5.10.5. UART0 Related Registers .................................................................................................................................................. 68
5.11. SPI .................................................................................................................................................................................................... 70
5.12. ADC .................................................................................................................................................................................................. 74
5.12.1. ADC Control ....................................................................................................................................................................... 74
5.13. MOTOR CONTROL UNIT....................................................................................................................................................................... 78
5.13.1. Hall Sensors Detection and Built-in Comparators Control.................................................................................................. 89
5.13.2. Protective Circuits............................................................................................................................................................... 93
5.13.3. 16-bit Capture Unit Control................................................................................................................................................. 96
5.13.4. Interrupt Sources................................................................................................................................................................ 99
5.13.5. Sine-wave PWM control (only in GPM8F3132A) ............................................................................................................. 102
5.14. AUDIO UNIT ...................................................................................................................................................................................... 104
5.15. ALPHABETICAL LIST OF INSTRUCTION SET.......................................................................................................................................... 106
5.15.1. Arithmetic Operations....................................................................................................................................................... 106
5.15.2. Logic Operations .............................................................................................................................................................. 106
5.15.3. Boolean Operations.......................................................................................................................................................... 107
5.15.4. Data Transfers.................................................................................................................................................................. 107
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Preliminary
GPM8F3132A/3116A/3108A
5.15.5. Program Branches............................................................................................................................................................ 109
6. ELECTRICAL CHARACTERISTICS....................................................................................................................................................... 110
6.1. ABSOLUTE MAXIMUM RATINGS ...........................................................................................................................................................110
6.2. AC CHARACTERISTICS (TA = 25℃).....................................................................................................................................................110
6.3. DC CHARACTERISTICS (TA = 25℃).....................................................................................................................................................110
6.4. ADC CHARACTERISTICS (TA = 25℃) ..................................................................................................................................................110
6.4.1. 12 bit mode ............................................................................................................................................................................110
6.4.2. 8 bit mode ..............................................................................................................................................................................111
6.5. OP AND COMPARATORS CHARACTERISTICS (TA = 25℃)......................................................................................................................111
7. PACKAGE INFORMATION ..................................................................................................................................................................... 112
7.1. ORDERING INFORMATION ...................................................................................................................................................................112
7.2. PACKAGE INFORMATION .....................................................................................................................................................................112
7.2.1. LQFP 44.................................................................................................................................................................................112
8. DISCLAIMER........................................................................................................................................................................................... 113
9. REVISION HISTORY............................................................................................................................................................................... 114
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Preliminary Version: 0.6
Preliminary
GPM8F3132A/3116A/3108A
44-PIN 8-BIT MICROCONTROLLER WITH 32/16/8KB FLASH MEMORY
1. GENERAL DESCRIPTION
−
−
−
Stop mode Reset (STOP_RST)
Miss Clock Reset (MISS_CLK_RST)
Flash Related Error Reset (FLASH_ERR_RST)
GPM8F3132A/3116A/3108A, a highly integrated microcontroller,
integrates a pipelined 1T 8051 CPU, 1K/512/256-byte XRAM,
256-byte IDM SRAM, and 32/16/8K-byte program Flash memory.
It includes 34 programmable multi-functional I/Os, Timer0/1/2,
UART0, SPI (master), Motor control unit with built-in OP and
comparators, audio and one up to 8-channel of 12-bit ADC for
general-purpose application. It operates over a wide voltage
range of 2.4V - 5.5V with different clock sources. It has two
modes in power management unit. Moreover, there is one
on-chip debug circuit with two pins to facilitate full speed
in-system debug.
Programmable Watchdog Timer
−
−
−
A time-base generator
An event timer
System supervisor
I/O Ports
−
−
Max. 34 multifunction bi-directional I/Os
Each incorporate with pull-up resistor, pull-down resistor,
output high, output low or floating input, depending on
programmer’s settings on the corresponding registers
I/O ports with 20mA current sink
−
−
I/O ports with 8mA current drive
Two 16-bit Timer/Counter (Timer 0/1)
2. FEATURES
−
−
−
Timer mode with clock source selectable
Auto reload 8-bit timers
CPU
High speed, high performance 1T 8051
−
Externally gated event counters
z 100% software compatible with industry standard 8051
z Pipeline RISC architecture enables to execute
instructions 10 times faster than standard 8051
z Up to 24.5MHz clock operation
One Powerful Timer 2 with 16-bit Compare/Capture Unit
−
−
−
−
Timer mode with clock source selectable
Auto-reload 16-bit timers
Event capturing
Memories
Pulse width modulation and measurement
−
−
−
1K/512/256 bytes XRAM
UART0
256 bytes internal Data Memory (IDM) SRAM
32/16/8K bytes Flash with high endurance
z Minimum 200,000 program/erase cycles
z Minimum 20 years data retention
−
−
One synchronous mode
Three asynchronous modes
SPI (master mode)
−
−
−
Programmable phase and polarity of master clock
Programmable master SPI_CLK clock frequency
Max SPI clock: 6.125MHz (FOSC /4) @24.5MHz
−Programming read only level for software security
Clock Management
−
−
−
Internal oscillator: 24.5MHz±2% @ 2.4V~5.5V
External clock input max 24.5MHz
A/D converter
−
−
−
One 8-channel 8-bit resolution mode
Crystal input with 32768Hz or 1MHz~25MHz
One 8-channel 12-bit resolution mode
Power Management
Max conversion clock: 6.125MHz (FOSC /4) @24.5MHz
−
−
1 STOP mode for power saving
Motor Control Unit
1 IDLE mode for only peripheral operation
−
−
Programmable dead-time control
Interrupt Management
Built-in four comparators and OP control (three sensorless
comparators are available only in GPM8F3132A/3116A)
Built-in protective circuits
−
−
22 interrupt sources
Up to 6 external interrupt sources
−
−
−
Reset Management
16-bit capture unit control
−
−
−
−
−
Power On Reset (POR)
Low Voltage Reset (LVR)
Pad Reset (PAD_RST)
Sine-wave PWM control (only in GPM8F3132A)
Audio Module
24KHz output or 32KHz output @24.5MHz
Debug Unit
−
Watchdog Reset (WDT_RST)
Software Reset (S/W_RST)
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Preliminary
GPM8F3132A/3116A/3108A
Product Number
GPM8F3132A
GPM8F3116A
GPM8F3108A
Speed (MHz)
Operating Voltage (V)
Flash (Kbytes)
XRAM (bytes)
IDM (bytes)
24.5
2.4~5.5
32
24.5
2.4~5.5
16
24.5
2.4~5.5
8
1K
512
256
256
256
256
Timer
3
3
3
UART
1
1
1
1
SPI
1
1
Motor Control Unit
Sine-wave PWM
Three Sensorless Comparators
Built-in OP and Comparator
12-bit ADC
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
Yes
Yes
Yes
8-channel
34
8-channel
34
8-channel
34
IO
Package Type
LQFP44
LQFP44
LQFP44
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Preliminary
GPM8F3132A/3116A/3108A
3. BLOCK DIAGRAM
3.1. GPM8F3132A
RESET/SCK
SYSCLK
2WIRE
WRITER /ICE
OPCODE
DECODER
P42/SDA
IOSC
I/F
RESET/SCK
SRAM
256B
IDM I/F
ALU
EXTERNAL
DATA
MEMORY
I/F
XRAM
1KB
(max.)
SFR I/F
Flash
32KB
(max.)
FLASH
CONTROLLER
WATCHDOG
TIMER
GATE0
T0
TIMERS
POWER
MANAGEMENT
UNIT
0/1
GATE1
T1
T2EX
TXD0
UART 0
TIMER 2
RXD0
CAPTURE[3:0]
P4[1:0]
P0[7],P0[5:2]
P0[6]
SPITXD
OP_CMP
MACRO
MOTOR
CONTROLLER
SPI
SPIRXD
PWM[5:0]
P0[7:0]
P1[5:1]
P2[7:0]
P3[7:0]
P4[4:0]
INT[1:0]
INT[7:3]
INTERRUPT
CONTROLLER
I/O Port
CONTROLLER
P3[7:6]
P0[7:0]
ADC
MACRO
ADC
CONTROLLER
AUDIO
Figure 3-1 Block diagram of GPM8F3132A
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GPM8F3132A/3116A/3108A
3.2. GPM8F3116A
RESET/SCK
SYSCLK
2WIRE
WRITER /ICE
OPCODE
DECODER
P42/SDA
IOSC
I/F
RESET/SCK
SRAM
256B
IDM I/F
ALU
EXTERNAL
DATA
MEMORY
I/F
XRAM
512KB
(max.)
SFR I/F
Flash
16KB
(max.)
FLASH
CONTROLLER
WATCHDOG
TIMER
GATE0
T0
TIMERS
POWER
MANAGEMENT
UNIT
0/1
GATE1
T1
T2EX
TXD0
UART 0
TIMER 2
RXD0
CAPTURE[3:0]
P4[1:0]
P0[7],P0[5:2]
P0[6]
SPITXD
OP_CMP
MACRO
MOTOR
CONTROLLER
SPI
SPIRXD
PWM[5:0]
P0[7:0]
P1[5:1]
P2[7:0]
P3[7:0]
P4[4:0]
INT[1:0]
INT[6:3]
INTERRUPT
CONTROLLER
I/O Port
CONTROLLER
P3[7:6]
P0[7:0]
ADC
MACRO
ADC
CONTROLLER
AUDIO
Figure 3-2 Block diagram of GPM8F3116A
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Preliminary
GPM8F3132A/3116A/3108A
3.3. GPM8F3108A
RESET/SCK
SYSCLK
2WIRE
WRITER /ICE
OPCODE
DECODER
P42/SDA
IOSC
I/F
RESET/SCK
SRAM
256B
IDM I/F
ALU
EXTERNAL
DATA
MEMORY
I/F
XRAM
256B
(max.)
SFR I/F
Flash
8KB
(max.)
FLASH
CONTROLLER
WATCHDOG
TIMER
GATE0
T0
TIMERS
POWER
MANAGEMENT
UNIT
0/1
GATE1
T1
T2EX
TXD0
UART 0
TIMER 2
RXD0
CAPTURE[3:0]
P0[5:2]
P0[6]
SPITXD
OP_CMP
MACRO
MOTOR
CONTROLLER
SPI
SPIRXD
PWM[5:0]
P0[7:0]
P1[5:1]
P2[7:0]
P3[7:0]
P4[4:0]
INT[1:0]
INT[6:3]
INTERRUPT
CONTROLLER
I/O Port
CONTROLLER
P3[7:6]
P0[7:0]
ADC
MACRO
ADC
CONTROLLER
AUDIO
Figure 3-3 Block diagram of GPM8F3108A
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Preliminary
GPM8F3132A/3116A/3108A
4. SIGNAL DESCRIPTIONS
4.1. Pin Descriptions
4.1.1. GPM8F3132A/3116A
Type：I = Input, O = Output, S = Supply
Pin Name LQFP44
Type
I/O
I/O
I
Description
P14
P15
RESET
NC
1
Port 1 bit 4/ INT5/ CAPTURE2/ HW(PWM2_TRIG)
2
Port 1 bit 5/ INT6/ CAPTURE3/ OC
3
RESET signal, high active/ SCK(2 wire serial bus clock input line)
4
P30
P31
P32
P33
P34
P35
NC
5
I/O
I/O
I/O
I/O
I/O
I/O
Port 3 bit 0/ RXD0
6
Port 3 bit 1/ TXD0
7
Port 3 bit 2/ INT0
8
Port 3 bit 3/ INT1
9
Port 3 bit 4/ T0(Timer 0 input)
Port 3 bit 5/ T1(Timer 1 input)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
P36
P37
VSS
P27
P20
P21
P22
P23
P24
NC
I/O
I/O
S
Port 3 bit 6/ GATE0(Timer 0 gate)/ AUDIO_N
Port 3 bit 7/ GATE1(Timer 1 gate)/ AUDIO_P
Ground
I/O
I/O
I/O
I/O
I/O
I/O
Port 2 bit 7
Port 2 bit 0
Port 2 bit 1/ PWM0
Port 2 bit 2/ PWM1
Port 2 bit 3/ PWM2
Port 2 bit 4/ PWM3
NC
P25
P26
VREG
P44
P43
P42
P41
P40
NC
I/O
I/O
S
Port 2 bit 5/ PWM4/XTI
Port 2 bit 6/ PWM5/XTO
Regulator output, needs 2.2uF Cap.
Port 4 bit 4
I/O
I/O
I/O
I/O
I/O
Port 4 bit 3/ HU_DET(Motor comparator U input)
Port 4 bit 2/ SDA(2 wire serial bus data input/output line)
Port 4 bit 1/ HW_DET(Motor comparator W input)
Port 4 bit 0/ HV_DET(Motor comparator V input)
P07
P06
P05
P04
P03
P02
P01
P00
VCC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
Port 0 bit 7/ AN7(ADC channel 7 input)/ SPI0_RX/ HU_DET(Motor comparator U input)
Port 0 bit 6/ AN6(ADC channel 6 input)/ SPI0_TX/ OP_OUT(Motor OP output)
Port 0 bit 5/ AN5(ADC channel 5 input)/ SPI0_CLK/ OP V-(Motor OP V-)
Port 0 bit 4/ AN4(ADC channel 4 input) / SPI0_CSB/ OP V+(Motor OP V+)
Port 0 bit 3/ AN3(ADC channel 3 input)/ CMPOC V-(Motor comparator OC V-)
Port 0 bit 2/ AN2(ADC channel 2 input)/ CMPOC V+(Motor comparator OC V+)
Port 0 bit 1/ AN1(ADC channel 1 input)
Port 0 bit 0/ AN0(ADC channel 0 input)
Power 5V input
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Preliminary
GPM8F3132A/3116A/3108A
Pin Name LQFP44
Type
I/O
Description
P11
P12
P13
42
43
44
Port 1 bit 1/ T2EX
I/O
Port 1 bit 2/ INT3/ CAPTURE0/ HU
Port 1 bit 3/ INT4/ CAPTURE1/ HV
I/O
4.1.2. GPM8F3108A
Type：I = Input, O = Output, S = Supply
Pin Name LQFP44
Type
I/O
I/O
I
Description
P14
P15
RESET
NC
1
Port 1 bit 4/ INT5/ CAPTURE2/ HW(PWM2_TRIG)
Port 1 bit 5/ INT6/ CAPTURE3/ OC
2
3
RESET signal, high active/ SCK(2 wire serial bus clock input line)
4
P30
P31
P32
P33
P34
P35
NC
5
I/O
I/O
I/O
I/O
I/O
I/O
Port 3 bit 0/ RXD0
6
Port 3 bit 1/ TXD0
7
Port 3 bit 2/ INT0
8
Port 3 bit 3/ INT1
9
Port 3 bit 4/ T0(Timer 0 input)
Port 3 bit 5/ T1(Timer 1 input)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
P36
P37
VSS
P27
P20
P21
P22
P23
P24
NC
I/O
I/O
S
Port 3 bit 6/ GATE0(Timer 0 gate)/ AUDIO_N
Port 3 bit 7/ GATE1(Timer 1 gate)/ AUDIO_P
Ground
I/O
I/O
I/O
I/O
I/O
I/O
Port 2 bit 7
Port 2 bit 0
Port 2 bit 1/ PWM0
Port 2 bit 2/ PWM1
Port 2 bit 3/ PWM2
Port 2 bit 4/ PWM3
NC
P25
P26
VREG
P44
P43
P42
P41
P40
NC
I/O
I/O
S
Port 2 bit 5/ PWM4/XTI
Port 2 bit 6/ PWM5/XTO
Regulator output, needs 2.2uF Cap.
I/O
I/O
I/O
I/O
I/O
Port 4 bit 4
Port 4 bit 3
Port 4 bit 2/ SDA(2 wire serial bus data input/output line)
Port 4 bit 1
Port 4 bit 0
P07
P06
P05
P04
P03
P02
P01
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 0 bit 7/ AN7(ADC channel 7 input)/ SPI0_RX
Port 0 bit 6/ AN6(ADC channel 6 input)/ SPI0_TX/ OP_OUT(Motor OP output)
Port 0 bit 5/ AN5(ADC channel 5 input)/ SPI0_CLK/ OP V-(Motor OP V-)
Port 0 bit 4/ AN4(ADC channel 4 input) / SPI0_CSB/ OP V+(Motor OP V+)
Port 0 bit 3/ AN3(ADC channel 3 input)/ CMPOC V-(Motor comparator OC V-)
Port 0 bit 2/ AN2(ADC channel 2 input)/ CMPOC V+(Motor comparator OC V+)
Port 0 bit 1/ AN1(ADC channel 1 input)
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GPM8F3132A/3116A/3108A
Pin Name LQFP44
Type
I/O
S
Description
P00
VCC
NC
39
40
41
42
43
44
Port 0 bit 0/ AN0(ADC channel 0 input)
Power 5V input
P11
P12
P13
I/O
I/O
I/O
Port 1 bit 1/ T2EX
Port 1 bit 2/ INT3/ CAPTURE0/ HU
Port 1 bit 3/ INT4/ CAPTURE1/ HV
4.2. PIN Map
Package Pin Sequence - LQFP 44 Package Top View
(INT5/CAPTURE2/HW) P14
(INT6/CAPTURE3/OC) P15
(SCK) RESET
P06 (AN6/SPI0_TX/OP_OUT)
P07 (AN7/SPI0_RX/HU_DET)
NC
NC
P40 (HV_DET)
P41 (HW_DET)
P42 (SDA)
(RXD0) P30
(TXD0) P31
(INT0) P32
(INT1) P33
(T0) P34
GPM8F3132A
GPM8F3116A
P43 (HU_DET)
P44
VREG
(T1) P35
NC
P26 (PWM5/XTO)
P25 (PWM4/XTI)
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(INT5/CAPTURE2/HW) P14
(INT6/CAPTURE3/OC) P15
(SCK) RESET
P06 (AN6/SPI0_TX/OP_OUT)
P07 (AN7/SPI0_RX)
NC
NC
P40
(RXD0) P30
(TXD0) P31
(INT0) P32
(INT1) P33
(T0) P34
P41
P42 (SDA)
GPM8F3108A
P43
P44
VREG
(T1) P35
NC
P26 (PWM5/XTO)
P25 (PWM4/XTI)
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5. FUNCTIONAL DESCRIPTIONS
5.1. Central Processing Unit
5.1.1. CPU Introduction
instruction execution. Typical arithmetic operations are addition,
subtraction, multiplication and division. Additional operations are
such as increment, decrement, BCD-decimal-add-adjust and
The CPU is an ultra-high performance, high speed embedded
microcontroller. Pipelined architecture enables the CPU 10 times
faster than standard architecture. This performance can also be
exploited to great advantage in low power application where the
core can be clocked over ten times slower than original
implementation for no performance penalty.
compare.
Within logic unit, operation such as AND, OR,
Exclusive OR, complement and rotation are performed. The
Boolean processor performs the bit operations as set, clear,
complement, jump-if-not-set, jump-if-set-and-clear and move
to/from carry.
5.1.4. Accumulator A register
5.1.2. CPU Features
The accumulation is the 8-bit general-purpose register, which can
be operated with data transfer, temporary saving, condition
judgment, etc.
100 % software compatible with industry 8051
24 times faster multiplication
12 times faster addition
5.1.5. B register
The CPU is fully compatible with industry standard 8051
microcontroller, maintaining all instruction mnemonics and binary
The B register is used during multiply and divide operations. In
other cases, it may be used as normal SFR.
compatibility.
It incorporates some great architectural
enhancements, allowing the CPU instructions execution with high
performance and high speed.
5.1.6. Program Status Word (PSW)
The PSW contains several bits that reflect the current state of the
CPU which is similar to the flag-register of general CPU.
The arithmetic section of the processor performs extensive data
manipulation and is comprised of an 8-bit arithmetic logic unit
(ALU), an ACC(0xE0) register, B(0xF0) register and PSW(0xD0)
register.
5.1.7. Program Counter (PC)
The program counter is a 16-bit wide register. It consists of two
8-bit registers which are PCH and PCL. This register indicates
the address of next instruction to be executed. In Reset state, the
content of 0x0000 is stored into program counter.
5.1.3. Arithmetic Logic Unit (ALU)
The ALU performs the arithmetic and logic operations during one
ACC
Address: 0xE0
Accumulator A Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
ACC[7:0]
0
0
0
Bit
Function
Type
R/W
Description
Condition
7:0
ACC[7:0]
Accumulator A
Table 5-1 The ACC register
B
Address: 0xF0
B Register
Bit
7
0
6
0
5
4
0
3
2
0
1
0
0
0
Function
Default
B[7:0]
0
0
Bit
Function
Type
Description
Condition
7:0
B[7:0]
R/W
B
Table 5-2 The B register
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PSW
Address: 0xD0
Program Status Word Register
Bit
7
CY
0
6
AC
0
5
F0
0
4
RS1
0
3
RS0
0
2
OV
0
1
F1
0
0
P
0
Function
Default
Bit
7
Function
Type
Description
Condition
CY
R/W
R/W
R/W
R/W
Carry flag
6
AC
F0
Auxiliary carry flag
5
General purpose flag 0
Register bank select bits
4:3
RS[1:0]
RS[1:0]
00
Function description
Bank 0, data address 0x00-0x07
Bank 1, data address 0x08-0x0F
Bank 2, data address 0x10-0x17
Bank 3, data address 0x18-0x1F
01
10
11
2
1
0
OV
F1
P
R/W
R/W
R/W
Overflow flag
General purpose flag 1
Parity flag
Table 5-3 The PSW register
5.2. Memory Organization
5.2.1. Introduction
The GPM8F313A2/3116A/3108A has three separated address
spaces for program memory and data memory. The program
memory is on-chip, re-programmable Flash memory and contains
up to 32/16/8K bytes spaces. The data memory is divided into
1K/512/256 bytes of external RAM, 256 bytes IDM with 128 bytes
of SFR which can be read and written. The upper IDM and SFR
use the same access address in different access ways which are
described in Figure 5-2.
the whole chip memory is protected and any page erase or
program by two wire serial interface is not allowed. The only
thing user can do is to erase whole chip. Figure 5-1 shows the
program memory map of 32KB/16KB/8KB Flash.
After each reset, CPU starts execution in the program memory at
location 0x0000. Each interrupt has its own start address for
service routine.
The Flash memory can be programmed
in-system, through the SCK/SDA interface or by software using the
MOVX instruction when PWE= 1. User can refer to the example
code in the programming guide for the procedure of write and
erase operations. Flash data cannot be programmed from a ‘0’ to a
‘1’, and only erase operation can realize it. Therefore, flash data
would typically be erased (set to 0xFF) before being programmed.
The write and erase operations are executed by using Pseudo-idle
mode to be automatically timed by hardware without data polling to
determine the end of the write and erase operation.
5.2.2. Program Memory Allocation
The program memory allocation is divided into two parts, including
code area and last page.
The GPM8F3132A/3116A/3108A
implements 32/16/8KB memory size. It begins at address 0x0000
and ends at address 0x7FFF/0x3FFF/0x1FFF. The address
space between 0x0000 and 0x7BFF/0x3BFF/0x1BFF is used for
code
area
and
the
address
space
between
0x7C00/0x3C00/0x1C00 and 0x7FFF/0x3FFF/0x1FFF is called
LAST_PAGE which cannot be erased by software. It reserves for
constants storage. The last address 0x7FFF/0x3FFF/0x1FFF is
used for CONFIG_BYTE whose definition of each bit is described
in Table 5-4. This CONFIG_BYTE value can be read from
CONFIG_BYTE register(0xB7). User can lock the whole chip by
CONFIG_BYTE [0]. If CONFIG_BYTE[0] is programmed to be ‘0’,
For software security consideration, user can set the
programmable Flash level by FL_LEVEL register to limit the code
area that avoids inadvertently erased or written by software; the
protected region is called READONLY_PAGE.
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CONFIG_BYTE
CONFIG_BYTE
LAST_PAGE
CONFIG_BYTE
LAST_PAGE
0x1FFF(8KB)
0x1C00(7KB)
0x7FFF(32KB)
0x7C00(31KB)
0x3FFF(16KB)
0x3C00(15KB)
LAST_PAGE
Code Area
GPM8F3108A
1
Code Area
Code Area
0x0000(0KB)
0x0000(0KB)
0x0000(0KB)
GPM8F3132A
GPM8F3116A
Figure 5-1 Program memory organization
CONFIG_BYTE
Address: 0xB7
CONFIG_BYTE Register
Bit
7
--
1
6
--
1
5
4
--
1
3
--
1
2
--
1
0
Function
Default
LVRVSEL
1
IOSEL
CODE Lock
1
1
Bit
7:6
5
Function
--
Type
Description
Condition
R
R
Reserved
LVRVSEL
LVR voltage level selection
0: 3.9V
1: 2.2V
4:2
1
--
R
R
R
Reserved
IO initial state selection bit
0: Input pull high
1: floating
IOSEL
0
CODE Lock
0 : CODE is locked; 1 : CODE is unlocked
Table 5-4 The CONFIG_BYTE register
FLASHCON
Bit
Address: 0xEC
Flash Control Register
7
--
1
6
--
1
5
--
1
4
--
1
3
--
1
2
M_ERASE
1
1
0
PROG
1
Function
Default
P_ERASE
1
Bit
7:2
2
Function
Type
R/W
R/W
R/W
R/W
Description
Condition
--
Reserved
Macro Erase enable bit
Page Erase enable bit
Program enable bit
M_ERASE
P_ERASE
PROG
1
0
Table 5-5 The CONFIG_BYTE register
FL_LEVEL
Bit
Address: 0xED
Flash Level Register
7
--
0
6
--
0
5
4
0
3
2
1
0
0
0
Function
Default
FLASH_LEVEL[5:0]
0
0
0
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Bit
7:6
5:0
Function
--
Type
R/W
R/W
Description
Condition
Reserved
FLASH_LEVEL[5:0]
FLASH_LEVEL, it determines how many 1K pages are read only
FLASH_LEVEL Note
0
no page is read only
1
address < 0x400 is read only
address < 0x800 is read only
address < 0xC00 is read only
address < 0x1000 is read only
address < 0x1400 is read only
address < 0x1800 is read only
address < 0x1C00 is read only
address < 0x2000 is read only
address < 0x2400 is read only
address < 0x2800 is read only
address < 0x2C00 is read only
address < 0x3000 is read only
address < 0x3400 is read only
address < 0x3800 is read only
address < 0x3C00 is read only
address < 0x4000 is read only
address < 0x4400 is read only
address < 0x4800 is read only
address < 0x4C00 is read only
address < 0x5000 is read only
address < 0x5400 is read only
address < 0x5800 is read only
address < 0x5C00 is read only
address < 0x6000 is read only
address < 0x6400 is read only
address < 0x6800 is read only
address < 0x6C00 is read only
address < 0x7000 is read only
address < 0x7400 is read only
address < 0x7800 is read only
address < 0x7C00 is read only
address < 0x7FFF is read only
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
≧32
Note 1. Only FLASH_LEVEL[5:0] is useful in GPM8F3732A
Note 2. Only FLASH_LEVEL[4:0] is useful in GPM8F3716A
Note 3. Only FLASH_LEVEL[3:0] is useful in GPM8F3708A
Table 5-6 The FL_LEVEL register
5.2.3. Data Memory Allocation
Data
memory
address
allocations
on
the
memory (IDM) consists of four register banks with eight registers
each. A bit addressable segment with 128 bits (16 bytes) begins
at 0x20. The address from 0x30 to 0x7F is not defined and can
be utilized freely by user. The last 128 bytes of data memory can
GPM8F3132A/3116A/3108A are divided into two parts. The first
part is 1K/512/256 bytes of external RAM and the second one is
256 byte IDM shown in Figure 5-2. The lowest internal data
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be used by different addressing modes.
With the indirect
addressing from 0x80 to 0xFF is accessed. The SFR memory
map is shown in Table 5-7.
addressing mode, address from 0x80 to 0xFF shared with stack
space is addressed. With the direct addressing mode, the SFR
0xFF
Upper Internal RAM
SFR
shared with Stack
space
Special Function
Registers
(indirect addressing)
(direct addressing)
0x80
0x30
RAM
Lower Internal RAM shared with Stack space
(direct & indirect addressing)
Bit addressable area
4 banks, R0-R7 each
0x20
0x00
XRAM: 1KB (GPM8F3132A)
512B(GPM8F3116A)
IDM:256B and SFR
256B(GPM8F3108A)
Figure 5-2 Data memory organization
Note1: Black: standard 8051 register; gray: additional register;
Note2: PWMSINCON, ADDR_OFFSETL and ADDR_OFFSETH register are only available in GPM8F3132A
Note3: CMPCON1 is only available in GPM8F3132A/3116A
0xF8
0xF0
0xE8
EIP
B
IOSCCON
ADCON
IOSCT0
IOSCT1
ADAEN
TA
SPICON
ADOL
SPITXD
ADOH
SPIRXD
ADLB
ADCFG
ADUB
EIE
PWMOVRD_
BUF
FLASHCON
FL_LEVEL
ADCPWM
KEYCODE
0xE0
0xD8
ACC
PWMCON4
CAP0BUFL
PWMCON3
CAP0BUFH
PWMOVRD
CAP1BUFL
PWMCON3_
BUF
CAP1BUFH
CAP0CON
CAP2BUFL
CAP1CON
CAP2BUFH
CAP2CON
WDCON PWMCON2
0xD0
0xC8
0xC0
0xB8
PSW
CMP0L
T2IF
CMP0H
CRCL
CMP1L
CRCH
CMP1H
TL2
CMP2L
TH2
CMP2H
CCEN
PWMCON6
PWMCON5
CCH3
T2CON
CCL1
CCH1
CCL2
CCH2
CCL3
IP
PWMCON1
MDPRDL
MDPRDH
DTR
PWMSINCON
ADDR_
OFFSETL
WKUEN
SYSCON0
ADDR_
OFFSETH
CONFIG_BYTE
SYSCON1
0xB0
0xA8
0xA0
0x98
0x90
0x88
0x80
P3
PWMIF
PWMCON9
P4
PWMIE
CMPCON1
P3_PU
AUDCON
CMPCON2
P3_PD
AUDBUF
PWMCON8
SRCON
P4_PD
IE
P2
P4_PU
P1_PU
RSTSTS
TH0
FLASHERRF SYSCON2
SCON0
P1
SBUF0
EIF
P0_PU
P0_PD
P1_PD
P2_PU
BIP
P2_PD
BIF
TCON
P0
TMOD
SP
TL0
TL1
TH1
CKCON
DPS
RSTCON
PCON
DPL0
DPH0
DPL1
DPH1
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
Table 5-7 SFR memory map
5.2.4. Memory Related SFR
5.2.4.1. Program write enable bit
The Program Write Enable (PWE) bit, located in PCON register bit
4, is used during MOVX instructions. When PWE bit is set to
logic 1, the MOVX @DPTR, An instruction writes data located in
accumulator register into program memory addressed by DPTR
register. Program memory can be read by MOVC only regardless
of PWE bit.
The following sub-sections describe program, external and internal
memories related SFRs of 8051 core and their functionality. For
other information about standard SFRs, please refer to appropriate
peripheral section.
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5.2.4.2. Data pointer registers
internal RAM space. It is incremented before data is stored
during PUSH and CALL execution and decremented after data is
popped during POP, RET and RETI execution. In the other words,
it always points to the last valid stack byte. The SP is accessed
as any other SFRs. Figure 5-3 shows an example when PUSH A
is executed and Figure 5-4 shows an example when POP PSW is
executed.
Dual data pointer registers are implemented to speed up data
block copying. DPTR0 and DPTR1 are located in four SFR
addresses. Active DPTR register is selected by SEL bit (DPS[0]).
If SEL=0 then DPTR0 is selected otherwise DPTR1.
5.2.4.3. Stack pointer
The 8051 has 8-bit stack pointer called SP (0x81) located in the
SP
SP
08H
07H
23H
21H
08H
07H
38H
21H
08H
07H
ACC
23H
ACC
23H
After execution
Before execution
Figure 5-3 Stack byte order for PUSH A instruction
SP
SP
07H
08H
65H
08H
07H
65H
21H
08H
07H
21H
PSW
65H
PSW
23H
After execution
Before execution
Figure 5-4 Stack byte order for POP PSW instruction
PCON
Bit
Address: 0x87
Power Configuration Register
7
6
--
0
5
4
PWE
0
3
2
--
0
1
STOP
0
0
--
0
Function
Default
SMOD0
0
CPU_IDLE
0
STOP_RST_EN
0
Bit
7
Function
SMOD0
--
Type
Description
Condition
R/W
R/W
R/W
UART0 double baud rate bit when clocked by Timer1
Reserved
6
5
CPU_IDLE
IDLE mode enable bit
0: IDLE mode disabled ;
1: IDLE mode entered
4
3
2
PWE
STOP_RST_EN
--
R/W
R/W
R/W
Program Write Enable (PWE)
0: Disable Flash write activity during MOVX instruction
1: Enable Flash write activity during MOVX instruction
Wakeup state selection bit
0: Next instruction state after wakeup
1: Reset state afer wakeup
Reserved
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Bit
Function
Type
Description
Condition
1
STOP
R/W
STOP mode enable bit
0: Disabled
1: Enabled
0
--
R/W
Reserved
Table 5-8 The PCON register
DPH0
Bit
Address: 0x83
Data Pointer Register - high byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
DPTR0[15:8]
0
0
0
Bit
Function
Type
Description
Condition
7:0
DPTR0[15:8]
R/W
Data pointer register DPTR0 - high byte
Table 5-9 The DPH0 register
DPL0
Bit
Address: 0x82
Data Pointer Register - low byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
DPTR0[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
DPTR0[7:0]
R/W
Data pointer register DPTR0 - low byte
Table 5-10 The DPL0 register
DPH1
Bit
Address: 0x85
Data Pointer 1 Register - high byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
DPTR1[15:8]
0
0
0
Bit
Function
Type
Description
Condition
7:0
DPTR1[15:8]
R/W
Data pointer 1 register DPTR1 - high byte
Table 5-11 The DPH1 register
DPL1
Bit
Address: 0x84
Data Pointer 1 Register - low byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
DPTR0[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
DPTR1[7:0]
R/W
Data pointer 1 register DPTR1 - low byte
Table 5-12 The DPL1 register
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DPS
Address: 0x86
Data Pointer Select Register
Bit
7
ID1
0
6
ID0
0
5
TSL
0
4
-
3
-
2
-
1
-
0
SEL
0
Function
Default
0
0
0
0
Bit
7:6
5
Function
ID[1:0]
TSL
Type
Description
Condition
Increment/decrement function select.
See Table 5-14
R/W
R/W
Toggle select enable bit
0: DPTR related instructions do not affect state of SEL bit
1: DPTR related instructions to toggle the SEL bit
Reserved
4:1
0
--
R/W
R/W
SEL
Active data pointer select bit
See Table 5-14
Table 5-13 The DPS register
ID1
ID0
SEL=0
INC DPTR0
SEL=1
0
0
1
1
0
1
0
1
INC DPTR1
INC DPTR1
DEC DPTR1
DEC DPTR1
DEC DPTR0
INC DPTR0
DEC DPTR0
Table 5-14 DPTR0/DPTR1 operations
SP
Address: 0x81
Stack Pointer Register
Bit
7
0
6
0
5
4
0
3
2
1
1
0
1
Function
Default
SP[7:0]
0
0
1
Bit
Function
Type
Description
Condition
7:0
SP[7:0]
R/W
Stack pointer
Table 5-15 The SP register
5.3. Special Function Registers(SFR)
GPM8F3132A/3116A/3108A has up to 120/118/117 control
registers for special function registers. All of the SFRs are used
by MCU and peripheral function block for controlling the desired
operation. Some of the SFRs contain control and status bits for
peripheral module such as Timer unit, Interrupt control unit, etc.
Some of bits in SFRs are read only, so write to those bits don't
have any effect on corresponding bits. Some SFRs have key
code design that KEYCODE register must be written with correct
key codes, in sequence, before writing a value to it for software
security. The following table shows the summary of the SFRs.
The detailed information of each SFRs are explained in each
peripheral section.
Key Reset
Addr
Function
7
6
5
4
3
2
1
0
Code Value
0x80
0x81
0x82
0x83
P0
SP
0xFF
0x07
0x00
0x00
Port 0
Stack Pointer
DPL0
DPH0
Data pointer register DPTR0 - low byte
Data pointer register DPTR0 - high byte
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Key Reset
Code Value
Addr
Function
7
6
5
4
3
2
1
0
0x84
0x85
0x86
DPL1
DPH1
DPS
0x00
0x00
0x00
Data pointer register DPTR1 - low byte
Data pointer register DPTR1 - high byte
ID1
ID0
--
TSL
CPU_
IDLE
TF0
--
--
STOP_RST
_EN
--
--
SEL
--
0x87
PCON
0x00
SMOD0
PWE
--
STOP
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
TCON
TMOD
TL0
0x00
0x00
0x00
0x00
0x00
0x00
0x01
TF1
TR1
CT1
TR0
M10
IE1
IT1
IE0
IT0
GATE1
M11
GATE0
CT0
M01
M00
Timer 0 Load value – low byte
Timer 1 Load value – low byte
Timer 0 Load value – high byte
Timer 1 Load value – high byte
TL1
TH0
TH1
CKCON
WD1
CB_P_
ENB
WD0
--
T1M
T0M
--
--
--
4F,72,
0x10
7A
LP_E_ FLASH_FL XADDR_E
CHIP_E_
ENB
MISS_CLK_ FLASH_ERR
0x8F
RSTCON
--
ENB
--
OW_ ENB
--
NB
ENB
_ ENB
--
0x90
0x91
P1
0xff
Port 1
EIF
0x00
--
--
INT6F
FLASH_
ERR_RST
PAUDIO
AUDIOF
REN0
INT5F
INT4F
INT3F
MISS_CL STOP_
0x94
RSTSTS
0x00
S/W_RST WDT_RST LVR_RST RAD_RST
PADC PHS_CHG PMOTOR PMERR
K_RST
--
RST
POC
OCF
SM02
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
BIP
0x00
0x00
0x00
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0xFF
0xFF
0x00
0xFF
0x00
--
--
BIF
--
ADCF
TB08
HS_CHGF MOTORF
MERRF
RI0
SCON0
SBUF0
P0_PU
P0_PD
P1_PU
P1_PD
P2_PU
P2_PD
P2
SM00
SM01
RB08
TI0
UART 0 buffer
P07_PU
P07_PD
P17_PU
P17_PD
P27_PU
P27_PD
P06_PU P05_PU P04_PU
P06_PD P05_PD P04_PD
P16_PU P15_PU P14_PU
P16_PD P15_PD P14_PD
P26_PU P25_PU P24_PU
P26_PD P25_PD P24_PD
P03_PU
P03_PD
P13_PU
P13_PD
P23_PU
P23_PD
P02_PU
P02_PD
P12_PU
P12_PD
P22_PU
P22_PD
P01_PU
P01_PD
P11_PU
P11_PD
P21_PU
P21_PD
P00_PU
P00_PD
P10_PU
P10_PD
P20_PU
P20_PD
Port 2
Port 4
P34_PU
P4
P3_PU
P3_PD
P4_PU
P4_PD
P37_PU
P36_PU
P36_PD
P46_PU
P46_PD
P35_PU
P35_PD
P45_PU
P45_PD
FLASH_FL
OW_F
P33_PU
P33_PD
P43_PU
P43_PD
P32_PU
P32_PD
P42_PU
P42_PD
P31_PU
P31_PD
P41_PU
P41_PD
P30_PU
P30_PD
P40_PU
P40_PD
P37_PD
P34_PD
P44_PU
P44_PD
--
--
0xA6
0xA7
FLASHERRF
SYSCON2
0x00
CB_P_F
LP_E_F
--
XADDR_F
--
CHIP_E_F
--
--
INT_filter_ GPIO_
SCHMIT_ SCHMIT_ SCHMIT_ SCHMIT_D
FF,00 0x00 ADCLKX2
en
SSO
ES0
DIS_P3
ET1
DIS_P2
EX1
DIS_P1
ET0
IS_P0
EX0
0xA8
0xA9
IE
0x00
0x00
EA
--
--
--
ET2
PWMCON9
CMPCON1
PWM5_POL PWM4_POL PWM3_POL PWM2_POL PWM1_POL
PWM0_POL
HU_DET_ SCHMIT_
0xAA (GPM8F3132A)
(GPM8F3116A)
0x04
--
--
--
P41_AEN P40_AEN
CMP_EN
SEL
EN
0xAB
0xAD
CMPCON2
SRCON
0x00
0xFF
--
--
--
--
OC_status
--
OC_SEL
P2_SR
OP_EN
P0_SR
TRIM_VOSP TRIM_VOSN
CMPOC_EN
P4_SR
P3_SR
P1_SR
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Preliminary Version: 0.6
Preliminary
GPM8F3132A/3116A/3108A
Key Reset
Code Value
Addr
Function
7
6
5
4
3
2
1
0
AUDIO_N
_DIS
SCHMIT_D
IS_P4
--
0xAE
SYSCON0
FF,00 0x00
LVRENB
--
--
--
--
CLKOUT_EN CCOUTENB
0xAF
0xB0
0xB1
0xB2
SYSCON1
P3
FF,00 0x03 T2CLK_SW HV_SEL SPI1_EN SPI0_EN
--
--
0xFF
0x00
Port 3
PWMIF
PWMIE
--
HS_CHGF PERIODF CAP2F
CAP1F
CAP0F
--
--
OCF
0x00 MATCHIE
PERIODIE CAP2IE
CAP1IE
CAP0IE
OCIE
HS_CHGIE
AUDIO_FRE
Q_SEL
0xB3
AUDCON
0x00
--
--
--
--
AUDIOIE
AUDIO_EN
AUDIO_MODE
0xB4
0xB5
0XB6
AUDBUF
PWMCON8
WKUEN
0x80
0x00
AUDBUF[7:0]
--
SIN_LOSE_LEVEL[3:0]
MOS_PRO_SEL[1:0]
MOS_PRO_EN
AF,50 0x07
0xFF
--
--
--
--
--
INT6_WKUEN INT5_WKUEN INT4_WKUEN INT3_WKUEN
INT1_WKUEN INT0_WKUEN
0xB7 CONFIG_BYTE
--
--
LVRVSEL
PT2
--
PS0
--
--
IOSEL
PT0
CODE_LOCK
0xB8
0xB9
0xBA
0xBB
0xBC
IP
0x00
PT1
PX1
TYPE
PX0
PWMCON1
MDPRDL
0x00 PWM_EN
0x01
TMR5EN
PWMCK_SEL[1:0]
MATCH_EN
SYNC_DECT
PWM Period : MDPRD[7:0]
-- PWM Period : MDPRD[11:8]
PWM Dead Time Period : DTR[7:0]
PHASE_ HALL_SA FLOAT_DI
MDPRDH
DTR
0x00
0x00
--
--
--
--
PWMSINCON
(GPM8F3132A)
SFR_ANG_
EN
0xBD
0x00
0x00
0x00
--
--
SIN_EN
DIRECT
TRT
S
0xBE ADDR_OFFSETL
(GPM8F3132A)
ADDR_OFFSET[7:0]
ADDR_OFFSET[15:8]
0xBF ADDR_OFFSETH
(GPM8F3132A)
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
T2CON
T2IF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Timer2cc compare/capture 1 low byte
Timer2cc compare/capture 1 high byte
Timer2cc compare/capture 2 low byte
Timer2cc compare/capture 2 high byte
Timer2cc compare/capture 3 low byte
Timer2cc compare/capture 3 high byte
T2PS
--
I3FR
--
--
--
T2R1
--
T2R0
--
T2CM
T2I1
T2I0
TF2
EXEN2
EXF2
CRCL
CRCH
TL2
CRC register – Low byte
CRC register – High Byte
Timer 2 Load value – low byte
Timer 2 Load value – high byte
TH2
CCEN
CMH3
OC_FILTER_
SEL
CML3
CMH2
CML2
CMH1
CML1
CMH0
--
CML0
OC_EN
P
PERIOD_TRIG_MD
[1:0]
0xCF
PWMCON5
0x00
TIMER5_CKSEL[2:0]
AC F0 RS1
0xD0
0xD1
0xD2
0xD3
0xD4
0xD5
PSW
0x00
0xa0
0x00
0xb0
0x00
0xc0
CY
RS0
OV
F1
CMP0L
CMP0H
CMP1L
CMP1H
CMP2L
CMP0 compare level: CMP0[7:0]
--
--
--
--
--
--
--
CMP0[11:8]
CMP1 compare level: CMP1[7:0]
--
CMP1[11:8]
CMP2 compare level: CMP2[7:0]
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Preliminary Version: 0.6
Preliminary
GPM8F3132A/3116A/3108A
Key Reset
Code Value
Addr
Function
7
6
5
4
3
2
1
0
0xD6
0xD7
0xD8
CMP2H
PWMCON6
WDCON
0x00
0x00
0x00
--
--
--
--
HW_INV
--
CMP2[11:8]
HU_INV CAP_SEL HS_SEL
HS_SWITCH[2:0]
--
HV_INV
WDIF
--
--
WTRF
EWT
RWT
PWMSYNC_
0xD9
PWMCON2
0x00
--
PWM45_EN PWM23_EN PWM01_EN
PWM45_MODE PWM23_MODE
PWM01_MODE
ADC
0xDA
0xDB
PWMCON3
PWMOVRD
0x00
0x00
0x00
--
--
--
PWM_SYNC
PWM5_AUTO PWM4_AUTO PWM3_AUTO PWM2_AUTO PWM1_AUTO PWM0_AUTO
PWM5_OVRD PWM4_OVRD
--
--
PWM3_OVRD
PWM2_OVRD
PWM1_OVRD
PWM0_OVRD
0xDC PWMCON3_BUF
PWMCON3_BUF[5:0]
CAP0_TMR5_
0xDD
0xDE
0xDF
CAP0CON
CAP1CON
CAP2CON
0x00
0x00
0x00
--
--
--
--
--
--
--
--
--
TF5
--
--
CAP0_MODE[1:0]
CAP1_MODE[1:0]
CAP2_MODE[1:0]
RST
CAP1_TMR5_
--
RST
CAP2_TMR5_
--
--
RST
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
ACC
0x00
0x00
0x9C
0x02
0x9C
0x02
0x9C
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ACC register
PWMCON4
CAP0BUFL
CAP0BUFH
CAP1BUFL
CAP1BUFH
CAP2BUFL
CAP2BUFH
EIE
ROTOR_STATUS[2:0]
--
MATCHF
MATCH_VALUE[2:0]
CAP0BUF[7:0]
CAP0BUF[15:8]
CAP1BUF[7:0]
CAP1BUF[15:8]
CAP2BUF[7:0]
CAP2BUF[15:8]
-
-
EWDI
EINT6
EINT5
PWMOVRD_BUF[5:0]
Timed Access protection register (0xaaÎ0x55)
EINT4
EINT3
--
0xEA PWMOVRD_BUF
0xEB
0xEC
0xED
0xEE
0xEF
0xF0
0xF1
0xF2
0xF3
0xF4
0xF5
0xF6
0xF7
0xF8
TA
FLASHCON
FL_LEVEL
ADCPWM
KEYCODE
B
--
--
--
--
--
--
--
FLASH_LEVEL[5:0]
ADC_SYNC_SHIFT[2:0]
KC4 KC3 KC2
B register
WINIE ADIE
SHCLK[1:0]
P_ERASE
PROG
M_ERASE
ADC_SYNC_MODE[1:0]
KC7
KC6
KC5
KC1
KC0
ADCON
ADCFG
ADAEN
ADOL
WINF
READYF WIN_SEL
CH_SEL[2:0]
--
PSIDLE
START
ADCLK[1:0]
AD_BITSEL
0x00 P07_AEN P06_AEN P05_AEN P04_AEN P03_AEN P02_AEN P01_AEN P00_AEN
--
--
--
--
ADO[3:0]
ADOH
ADO[11:4]
ADLB[7:0]
ADUB[7:0]
ADLB
0x00
0x00
0x00
ADUB
EIP
--
--
PWDI
XTAL_PAD_
EN
PINT6
PINT5
PINT4
PINT3
--
0xF9
IOSCCON
0x09 XTO_AEN XTI_AEN
OSC_SEL[1:0]
CLKDIV[2:0]
0xFA
0xFB
IOSCT0
IOSCT1
0x18
--
--
TEMP_TRIM[2:0]
XFCN[2:0]
OSC_TRIM[2:0]
OSC_TUNE[4:0]
PO-
CSB_
KEEP
SPI_
0xFC
0xFD
SPICON
SPITXD
0x00
0x00
PHASE
SPI_CLK_SEL[1:0]
--
SPI_RD
LARITY
START
SPI TX Data[7:0]
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Preliminary Version: 0.6
Preliminary
GPM8F3132A/3116A/3108A
Key Reset
Code Value
Addr
Function
7
6
5
4
3
2
1
0
0xFE
SPIRXD
0x00
SPI RX Data[7:0]
5.4. Clock Source
GPM8F3132A/3116A/3108A has three clock sources including
internal oscillator (24.5MHz), external crystal and external clock
source. These three clocks are chosen to be system clock
source by controlling OSC_SEL[1:0] bits of IOSCCON register. In
addition, a clock divisor for the system clock source is contained to
obtain different frequencies. There are eight selection totally and
can be controlled by CLKDIV[2:0] bits of IOSCCON register.
User can monitor the frequency of SYSCLK on P35 by setting
SYSCON0[2]. The block diagram of clock source and detailed
description of IOSCCON register are shown in Figure 5-5 and
Table 5-16 respectively.
IOSCCON(0xF9)
DIV2~DIV64
CLKGATE
STOP
PERIPHERAL
IOSC_CLK
XOSC_CLK
EOSC_CLK
XTI
CLK
SYSCLK
SYSCLK_SOURCE
GENERATOR
XTO
CLK
CLKGATE
CPU
DIV1.5
Figure 5-5 The block diagram of clock sources
If crystal mode is utilized, different frequencies can be selected by
IOSCT0[2:0] as shown in Table 5-18 and software should delay a
period of time according to different crystals for clock stable time.
In order to enter stop mode, XTAL_PAD_EN should be turned off
before PCON[1] is set to ‘1’. If internal oscillator mode is utilized,
tuning frequencies is possible through IOSCT1[7:0].
If
IOSCT1[7:5] is used for trimming bit, each step of frequency is
10%. If IOSCT1[4:0] is used for trimming bit, each step of
frequency is 0.4% for fine-tuning. The IOSCT1 register is shown
in Table 5-19.
IOSCCON
Bit
Address: 0xF9
IOSC Control Register
7
XTO_AEN
0
6
XTI_AEN
0
5
4
0
3
2
0
1
0
1
Function
Default
XTAL_PAD_EN
0
OSC_SEL[1:0]
CLKDIV[2:0]
0
1
Bit
Function
Type
Description
7
XTO_AEN
R/W
XTO analog PAD enable control bit
0: XTO can be I/O PAD
1: XTO can be analog PAD
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Preliminary
GPM8F3132A/3116A/3108A
Bit
Function
Type
Description
6
XTI_AEN
R/W
XTI analog PAD enable control bit
0: XTI can be I/O PAD
1: XTI can be analog PAD
5
XTAL_PAD_EN
OSC_SEL[1:0]
R/W
R/W
If using XTAL or ECLK, XTAL_PAD_EN should be set first for OSC_SEL selection.
4:3
00: Internal ROSC
01: Internal ROSC
10: XTAL
11: External CLK
If using XTAL, OSC_SEL[1](XTAL_EN) should be set after XOSC_CLK is stable
System Clock source divider
2:0
CLK_DIV
R/W
CLK_DIV
000
Clock control
SYSCLK_SOURCE
SYSCLK_SOURCE/2
SYSCLK_SOURCE/4
SYSCLK_SOURCE/8
SYSCLK_SOURCE/16
SYSCLK_SOURCE/32
SYSCLK_SOURCE/64
SYSCLK_SOURCE/1.5
001
010
011
100
101
110
111
Table 5-16 The IOSCCON register
SYSCON0
Address: 0xAE
SYSTEM control0 Register
Bit
7
6
--
0
5
--
0
4
3
--
0
2
1
0
SCHMIT_DIS_
Function
LVRENB
AUDIO_N_DIS
0
CLKOUT_EN CCOUTENB
P4
0
Default
0
0
0
Key Code
FF,00
Bit
Function
Type
Description
Condition
7
LVRENB
R/W
LVR enable control
0: enable LVR function
1: disable LVR function
Reserved
6:5
4
--
--
AUDIO_N_DIS
R/W
AUDIO_N disable bit available only if audio function is enabled
0: P36/P37 are output simultaneously as AUDIO_N/P
1: Only P37 is output as AUDIO_P
3
2
1
--
--
Reserved
CLKOUT_EN
CCOUTENB
R/W
R/W
Clock output enable bit (SYSCLK is output on P35)
Disable output function of compare mode in Timer2
0: P1[3:1] = {compare3,compare2,compare1}
1: P1[3:1] is GPIO
0
SCHMIT_DIS_P4
R/W
P4 schmitt trigger function disable control bit
Table 5-17 SYSCON0 register
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Preliminary Version: 0.6
Preliminary
GPM8F3132A/3116A/3108A
IOSCT0
Bit
Address: 0xFA
IOSC Timing 0 Register
7
--
0
6
--
0
5
4
3
2
1
XFCN[2:0]
0
0
0
Function
Default
TEMP_TRIM[2:0]
1
0
1
0
Bit
Function
Type
Description
Condition
7:6
5:3
2:0
--
R/W
R/W
R/W
Reserved
TEMP_TRIM[2:0]
XFCN[2:0]
Temperature coefficient trimming(011: default)
External XTAL Freq control bit (XTAL_PAD_EN need to be1)
XFCN
000
001
010
011
100
101
110
111
XTAL(HZ)
F=32768Hz(weak)
F=32768Hz(strong)
1MHz<F<4MHz
4MHz<F<8MHz
8MHz<F<12MHz
12MHz<F<16MHz
16MHz<F<20MHz
25MHz>F>20MHz
Table 5-18 The IOSCT0 register
IOSCT1
Bit
Address: 0xFB
IOSC Control Timing 1 Register
7
6
5
4
3
2
1
0
Function
Default
OSC_TRIM[2:0]
OSC_TUNE[4:0]
Bit
7:5
4:0
Function
Type
Description
Condition
OSC_TRIM[2:0]
OSC_TUNE[4:0]
R/W
R/W
Internal OSC frequency trimming bit, 10% each step
Internal OSC frequency trimming bit, 0.4% each step
Table 5-19 The IOSCT1 register
5.5. Power Saving Mode
5.5.1. Introduction
not turned off, so peripheral device can still work normally.
Although
GPM8F3132A/3116A/3108A
is
a
high-speed
5.5.3. STOP mode
microcontrollers designed for maximum performance, it also
provide Power Management Unit (PMU) with two advanced power
conservation modes. These modes are IDLE mode, and STOP
mode. In order to reduce the current consumption when system
does not need to be active, STOP mode can be utilized. For
more information about these two modes, please see the following
two sections.
STOP mode is the lowest power states that the microcontroller can
enter. It is achieved by cutting-off frequency provided to SYSCLK,
resulting in a fully static condition. No processing is possible,
timers are stopped, and no serial communication is executed.
Processor operation will be postponed on the instruction that sets
the STOP bit. STOP mode can be exited in the following ways:
i. A non-clocked interrupt such as the external interrupts
5.5.2. IDLE mode
INT0-INT6 can be used.
Clocked interrupts such as the
watchdog timer, internal timers, and serial ports do not operate in
STOP mode. Processor operation will resume with the fetching of
the interrupt vector associated with the interrupt that caused the
exit from STOP mode. When the interrupt service routine is
The IDLE Mode reduces power consumption by turning off the
clock provided to the microcontroller, causing MCU to stop to
execute following instruction. IDLE mode is entered by setting
the CPU_IDLE bit (PCON[5]). In this mode, peripheral clock is
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Preliminary Version: 0.6
Preliminary
GPM8F3132A/3116A/3108A
completed, RETI returns the program to the instruction
immediately following the one that invoked the STOP mode.
When INT0~INT6 are used for wakeup source, WKUEN register
must be set as shown in Table 5-22. There are two selections of
the place of instruction execution after wakeup when entering
STOP mode and the control bit is in POCN[3]. If STOP_RST_EN
is set to ‘1’, reset state will take place after wakeup; otherwise,
next instruction will be executed. Table 5-20 shows the three
modes in GPM8F3132A/3116A/3108A.
ii. RESET pin cause exit from stop mode and the processor
operation will resume execution at address 0x0000.
System Clock
Peripheral clock
Wakeup source
After wakeup
RUN Mode
IDLE Mode
Register setting Register setting
--
--
OFF
OFF
ON
1. All wakeup sources
2. All interrupt sources
1. All wakeup sources
Next instruction state
STOP Mode
OFF
Reset state or next instruction state base on PCON[3]
Table 5-20 The three operation modes for GPM8F3132A/3116A/3108A
PCON
Bit
Address: 0x87
Power Configuration Register
7
6
--
0
5
CPU_IDLE
0
4
PWE
0
3
2
--
0
1
STOP
0
0
--
0
Function
Default
SMOD0
0
STOP_RST_EN
0
Bit
7
Function
SMOD0
--
Type
Description
Condition
R/W
R/W
R/W
UART0 double baud rate bit when clocked by Timer1
Reserved
6
5
CPU_IDLE
IDLE mode enable bit
0: IDLE mode disabled ;
1: IDLE mode entered
4
3
PWE
R/W
R/W
Program Write Enable (PWE)
0: Disable Flash write activity during MOVX instruction
1: Enable Flash write activity during MOVX instruction
Wakeup state selection bit
0: Next instruction state after wakeup
1: Reset state afer wakeup
Reserved
STOP_RST_EN
2
1
--
R/W
R/W
STOP
STOP mode enable bit
0: Disabled
1: Enabled
0
--
R/W
Reserved
Table 5-21 The PCON register
WKUEN
Bit
Address: 0xB6
Wake Up Enable Register
7
6
5
4
3
2
--
1
1
0
Function
Default
Key Code
--
0
INT6_WKUEN INT5_WKUEN INT4_WKUEN INT3_WKUEN
INT1_WKUEN INT0_WKUEN
0
0
0
0
1
1
AF, 50
Bit
Function
--
Type
Description
Condition
7
R/W
Reserved
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Preliminary Version: 0.6
Preliminary
GPM8F3132A/3116A/3108A
Bit
6
Function
INT6_WKUEN
INT5_WKUEN
INT4_WKUEN
INT3_WKUEN
--
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Condition
INT6 PAD wake up enable control, active high
INT5 PAD wake up enable control, active high
INT4 PAD wake up enable control, active high
INT3 PAD wake up enable control, active high
Reserved
5
4
3
2
1
INT1_WKUEN
INT0_WKUEN
INT1 PAD wake up enable control, active high
INT0 PAD wake up enable control, active high
Table 5-22 The WKUEN register
0
5.6. Interrupt System
5.6.1. Introduction
The GPM8F3132A/3116A/3108A provides 22 types of interrupt
sources (including 16 interrupt sources of standard 8051 and
additional 6 interrupt sources) with two levels interrupt priority
control which tabled in Table 5-23. For standard 8051 interrupt
sources, each interrupt can be in high or low level priority group by
setting or clearing a bit in the IP(0xB8) and EIP(0xF8) registers.
INT0 has the top priority in default state and user can choose the
related interrupt source to be the top priority by IP register. For
additional interrupt sources, high or low level priority group is set
or cleared a bit in the BIP(0x96).
interrupt request signal will be generated and then CPU executes
service routine. If the related interrupt control bit is disabled,
programmer still can observe the corresponding flag bit, but no
interrupt request signal will be generated. The interrupt flag bits
must be cleared in the interrupt service routine to prevent program
from deadlock in interrupt service routine. With any instruction,
interrupts pending during the previous instruction is served.
Before entering interrupt service routine, the system saves the
current PC address into top of stack pointer and jumps to
corresponding vector to execute the interrupt service. After
finishing the interrupt service, the system abstract the return PC
address from the top of the stack to execute the following
instruction.
Interrupt requests are sampled each system clock at the rising
edge of clock control. Each interrupt vector can be individually
enabled or disabled by setting or clearing a corresponding bit in
the IE(0xA8), EIE(0xE8). The IE contains global interrupt system
disable(0) / enable(1) bit called EA.
As to additional six interrupt sources, each interrupt vector can be
individually enabled or disabled by setting or clearing
a
In general, once an interrupt event occurs, the corresponding flag
bit will be set. The related registers of interrupt flag are described
as below.
corresponding bit in the AUDCON(0xB3), PWMIE(0xB2),
ADCON(0xF1) and RSTCON(0x8F). The corresponding flag can
be found in BIF(0x97), PWMIF(0xB1) and ADCON(0xF1). For
detail description, please refer to related block.
If the related interrupt control bit is set to enable interrupt, an
Interrupt flag
Function
Active level/edge
Flag resets
Vector
0x03
0x0B
0x13
0x1B
0x23
Vector number
Priority
IE0
Device pin INT 0
Internal Timer 0
Device pin INT 1
Internal Timer 1
AUDIO interrupt
Internal UART0
MOTOR_PWM interrupt
Internal Timer2
Timer2 external reload
ADC interrupt
Low/Falling
Hardware
0
1
2
3
4
1
2
3
4
5
TF0
-
Hardware
IE1
Low/Falling
Hardware
TF1
-
-
Hardware
AUDIOF
TI0 & RI0
MOTORF
TF2
Software(cleared by 1)
Software(cleared by 0)
Software(cleared by 1)
Software(cleared by 0)
Software(cleared by 0)
Software(cleared by 1)
--
-
0x2B
5
6
EXF2
ADCF
Reserved
INT3F
-
0x33
0x3B
0x43
6
7
8
7
8
9
--
--
Device pin /INT3
Internal Compare 0
Device pin /INT4
Internal Compare 1
Low
Hardware
Software(cleared by 1)
Hardware
INT4F
Low
0x4B
9
10
Software(cleared by 1)
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GPM8F3132A/3116A/3108A
Interrupt flag
Function
Active level/edge
Flag resets
Vector
Vector number
Priority
INT5F
Device pin /INT5
Falling
Software(cleared by 1)
Software(cleared by 1)
Software(cleared by 1)
Software(cleared by 1)
Software(cleared by 0)
Software(cleared by 1)
Software(cleared by 1)
Software(cleared by 1)
0x53
10
11
Internal Compare 2
Device pin /INT6
INT6F
Falling
0x5B
11
12
Internal Compare 3
Internal Watchdog
Memory access Error
Over-current interrupt
HS changes interrupt
WDIF
-
0x63
0x6B
0x73
0x7B
12
13
14
15
13
14
15
16
MERRF
OCF
-
Falling
Falling
HS_CHGF
Note1: Interrupt is also generated at falling edge of T2EX pin, while EXEN2 bit is set. This interrupt doesn’t set TF2 flag, but EXF2 only and uses 0x2B vector.
Note2: External interrupt pins are activated at low level or by a falling edge.
Note3: MOTORF can only be read in BIF register. It contains five kinds of flags which are described in PWMIF register.
Table 5-23 Summaries of all interrupt sources
IP
Address: 0xB8
Interrupt Priority Register
Bit
7
-
6
--
0
5
PT2
0
4
PS0
0
3
PT1
0
2
PX1
0
1
PT0
0
0
PX0
0
Function
Default
0
Bit
7:6
5
Function
--
Type
Description
Condition
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
PT2
PS0
PT1
PX1
PT0
PX0
Timer 2 priority level control (1: high level)
UART0 priority level control (1: high level)
Timer 1 priority level control (1: high level)
INT1 priority level control (1: high level)
Timer 0 priority level control (1: high level)
INT0 priority level control (1: high level)
Table 5-24 IP register
4
3
2
1
0
EIP
Address: 0xF8
Extended Interrupt Priority Register
Bit
7
--
0
6
--
0
5
PWDI
0
4
PINT6
0
3
PINT5
0
2
PINT4
0
1
0
--
0
Function
Default
PINT3
0
Bit
7
Function
--
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
Reserved
Condition
6
--
5
PWDI
PINT6
PINT5
PINT4
PINT3
--
Watchdog priority level control (1: high level)
4
INT6/Compare3 priority level control (1: high level)
INT5/Compare2 priority level control (1: high level)
INT4/Compare1 priority level control (1: high level)
INT3/Compare0 priority level control (1: high level)
Reserved
3
2
1
0
Table 5-25 EIP register
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BIP
Address: 0x96
Additional Interrupt Priority Register
Bit
7
--
0
6
--
0
5
POC
0
4
PAUDIO
0
3
PADC
0
2
PHS_CHG
0
1
PMOTOR
0
0
PMERR
0
Function
Default
Bit
7
Function
--
Type
Description
Reserved
Reserved
Condition
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
--
5
POC
Over-current priority level control (1: high level)
AUDIO priority level control (1: high level)
ADC priority level control (1: high level)
4
PAUDIO
PADC
3
2
PHS_CHG
PMOTOR
PMERR
Hall-sensor change priority level control (1: high level)
MOTOR_PWM priority level control (1: high level)
MERR priority level control (1: high level)
1
0
Table 5-26 BIP register
IE
Address: 0xA8
Interrupt Enable Register
Bit
7
EA
0
6
--
0
5
ET2
0
4
ES0
0
3
ET1
0
2
EX1
0
1
ET0
0
0
EX0
0
Function
Default
Bit
7
Function
EA
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Condition
Enable global interrupts
Reserved
6
--
5
ET2
ES0
ET1
EX1
ET0
EX0
Enable Timer 2 interrupt
Enable UART0 interrupt
Enable Timer 1 interrupt
Enable INT1 interrupt
Enable Timer 0 interrupt
Enable INT0 interrupt
4
3
2
1
0
Table 5-27 IE register
EIE
Address: 0xE8
Extended Interrupt Enable Register
Bit
7
-
6
-
5
4
EINT6
0
3
EINT5
0
2
EINT4
0
1
0
--
0
Function
Default
EWDI
0
EINT3
0
0
0
Bit
7
Function
--
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
Reserved
Condition
6
--
5
EWDI
EINT6
EINT5
EINT4
EINT3
--
Enable watchdog interrupt
4
Enable INT6/Compare3 interrupts
Enable INT5/Compare2 interrupts
Enable INT4/Compare1 interrupts
Enable INT3/Compare0 interrupts
Reserved
3
2
1
0
Table 5-28 EIE register
31
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GPM8F3132A/3116A/3108A
TCON
Bit
Address: 0x88
Timer0/1 Configuration Register
7
TF1
0
6
TR1
0
5
TF0
0
4
TR0
0
3
IE1
0
2
IT1
0
1
IE0
0
0
IT0
0
Function
Default
Bit
7
Function
TF1
Type
Description
Condition
R/W
R/W
Timer 1 interrupt (overflow) flag
Timer 1 run control bit
6
TR1
0: disabled ;
1: enabled
5
4
TF0
TR0
R/W
R/W
Timer 0 interrupt (overflow) flag
Timer 0 run control bit
0: disabled ;
1: enabled
3
2
1
0
IE1
IT1
IE0
IT0
R/W
R/W
R/W
R/W
INT1 interrupt flag
INT1 level (at 0) / edge (at 1) sensitivity
INT0 interrupt flag
INT0 level (at 0) / edge (at 1) sensitivity
Table 5-29 TCON register
T2IF
Address: 0xC9
Timer 2 Interrupt Flag Register
Bit
7
--
0
6
--
0
5
--
0
4
--
0
3
--
0
2
EXEN2
0
1
EXF2
0
0
TF2
0
Function
Default
Bit
Function
Type
Description
Condition
7:3
--
R/W
Reserved
Timer 2 external reload interrupt enable
0: external reload interrupt is disabled
1: external reload interrupt is enabled.
Timer 2 external reload flag
2
EXEN2
R/W
1
0
EXF2
TF2
R/W
R/W
Cleared by the software
Timer 2 overflow flag
Cleared by the software
Table 5-30 T2IF register
WDCON
Bit
Address: 0xD8
Watchdog Control Register
7
--
0
6
--
0
5
--
0
4
--
0
3
WDIF
0
2
WTRF
0
1
EWT
0
0
RWT
0
Function
Default
Bit
7:4
3
Function
Type
Description
Condition
--
R/W
R/W
R/W
R/W
Reserved
WDIF
WTRF
EWT
Watchdog interrupt flag
2
Watchdog timer reset flag
Watchdog timer reset enable bit
1
0: Disable;
1: Enable
0
RWT
R/W
Reset watchdog timer
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Bit
Function
Type
Description
Condition
0: NA;
1: Reset
Table 5-31 WDCON register
SCON0
Bit
Address: 0x98
UART0 configuration register
7
SM00
0
6
SM01
0
5
SM02
0
4
REN0
0
3
TB08
0
2
RB08
0
1
TI0
0
0
RI0
0
Function
Default
Bit
7:6
5
Function
SM0[1:0]
SM02
Type
R/W
R/W
R/W
R/W
R/W
Description
Condition
Mode and baud rate setting
Enables a multiprocessor communication feature
Enable serial reception.
4
REN0
3
TB08
The 9th transmitted data bit in Modes 2 and Mode 3
In Mode 0, this bit is not used
2
RB08
In Mode 1, if SM02 is 0, RB08 is the stop bit.
In Mode 2 and Mode 3, it is the 9th data bit received.
UART0 transmitter interrupt flag
1
0
TI0
RI0
R/W
R/W
UART0 receiver interrupt flag
Table 5-32 SCON0 register
EIF
Address: 0x91
Extended interrupt flag
Bit
7
--
0
6
--
0
5
--
0
4
INT6F
0
3
INT5F
0
2
INT4F
0
1
INT3F
0
0
--
0
Function
Default
Bit
7:5
4
Function
--
Type
R/W
R/W
R/W
R/W
R/W
R/W
Description
Condition
Reserved
INT6F
INT5F
INT4F
INT3F
--
INT6 interrupt flag/ Compare3 interrupt flag
INT5 interrupt flag/ Compare2 interrupt flag
INT4 interrupt flag/ Compare1 interrupt flag
INT3 interrupt flag/ Compare0 interrupt flag
Reserved
3
2
1
0
Table 5-33 EIF register
BIF
Address: 0x97
Additional interrupt flag
Bit
7
--
0
6
--
0
5
OCF
0
4
AUDIOF
0
3
ADCF
0
2
HS_CHGF
0
1
MOTORF
0
0
MERRF
0
Function
Default
Bit
7:6
5
Function
--
Type
R/W
R
Description
Condition
Reserved
OCF
Over-current interrupt flag, cleared by 1 in PWMIF[0]
AUDIO interrupt flag, cleared by 1
4
AUDIOF
ADCF
R/W
R
3
ADC interrupt flag, cleared by 1 in ADCON register
Hall-sensor change interrupt flag, cleared by 1 in PWMIF[6]
2
HS_CHGF
R
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Bit
1
Function
MOTORF
MERRF
Type
R
Description
Condition
MOTOR_PWM interrupt flag, cleared by 1 in PWMIF register
IMemory related error interrupt flag, cleared by 1
Table 5-34 BIF register
0
R/W
5.7. Reset Sources
5.7.1. Introduction
Timer Reset (WDT_RST), Software Reset (S/W_RST), STOP
mode Reset (STOP_RST), Flash Error Reset (FLASH_ERR_RST),
and missing system clock Reset (MISS_CLK_RST). Figure 5-6
shows the block diagram of each reset source.
There are eight types of reset sources for the
GPM8F3132A/3116A/3108A including Power-On Reset (POR),
Low Voltage Reset (LVR), Pad Reset (RAD_RST), Watchdog
LVR_POR
Macro
RESET_pad
PAD_RST
LVR
RST filter
POR
rst
WDT_RST
S/W_RST
8051
STOP_RST
FLASH_ERR_RST
clkrun
Missing Clock
Detect
MISS_CLK_RST
RESET
module
SYSRESET
Figure 5-6 Reset sources
5.7.2. Power-On Reset (POR)
function is enabled, the LVR circuit will monitor power level while
chip is operating. And the LVR voltage level can be 2.2V or 3.9V
by setting CONFIG_BYTE[5] through 2-wire interface. If the
power is lower than the specific level for a specific period, the
system reset will take place and go to initial state.
A POR is generated when VDD is rising from 0v. When VDD
rises to an acceptable level (~1.5V), the power on reset circuit will
starts a power-on sequence. After that, the system starts to
activate and will operate in target speed. The POR will reset
whole chip and registers.
5.7.4. Pad Reset (PAD_RST)
5.7.3. Low Voltage Reset (LVR)
The GPM8F3132A/3116A/3108A provides an external pin to force
the system returning to its initial status. The RESET pin is high
active as shown in Figure 5-7. When the RESET pin equals to
VDD, system will be forced to enter reset state, execute instruction
from address 0x0000 and all registers go to default state.
The on-chip Low Voltage Reset (LVR) circuitry forces the system
entering reset state when power supplying voltage falls below the
specific LVR trigger voltage. This function prevents MCU from
working at an invalid operating voltage range.
To enable or disable this function, SYSCON0[7] can be set. If this
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VDD
clk
217
23
23
23
External
Internal
217
220
223
226
30pF
WD1
WD0
Timeout selector
RESET pin
WDIF
Watchdog interrupt
EWDI
EWT
512 CLK delay
RESET
WTRF
Figure 5-8 The block diagram of Watchdog timer
5.7.6. Other Reset Sources
Other reset sources includes Software Reset (S/W_RST), STOP
mode Reset (STOP_RST), Flash Error Reset (FLASH_ERR_RST),
and missing system clock Reset (MISS_CLK_RST). Software
Reset is occurred when writing KEY code to KEYCODE
register(0xEF). The key codes are 0x3c and 0xc3. The timing
does not matter, but the key codes must be written in order before
SW reset is take place. STOP mode Reset is enabled by setting
PCON[3] bit. This is the reset when system is reset from STOP
mode.
Figure 5-7 Pad reset circuit
5.7.5. Watchdog Timer Reset (WDT_RST)
On-chip watchdog circuitry makes the device entering reset state
when MCU goes into unknown state and has no watchdog cleared
information. This function prevents the MCU to be stuck in an
abnormal condition. The WDT can be enabled or disabled
through WDCON register bit 1. At any time prior to reaching its
user selected terminal value, software can set the Reset Watchdog
Timer (WDCON[0]) bit. If RWT is set before the timeout is
reached, the timer will start over. If timeout is reached without
RWT being set, the watchdog will reset the CPU. Hardware will
automatically clear RWT after software sets it. When the reset
occurs, the Watchdog Timer Reset Flag (WDCON[2]) will
automatically be set to indicate the cause of the reset, however
software must clear this bit manually.
Flash Error Reset is the reset when five flash related errors are
arisen. The first error is to execute whole chip erase by software.
The second error is to access the wrong address. The third error
is when flash is programmed in a wrong way or to program
READONLY_PAGE. The forth error is to erase LAST_PAGE and
the last error is to program CONFIG_BYTE. Each flash error
related reset source can be enabled or disabled by clearing or
setting a bit in the RSTCON(0x8F) as shown in Table 5-42. The
corresponding flag when flash error reset occurs can be observed
in FLASHERRF register which is shown in Table 5-43. Missing
system clock Reset is the reset when system clock is missed over
4095 IOSC clocks if external crystal is utilized as clock source.
There are seven reset status flag can be monitored by RSTSTS
register which is shown as Table 5-44.
WDCON register is a timed access register that prevent it from
accidental writes. TA is located at 0xEB. Correct sequence,
0xAA and 0x55, is required before write to WDCON register.
Reading from such register is not protected.
The Watchdog has four timeout selections based on the system
clock frequency. The selections are a pre-selected number of
clocks and can be set by CKCON[7:6]. Therefore, the actual
timeout interval is dependent on the SYSCLK frequency. Figure
5-8 shows the block diagram of Watchdog timer.
CONFIG_BYTE
Bit
Address: 0xB7
CONFIG_BYTE Register
7
--
1
6
--
1
5
LVRVSEL
1
4
--
1
3
--
1
2
--
1
1
IOSEL
1
0
Function
Default
CODE Lock
1
Bit
Function
Type
Description
Condition
7:6
--
R
Reserved
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GPM8F3132A/3116A/3108A
Bit
Function
Type
Description
Condition
5
LVRVSEL
R
LVR voltage level selection
0: 3.9V
1: 2.2V
4:2
1
--
R
R
R
Reserved
IO initial state selection bit
0: Input pull high
IOSEL
1: floating
0
CODE Lock
0 : CODE is locked; 1 : CODE is unlocked
Table 5-35 The CONFIG_BYTE register
SYSCON0
Bit
Address: 0xAE
SYSTEM control0 Register
7
LVRENB
0
6
5
4
3
--
0
2
1
0
Function
SCHMIT_DIS_
--
0
--
0
AUDIO_N_DIS
0
CLKOUT_EN CCOUTENB
P4
0
Default
0
0
Key Code
FF,00
Bit
Function
Type
Description
Condition
7
LVRENB
R/W
LVR enable control
0: enable LVR function
1: disable LVR function
Reserved
6:5
4
--
--
AUDIO_N_DIS
R/W
AUDIO_N disable bit available only if audio function is enabled
0: P36/P37 are output simultaneously as AUDIO_N/P
1: Only P37 is output as AUDIO_P
3
2
1
--
--
Reserved
CLKOUT_EN
CCOUTENB
R/W
R/W
Clock output enable bit (SYSCLK is output on P35)
Disable output function of compare mode in Timer2
0: P1[3:1] = {compare3,compare2,compare1}
1: P1[3:1] is GPIO
0
SCHMIT_DIS_P4
R/W
P4 schmitt trigger function disable control bit
Table 5-36 SYSCON0 register
WDCON
Bit
Address: 0xD8
Watchdog Control Register
7
--
0
6
5
--
0
4
--
0
3
WDIF
0
2
WTRF
0
1
0
RWT
0
Function
Default
--
0
EWT
0
Bit
7:4
3
Function
--
Type
R/W
R/W
R/W
R/W
Description
Condition
Reserved
WDIF
WTRF
EWT
Watchdog interrupt flag
Watchdog timer reset flag
Watchdog timer reset enable bit
0: Disable
2
1
1: Enable
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Bit
Function
Type
Description
Reset watchdog timer
0: NA
Condition
0
RWT
R/W
1: Reset
Table 5-37 WDCON register
TA
Address: 0xEB
Timed Access Protection Register
Bit
7
0
6
0
5
4
3
2
1
0
0
0
Function
Default
Timed Access protection register (0xaaÎ0x55)
0
0
0
0
Bit
Function
Type
Description
Condition
7:0
TA[7:0]
R/W
Timed Access protection register (0xaaÎ0x55)
Table 5-38 TA register
CKCON
Bit
Address: 0x8E
Clock Control Register
7
WD1
0
6
WD0
0
5
--
0
4
T1M
0
3
T0M
0
2
--
0
1
--
0
0
--
1
Function
Default
Bit
Function
Type
Description
Condition
7:6
WD[1:0]
R/W
Watchdog timeout selection bits
WD[1:0]
00
Watchdog internal
Number of clocks
131072
217
220
223
226
01
1048576
10
8388608
11
67108864
5
4
--
R/W
R/W
Reserved
T1M
Division selection of the system clock that drives Timer 1
0: Timer 1 uses a divided-by-12 of the system clock frequency
1: Timer 1 uses a divided-by-4 of the system clock frequency
Division selection of the system clock that drives Timer 0
0: Timer 0 uses a divided-by-12 of the system clock frequency
1: Timer 0 uses a divided-by-4 of the system clock frequency
Reserved
3
T0M
--
R/W
R/W
2:0
Table 5-39 CKCON register
KEYCODE
Bit
Address: 0xEF
KEYCODE Register
7
KC7
0
6
KC6
0
5
KC5
0
4
KC4
0
3
KC3
0
2
KC2
0
1
0
KC0
0
Function
Default
KC1
0
Bit
Function
Type
Description
Condition
7:0
KEYCODE[7:0]
R/W
KEYCODE register
Note: Some protected registers are needed to write correct key code to KEYCODE register before write data to them.
Table 5-40 KEYCODE register
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PCON
Bit
Address: 0x87
Power Configuration Register
7
SMOD0
0
6
--
0
5
4
PWE
0
3
2
--
0
1
STOP
0
0
--
0
Function
Default
CPU_IDLE
0
STOP_RST_EN
0
Bit
7
Function
SMOD0
--
Type
Description
Condition
R/W
R/W
R/W
UART0 double baud rate bit when clocked by Timer1
Reserved
6
5
CPU_IDLE
IDLE mode enable bit
0: IDLE mode disabled ;
1: IDLE mode entered
4
3
PWE
R/W
R/W
Program Write Enable (PWE)
0: Disable Flash write activity during MOVX instruction
1: Enable Flash write activity during MOVX instruction
Wakeup state selection bit
0: Next instruction state after wakeup
1: Reset state afer wakeup
Reserved
STOP_RST_EN
2
1
--
R/W
R/W
STOP
STOP mode enable bit
0: Disabled
1: Enabled
0
--
R/W
Reserved
Table 5-41 PCON register
RSTCON
Bit
Address: 0x8F
Flash Error RESET Enable Control Register
7
6
5
4
3
2
1
0
Function
FLASH_FLOW
CB_P_ENB LP_E_ENB
XADDR_ENB -- CHIP_E_ENB MISS_CLK_ENB FLASH_ERR__ENB
_ENB
0
Default
0
0
1
0
0
0
0
Key Code
4F,72,7A
Bit
7
Function
Type
Description
Condition
CB_P_ENB
LP_E_ ENB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CONFIG_BYTE program reset disable control bit
LAST_PAGE erase reset disable control bit
6
5
FLASH_FLOW_ ENB
XADDR_ENB
--
Error flash flow/READONLY_PAGE program reset disable control bit
Error flash address access reset disable control bit
Reserved
4
3
2
CHIP_E_ ENB
MISS_CLK _ ENB
FLASH_ERR _ ENB
Whole chip erase reset disable control bit
Miss clock reset disable control bit
1
0
Global Flash related error reset disable control bit
Table 5-42 RSTCON register
FLASHERRF
Bit
Address: 0xA6
Flash Error RESET Status Flag Register
7
CB_P_F
0
6
LP_E_F
0
5
4
3
--
0
2
CHIP_E_F
0
1
--
0
0
--
0
Function
Default
FLASH_FLOW_F XADDR_F
0
0
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GPM8F3132A/3116A/3108A
Bit
7
Function
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Condition
CB_P_F
Error CONFIG_BYTE program reset flag
Error LAST_PAGE erase reset flag
Error flash flow/ READONLY_PAGE program reset flag
Error flash address access reset flag
Reserved
6
LP_E_F
5
FLASH_FLOW_F
4
XADDR_F
3
--
2
CHIP_E_F
Error Macro erase reset flag
Reserved
1
--
--
0
Reserved
Table 5-43 FLASHERRF register
RSTSTS
Bit
Address: 0x94
RESET Status Flag Register
7
6
5
4
3
2
1
LVR_RST
0
0
RAD_RST
0
Function
Default
--
0
MISS_CLK_RST
0
STOP_RST
0
FLASH_ERR_RST
0
S/W_RST
WDT_RST
0
0
Bit
7
Function
--
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
Condition
6
MISS_CLK_RST
STOP_RST
FLASH_ERR_RST
SW_RST
RESET from system clock missing clock
RESET from STOP mode
RESET from FLASH error
RESET from SW RST
5
4
3
2
WDT_RST
LVR_RST
RESET from WDT
1
RESET from LVR
0
PAD_RST
RESET from RESET PAD
Table 5-44 RSTSTS register
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GPM8F3132A/3116A/3108A
5.8. I/O Ports
5.8.1. Introduction
PU
0
PD
0
DATA
PAD
The GPM8F3132A/3116A/3108A has five ports, including standard
Port 0, Port 1, Port 2, Port 3 and additional Port 4. These port
pins may be multiplexed with an alternate function for the
peripheral features on the device. In general, when an initial
reset state occurs, all ports are used as a general purpose input
port with open-drain structure and Schmitt trigger function. User
can change IO initial state by CONFIG_BYTE[1] through the
0
1
0
1
0
1
0
1
Driving Low
Floating
0
0
0
1
Driving Low
Pull low
0
1
1
0
Illegal
1
0
Pull high
Driving Low
Driving High
SCK/SDA interface.
The Schmitt trigger function can be
1
1
controlled by SYSCON2[3:0] and SYSCON0[0]. All the input
ports can be programmable pull high/low by PU and PD registers.
The PU and PD registers of Port 0 are controlled by 0x9A and
0x9B, the PU and PD registers of Port 1 are controlled by 0x9C
and 0x9D, the PU and PD registers of Port 2 are controlled by
0x9E and 0x9F, the PU and PD registers of P3 are controlled by
0xA2 and 0xA3 and the PU and PD registers of P4 are controlled
by 0xA4 and 0xA5. Read and write accesses to the I/O port are
performed via their corresponding SFRs P0(0x80), P1(0x90),
P2(0xA0), P3(0xB0) and P4(0xA1). When PU and PD are
enabled at the same time, the port can output high or low
depending on the data. Table 5-45 and Table 5-46 show the truth
1
1
Table 5-46 The truth table of digital pad
ANAEN
ANAIP
OE=~DATA | (PU &PD)
DATA
50K
PU & ~PD
IP
table of analog pad and digital pad respectively.
In
GPM8F3132A/3116A/3108A, P0[7:0], P2[6:5] and P4[1:0] can be
analog pad for special function. P0[7:0] are used for ADC input.
P2[6:5] are used for external crystal input and output. P4[1:0] are
used for compare input. The detail descriptions of analog
function are in corresponding sections. The built-in pull high/low
resister is 50KΩ. In addition to this, there is a register, SRCON,
for slew rate control (0xAD) of P0~P4. If IO ports are needed to
change immediately without slew rate control, the corresponding
control bit of each port can be set to ‘0’. The default state of
SRCON register is ‘0xFF’ with 30ns slew rate control. Figure 5-9
and Figure 5-10 show the block diagrams of analog pad and digital
pad respectively.
50K
PD & ~PU
Figure 5-9 The block diagram of analog pad
OE=~DATA | (PU&PD)
DATA
PU & ~PD
50K
IP
PU
0
PD
0
DATA
ADAEN
PAD
50K
PD & ~PU
0
1
0
1
0
1
0
1
x
0
0
0
0
0
0
0
0
1
Driving Low
Floating
0
0
0
1
Driving Low
Pull low
Figure 5-10 The block diagram of digital pad
0
1
1
0
Illegal
1
0
Pull high
Driving Low
Driving High
Floating
1
1
1
1
x
x
Table 5-45 The truth table of analog pad
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GPM8F3132A/3116A/3108A
CONFIG_BYTE
Bit
Address: 0xB7
CONFIG_BYTE Register
7
--
1
6
--
1
5
LVRVSEL
1
4
--
1
3
--
1
2
--
1
1
IOSEL
1
0
Function
Default
CODE Lock
1
Bit
7:6
5
Function
--
Type
Description
Condition
R
R
Reserved
LVRVSEL
LVR voltage level selection
0: 3.9V
1: 2.2V
4:2
1
--
R
R
R
Reserved
IO initial state selection bit
0: Input pull high
1: floating
IOSEL
0
CODE Lock
0 : CODE is locked; 1 : CODE is unlocked
Table 5-47 The CONFIG_BYTE register
P0
Address: 0x80
Port0 Register
Bit
7
P07
1
6
P06
1
5
P05
1
4
P04
1
3
P03
1
2
P02
1
1
P01
1
0
P00
1
Function
Default
Bit
Function
Type
Description
Condition
7:0
P0[7:0]
R/W
Port0
Table 5-48 P0 register
P1
Address: 0x90
Port1 Register
Bit
7
P17
1
6
P16
1
5
P15
1
4
P14
1
3
P13
1
2
P12
1
1
P11
1
0
P10
1
Function
Default
Bit
Function
Type
Description
Condition
7:0
P1[7:0]
R/W
Port1
Table 5-49 P1 register
P2
Address: 0xA0
Port2 Register
Bit
7
P27
1
6
P26
1
5
P25
1
4
P24
1
3
P23
1
2
P22
1
1
P21
1
0
P20
1
Function
Default
Bit
Function
Type
Description
Condition
7:0
P2[7:0]
R/W
Port2
Table 5-50 P2 register
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P3
Address: 0xB0
Port3 Register
Bit
7
P37
1
6
P36
1
5
P35
1
4
P34
1
3
P33
1
2
P32
1
1
P31
1
0
P30
1
Function
Default
Bit
Function
Type
R/W
Description
Condition
7:0
P3[7:0]
Port3
Table 5-51 P3 register
P4
Address: 0xA1
Port4 Register
Bit
7
P47
1
6
P46
1
5
P45
1
4
P44
1
3
P43
1
2
P42
1
1
P41
1
0
P40
1
Function
Default
Bit
Function
Type
Description
Condition
7:0
P4[7:0]
R/W
Port4
Table 5-52 P4 register
P0_PU
Bit
Address: 0x9A
Port0 pull up configuration Register
7
P07_PU
0
6
P06_PU
0
5
P05_PU
0
4
P04_PU
0
3
P03_PU
0
2
P02_PU
0
1
0
P00_PU
0
Function
Default
P01_PU
0
Bit
Function
Type
R/W
Description
Condition
7:0
P0_PU[7:0]
Port0 pull up control bits
0: floating; 1: pull up
Table 5-53 P0_PU register
P0_PD
Bit
Address: 0x9B
Port0 pull down configuration Register
7
P07_PD
0
6
5
P05_PD
0
4
P04_PD
0
3
P03_PD
0
2
P02_PD
0
1
P01_PD
0
0
P00_PD
0
Function
Default
P06_PD
0
Bit
Function
Type
R/W
Description
Condition
7:0
P0_PD[7:0]
Port0 pull down control bits
0: floating
1: pull down
Note: If P0_PU and P0_PD are setting to ‘1’ simultaneously, P0 will be output mode
Table 5-54 P0_PD register
P1_PU
Bit
Address: 0x9C
Port1 pull up configuration Register
7
P17_PU
0
6
P16_PU
0
5
P15_PU
0
4
P14_PU
0
3
P13_PU
0
2
P12_PU
0
1
0
P10_PU
0
Function
Default
P11_PU
0
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Bit
Function
Type
Description
Condition
7:0
P1_PU[7:0]
R/W
Port1 pull up control bits
0: floating
1: pull up
Table 5-55 P1_PU register
P1_PD
Bit
Address: 0x9D
Port1 pull down configuration Register
7
P17_PD
0
6
P16_PD
0
5
4
P14_PD
0
3
P13_PD
0
2
P12_PD
0
1
P11_PD
0
0
P10_PD
0
Function
Default
P15_PD
0
Bit
Function
Type
R/W
Description
Condition
7:0
P1_PD[7:0]
Port1 pull down control bits
0: floating
1: pull down
Note: If P1_PU and P1_PD are setting to ‘1’ simultaneously, P1 will be output mode.
Table 5-56 P1_PD register
P2_PU
Bit
Address: 0x9E
Port2 pull up configuration Register
7
P27_PU
0
6
P26_PU
0
5
P25_PU
0
4
P24_PU
0
3
P23_PU
0
2
P22_PU
0
1
0
P20_PU
0
Function
Default
P21_PU
0
Bit
Function
Type
R/W
Description
Condition
7:0
P2_PU[7:0]
Port2 pull up control bits
0: floating
1: pull up
Table 5-57 P2_PU register
P2_PD
Bit
Address: 0x9F
Port2 pull down configuration Register
7
P27_PD
0
6
P26_PD
0
5
4
P24_PD
0
3
P23_PD
0
2
P22_PD
0
1
P21_PD
0
0
P20_PD
0
Function
Default
P25_PD
0
Bit
Function
Type
R/W
Description
Condition
7:0
P2_PD[7:0]
Port2 pull down control bits
0: floating
1: pull down
Note: If P2_PU and P2_PD are setting to ‘1’ simultaneously, P2 will be output mode
Table 5-58 P2_PD register
P3_PU
Bit
Address: 0xA2
Port3 pull up configuration Register
7
P37_PU
0
6
P36_PU
0
5
P35_PU
0
4
P34_PU
0
3
P33_PU
0
2
P32_PU
0
1
0
P30_PU
0
Function
Default
P31_PU
0
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Bit
Function
Type
Description
Condition
7:0
P3_PU[7:0]
R/W
Port3 pull up control bits
0: floating
1: pull up
Table 5-59 P3_PU register
P3_PD
Bit
Address: 0xA3
Port3 pull down configuration Register
7
P37_PD
0
6
P36_PD
0
5
4
P34_PD
0
3
P33_PD
0
2
P32_PD
0
1
P31_PD
0
0
P30_PD
0
Function
Default
P35_PD
0
Bit
Function
Type
R/W
Description
Condition
7:0
P3_PD[7:0]
Port3 pull down control bits
0: floating
1: pull down
Note: If P3_PU and P3_PD are setting to ‘1’ simultaneously, P3 will be output mode.
Table 5-60 P3_PD register
P4_PU
Bit
Address: 0xA4
Port4 pull up configuration Register
7
P47_PU
0
6
P46_PU
0
5
P45_PU
0
4
P44_PU
0
3
P43_PU
0
2
P42_PU
0
1
0
P40_PU
0
Function
Default
P41_PU
0
Bit
Function
Type
R/W
Description
Condition
7:0
P4_PU[7:0]
Port4 pull up control bits
0: floating
1: pull up
Table 5-61 P4_PU register
P4_PD
Bit
Address: 0xA5
Port4 pull down configuration Register
7
P47_PD
0
6
P46_PD
0
5
4
P44_PD
0
3
P43_PD
0
2
P42_PD
0
1
P41_PD
0
0
P40_PD
0
Function
Default
P45_PD
0
Bit
Function
Type
R/W
Description
Condition
7:0
P4_PD[7:0]
Port4 pull down control bits
0: floating; 1: pull down
Note: If P4_PU and P4_PD are setting to ‘1’ simultaneously, P4 will be output mode.
Table 5-62 P4_PD register
SRCON
Bit
Address: 0xAD
Slew Rate Control Register
7
--
1
6
--
1
5
--
1
4
P4_SR
1
3
P3_SR
1
2
P2_SR
1
1
P1_SR
1
0
P0_SR
1
Function
Default
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GPM8F3132A/3116A/3108A
Bit
7:5
4
Function
--
Type
R/W
R/W
Description
Condition
Reserved
P4_SR
Port4 slew rate control bit
0: slew rate control disable
1: slew rate control enable 30ns
Port3 slew rate control bit
3
2
1
0
P3_SR
P2_SR
P1_SR
P0_SR
R/W
R/W
R/W
R/W
0: slew rate control disable
1: slew rate control enable 30ns
Port2 slew rate control bit
0: slew rate control disable
1: slew rate control enable 30ns
Port1 slew rate control bit
0: slew rate control disable
1: slew rate control enable 30ns
Port0 slew rate control bit
0: slew rate control disable
1: slew rate control enable 30ns
Table 5-63 SRCON register
SYSCON2
Bit
Address: 0xA7
SYSTEM control2 Register
7
ADCLKX2
0
6
--
0
5
4
3
2
1
0
Function
SCHMIT_DIS SCHMIT_DIS_ SCHMIT_DIS_ SCHMIT_DIS_
INT_filter_en GPIO_SSO
_P3
0
P2
0
P1
0
P0
0
Default
0
0
Key Code
FF,00
Bit
7
Function
ADCLKX2
--
Type
R/W
R/W
R/W
Description
Condition
ADCLK double enable bit
Reserved
6
5
INT_filter_en
INT0~INT2 pad filter enable bit
0: no filter
1: 2us
4
GPIO_SSO
R/W
GPIO SSO function enable bit
(Avoid GPIO change simultaneously)
3
2
1
0
SCHMIT_DIS_P3
SCHMIT_DIS_P2
SCHMIT_DIS_P1
SCHMIT_DIS_P0
R/W
R/W
R/W
R/W
P3 schmitt trigger function disable control bit
P2 schmitt trigger function disable control bit
P1 schmitt trigger function disable control bit
P0 schmitt trigger function disable control bit
Table 5-64 SYSCON2 register
SYSCON0
Bit
Address: 0xAE
SYSTEM control0 Register
7
6
5
4
3
--
0
2
1
0
Function
SCHMIT_DIS_
LVRENB
--
0
--
0
AUDIO_N_DIS
0
CLKOUT_EN CCOUTENB
P4
0
Default
0
0
0
Key Code
FF,00
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GPM8F3132A/3116A/3108A
Bit
Function
Type
Description
Condition
7
LVRENB
R/W
LVR enable control
0: enable LVR function
1: disable LVR function
Reserved
6:5
4
--
--
AUDIO_N_DIS
R/W
AUDIO_N disable bit available only if audio function is enabled
0: P36/P37 are output simultaneously
1: Only P37 is output
3
2
1
--
--
Reserved
CLKOUT_EN
CCOUTENB
R/W
R/W
Clock output enable bit (SYSCLK is output on P35)
Disable output function of compare mode in Timer2
0: P1[3:1] = {compare3,compare2,compare1}
1: P1[3:1] is GPIO
0
SCHMIT_DIS_P4
R/W
P4 schmitt trigger function disable control bit
Table 5-65 SYSCON0 register
ADAEN
Bit
Address: 0xF3
ADC analog PAD enable Register
7
P07_AEN
0
6
5
P05_AEN
0
4
P04_AEN
0
3
P03_AEN
0
2
P02_AEN
0
1
P01_AEN
0
0
P00_AEN
0
Function
Default
P06_AEN
0
Bit
Function
Type
Description
Condition
7
P07_AEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P07 analog PAD enable control bit
0: P07 can be I/O PAD
1: P07 can be analog PAD
P06 analog PAD enable control bit
0: P06 can be I/O PAD
6
5
4
3
2
1
0
P06_AEN
P05_AEN
P04_AEN
P03_AEN
P02_AEN
P01_AEN
P00_AEN
1: P06 can be analog PAD
P05 analog PAD enable control bit
0: P05 can be I/O PAD
1: P05 can be analog PAD
P04 analog PAD enable control bit
0: P04 can be I/O PAD
1: P04 can be analog PAD
P03 analog PAD enable control bit
0: P03 can be I/O PAD
1: P03 can be analog PAD
P02 analog PAD enable control bit
0: P02 can be I/O PAD
1: P02 can be analog PAD
P01 analog PAD enable control bit
0: P01 can be I/O PAD
1: P01 can be analog PAD
P00 analog PAD enable control bit
0: P00 can be I/O PAD
1: P00 can be analog PAD
Table 5-66 ADAEN register
46
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GPM8F3132A/3116A/3108A
IOSCCON
Bit
Address: 0xF9
IOSC Control Register
7
XTO_AEN
0
6
XTI_AEN
0
5
4
3
2
1
0
1
Function
Default
XTAL_PAD_EN
0
OSC_SEL[1:0]
CLKDIV[2:0]
0
0
1
0
Bit
Function
Type
Description
7
XTO_AEN
R/W
XTO analog PAD enable control bit
0: XTO can be I/O PAD
1: XTO can be analog PAD
XTI analog PAD enable control bit
0: XTI can be I/O PAD
6
XTI_AEN
R/W
1: XTI can be analog PAD
5
XTAL_PAD_EN
OSC_SEL[1:0]
R/W
R/W
If using XTAL or ECLK, XTAL_PAD_EN should be set first for OSC_SEL selection.
4:3
00: Internal ROSC
01: Internal ROSC
10: XTAL
11: External CLK
If using XTAL, OSC_SEL[1](XTAL_EN) should be set after XOSC_CLK is stable
System Clock source divider
2:0
CLK_DIV
R/W
CLK_DIV
000
Clock control
SYSCLK_source
SYSCLK_source/2
SYSCLK_source/4
SYSCLK_source/8
SYSCLK_source/16
SYSCLK_source/32
SYSCLK_source/64
SYSCLK_source/1.5
001
010
011
100
101
110
111
Table 5-67 The IOSCCON register
CMPCON1
Bit
Address: 0xAA
Comparator Control Register 1
7
--
0
6
--
0
5
--
0
4
P41_AEN
0
3
P40_AEN
0
2
1
0
CMP_EN
0
Function
Default
HU_DET_SEL SCHMIT_EN
1
0
Bit
Function
Type
Description
Condition
7:5
4
--
R/W
R/W
Reserved
P41 analog PAD enable control bit
0: P41 can be I/O PAD
P41_AEN
1: P41 can be analog PAD
P40 analog PAD enable control bit
0: P40 can be I/O PAD
3
2
R/W
R/W
P40_AEN
1: P40 can be analog PAD
HU_DET pad select control bit
0: P43 is used as HU_DET pad
1: P07 is used as HU_DET pad
HU_DET_SEL
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Bit
Function
Type
Description
Condition
1
SCHMIT_EN
R/W
0: Disable schmitt window
1: Enable schmitt window (30mV)
0
CMP_EN
R/W
Enable three comparators to produce sensorless signals
Table 5-68 CMPCON1 register
5.9. Timer Module
5.9.1. Introduction
GPM8F3132A/3116A/3108A is equipped with three timers. They
are Timer 0, Timer 1 and Timer 2 respectively. In addition, Timer
2 also features Compare/Capture/Reload function. All of these
three timers are up-count timers and 16-bit timer/counter. Each
timer’s function is described in the following sections.
TL0(0x8A), TH1(0x8D), TL1(0x8B). Timers 0 and Timer 1 work in
the same three modes except for mode 3 and the related control
registers are TMOD(0x89), TCON(0x88) and CKCON(0x8E)
registers. In the timer mode, timer registers are incremented
every 4/12 SYSCLK periods depends on CKCON(0x8E) setting,
when appropriate timer is enabled. In the counter mode, the
timer registers are incremented every falling transition on theirs
corresponding input pins: T0 or T1. The input pins are sampled
every CLK period.
5.9.2. Timer 0/1
Timer 0 and Timer 1 are fully compatible with the standard 8051
timers. Each timer consists of two 8-bit registers TH0(0x8C),
TH0
Address: 0x8C
Timer0 High Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TH0[7:0]
0
0
0
Bit
Function
Type
R/W
Description
Condition
7:0
TH0[7:0]
Timer 0 Load value – high byte
Table 5-69 TH0 register
TL0
Address: 0x8A
Timer0 Low Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TL0[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
TL0[7:0]
R/W
Timer 0 Load value – low byte
Table 5-70 TL0 register
TH1
Address: 0x8D
Timer1 High Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TH1[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
TH1[7:0]
R/W
Timer 1 Load value – high byte
Table 5-71 TH1 register
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TL1
Address: 0x8B
Timer1 Low Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TL1[7:0]
0
0
0
Bit
Function
Type
R/W
Description
Condition
7:0
TL1[7:0]
Timer 1 Load value – low byte
Table 5-72 TL1 register
TMOD
Bit
Address: 0x89
Timer0/1 Control Mode Register
7
GATE1
0
6
CT1
0
5
M11
0
4
M10
0
3
GATE0
0
2
CT0
0
1
0
Function
Default
M01
M00
0
0
Bit
Function
Type
Description
Condition
7
GATE1
R/W
Gating control
0: Timer 1 enabled while TR1 control bit is set
1: Timer 1 enabled while GATE1 pin is high and TR1 control bit is set
Counter or timer select bit
6
CT1
R/W
0: Timer mode, internally clocked
1: Counter mode, Timer 1 clock source is from T1 pin
Mode select bits of timer 1, which is tabled as Table 5-74
Gating control
5:4
3
M1[1:0]
GATE0
R/W
R/W
0: Timer 0 enabled while TR0 control bit is set
1: Timer 0 enabled while GATE0 pin is high and TR0 control bit is set
Counter or timer select bit
2
CT0
R/W
R/W
0: Timer mode, internally clocked
1: Counter mode, Timer 0 clock source is from T0 pin
Mode select bits of timer 0, which is tabled as Table 5-74
1:0
M0[1:0]
Table 5-73 TMOD register
M1
0
M0
0
Mode
Function description
0
1
2
3
TH0/1 operates as 8-bit timer/counter with a divide by 32 pre-scaler served by lower 5-bit of TL0/1.
16-bit timer/counter. TH0/1 and TL0/1 are cascaded
0
1
1
0
TL0/1 operates as 8-bit timer/counter with 8-bit auto-reload by TH0/1
1
1
TL0 is configured as 8-bit timer/counter controlled by the standard Timer 0 bits. TH0 is an 8-bit
timer controlled by the Timer 1 controls bits. Timer 1 holds its count.
Table 5-74 Four modes of Timer 0 and Timer 1
TCON
Bit
Address: 0x88
Timer0/1 Configuration Register
7
6
TR1
0
5
TF0
0
4
TR0
0
3
IE1
0
2
IT1
0
1
IE0
0
0
IT0
0
Function
Default
TF1
0
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Bit
7
Function
TF1
Type
R/W
R/W
Description
Condition
Timer 1 interrupt (overflow) flag
Timer 1 run control bit
0: disabled ;
6
TR1
1: enabled
5
4
TF0
TR0
R/W
R/W
Timer 0 interrupt (overflow) flag
Timer 0 run control bit
0: disabled ;
1: enabled
3
2
1
0
IE1
IT1
IE0
IT0
R/W
R/W
R/W
R/W
INT1 interrupt flag
INT1 level (at 0)/ edge (at 1) sensitivity
INT0 interrupt flag
INT0 level (at 0)/ edge (at 1) sensitivity
Table 5-75 TCON register
CKCON
Bit
Address: 0x8E
Clock Control Register
7
WD1
0
6
WD0
0
5
4
T1M
0
3
T0M
0
2
MD2
0
1
MD1
0
0
MD0
1
Function
Default
--
0
Bit
Function
Type
Description
Condition
7:6
WD[1:0]
R/W
Watchdog timeout selection bits
WD[1:0]
00
Watchdog internal
Number of clocks
131072
217
220
223
226
01
1048576
10
8388608
11
67108864
5
4
--
R/W
R/W
Reserved
T1M
Division selection of the system clock that drives Timer 1
0: Timer 1 uses a divide-by-12 of the system clock frequency
1: Timer 1 uses a divide-by-4 of the system clock frequency
Division selection of the system clock that drives Timer 0
0: Timer 0 uses a divide-by-12 of the system clock frequency
1: Timer 0 uses a divide-by-4 of the system clock frequency
Reserved
3
T0M
--
R/W
R/W
2:0
Table 5-76 CKCON register
5.9.2.1. Timer 0: Mode 0 (13-Bit Timer/Counter)
In this mode, Timer 0 register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, Timer 0 interrupt flag
TF0 is set. The counted input is enabled to the Timer 0 when
TR0(TCON[4]) = 1 and either GATE0(TMOD[3]) = 0 or GATE0
input pin(P36)= 1. (Setting GATE0(TMOD[3]) = 1 allows the
Timer 0 to be controlled by external input GATE0(P36), to facilitate
pulse width measurements). The 13-bit register consists of all 8
bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0
are indeterminate and should be ignored. Figure 5-11 shows the
block diagram of Timer 0 for Mode 0.
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CKCON(0x8E)
TH0(0x8C)
TL0(0x8A)
SYSCLK/12
SYSCLK/4
clock
division
selection
timer
counter
switch
Interrupt request
13-bit upper counter
T0(P34)
TMOD(0x89)
TCON(0x88)
GATE0(P36)
Figure 5-11 The block diagram of Timer 0 for Mode 0
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5.9.2.2. Timer 0: Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0, except that the timer register is
running with all 16 bits. The block diagram of Mode 1 is shown in
Figure 5-12.
CKCON(0x8E)
TH0(0x8C)
TL0(0x8A)
SYSCLK/12
clock
division
SYSCLK/4
selection
Interrupt request
timer
counter
16-bit upper counter
switch
T0(P34)
TMOD(0x89)
TCON(0x88)
GATE0(P36)
Figure 5-12 The block diagram of Timer 0 for Mode 1
5.9.2.3. Timer 0: Mode 2 (8-bit Timer/Counter with Auto-reload Function)
Mode 2 configures the timer register as an 8-bit counter (TL0) with
automatic reloads, as shown in Figure 5-13. Overflow from TL0
not only sets TF0, but also reloads TL0 with the contents of TH0,
which is loaded by software. The reload leaves TH0 unchanged.
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CKCON(0x8E)
TL0(0x8A)
SYSCLK/12
SYSCLK/4
clock
division
selection
timer
counter
switch
Interrupt request
8-bit upper counter
T0(P34)
TMOD(0x89)
TCON(0x88)
Set
TH0(0x8C)
GATE0(P36)
Figure 5-13 The block diagram of Timer 0 for Mode 2
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5.9.2.4. Timer 0: Mode 3 (Two 8-Bit Timers/Counters)
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate
counters. The block diagram for Mode 3 on Timer 0 is shown in
Figure 5-14. TL0 uses the Timer 0 control bits: CT0, GATE0, TR0,
and TF0. TH0 is locked into a timer function and uses the TR1
and TF1 flags from Timer 1 and controls Timer 1 interrupt. Mode
3 is provided for applications requiring an extra 8-bit timer/counter.
When Timer 0 is in Mode 3, Timer 1 can be turned off by switching
it into its own Mode 3, or can still be used by the serial channel as
a baud rate generator, or in any application where interrupt from
Timer 1 is not required.
TH0(0x8C)
Interrupt request
8-bit upper counter
CKCON(0x8E)
TL0(0x8A)
TCON(0x88)
SYSCLK/12
clock
division
SYSCLK/4
selection
timer
counter
switch
8-bit upper counter
T0(P34)
Interrupt request
TMOD(0x89)
GATE0(P36)
Figure 5-14 The block diagram of Timer 0 for Mode 3
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5.9.2.5. Timer 1: Mode 0 (13-Bit Timer/Counter)
In this mode, the Timer 1 register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, Timer 1 interrupt flag
TF1 is set. The counted input is enabled to the Timer1 when
TR1(TCON[6]) = 1 and either GATE1(TMOD[7]) = 0 or GATE1
input pin(P37)= 1. (Setting GATE1(TMOD[7]) = 1 allows the
Timer1 to be controlled by external input GATE1(P37), to facilitate
pulse width measurements). The 13-bit register consists of all 8
bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1
are indeterminate and should be ignored. Figure 5-15 shows the
block diagram of Timer1 for Mode 0.
CKCON(0x8E)
TH1(0x8D)
TL1(0x8B)
SYSCLK/12
clock
division
SYSCLK/4
selection
timer
Interrupt request
counter
switch
13-bit upper counter
T1(P35)
TMOD(0x89)
TCON(0x88)
GATE1(P37)
Figure 5-15 The block diagram of Timer 1 for Mode 0
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5.9.2.6. Timer 1: Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0, except that the timer register is
running with all 16 bits. The block diagram of Mode 1 is shown in
Figure 5-16.
CKCON(0x8E)
TH1(0x8D)
TL1(0x8B)
SYSCLK/12
clock
division
SYSCLK/4
selection
timer
counter
switch
Interrupt request
16-bit upper counter
T1(P35)
TMOD(0x89)
TCON(0x88)
GATE1(P37)
Figure 5-16 The block diagram of Timer 1 for Mode 1
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5.9.2.7. Timer 1: Mode 2 (8-Bit Timer/Counter with Auto-reload Function)
Mode 2 configures the timer register as an 8-bit counter (TL1)
with automatic reloads, as shown in Figure 5-17. Overflow
from TL1 not only sets TF1, but also reloads TL1 with the
contents of TH1, which is loaded by software. The reload
leaves TH1 unchanged.
CKCON(0x8E)
TL1(0x8B)
SYSCLK/12
clock
division
SYSCLK/4
selection
timer
Interrupt request
counter
switch
8-bit upper counter
T1(P35)
TMOD(0x89)
TCON(0x88)
Set
TH1(0x8D)
GATE1(P37)
Figure 5-17 The block diagram of Timer 1 for Mode 2
5.9.2.8. Timer 1: Mode 3
Timer 1 in Mode 3 is has no timer function. The effect is the same as setting TR1=0.
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5.9.3. Timer 2
The Timer 2, which is a 16-bit-wide register, can operate as timer.
The additional Compare/Capture/Reload feature is one of the
most powerful peripheral units of the core. It can be used for all
kinds of digital signal generation and event capturing like pulse
generation, pulse width modulation, pulse width measuring etc.
Figure 5-18 shows the block diagram of compare/capture function
for Timer 2.
T2EX(P11)
Sync.
T2CON(0xC8)
T2IF(0xC9)
Interrupt
request
Reload
clock
division
16-bit upper counter
TL2
TH2
SYSCON1(0xAF)
16-bit
16-bit
16-bit
16-bit
comparator
comparator
comparator
comparator
Compare0/INT3
Compare
Capture
Compare1/INT4
Compare2/INT5
SYSCLK/12
SYSCLK/1
clock
sw
Compare3/INT6
SYSCLK/24
SYSCLK/2
clock
sw
CCL3/CCH3
CCL2/CCH2
CCL1/CCH1
CRCL/CRCH
Figure 5-18 The block diagram of compare/capture function for Timer 2
5.9.3.1. Timer mode
In timer function, the count rate is derived from the oscillator
frequency. A 2:1 pre-scaler offers the possibility of selecting a
count rate of 1/12(1/1) or 1/24(1/2) of an oscillator frequency.
Thus, the 16-bit timer register (consisted of TH2 and TL2) is either
incremented in every 1/12(1/1) clock periods or in every 1/24(1/2)
clock periods. The pre-scaler is selected by bit T2PS of T2CON
and the clock switch is selected by bit T2CLK_SW of SYSCON1.
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5.9.3.2. Reload of Timer 2
The reload mode for Timer 2 is selected by T2R0 and T2R1 bits of
T2CON. In mode 0, when Timer2 rolls over from all 1’s to all 0’s,
not only TF2 is set but also Timer 2 registers is loaded with the
16-bit value from CRC register. Required CRC value can be
preset by software. The reload occurs in the same clock cycle in
which TF2 is set, thus overwriting the count value 0x0000. In
mode 1, a 16-bit reload from the CRC register is caused by a
negative transition at the corresponding T2EX input pin(P11). In
addition, this transition sets EXF2 flag, if bit EXEN2 is set.
Setting EXF2 will generate an interrupt, if Timer 2 interrupt is
enabled.
T2IF(0xC9)
16 - bit timer
TH2(0xCD)
TL2(0xCC)
T2CON(0xC8)
mode1
mode0
T2EX(P11)
Timer 2
interrupt
request
CRCH(0xCB)
CRCL(0xCA)
Figure 5-19 The block diagram of reload function for Timer 2
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5.9.3.3. Compare functions
The 16-bit value stored in a compare/capture register is compared
with the contents of the timer register. If the count value in the
timer register matches the stored value, an appropriate output
signal is generated at a corresponding port pin, and an interrupt is
function register T2CON. In both compare modes, the new value
arrives at certain pin of P1[3:1] within the same clock cycle in
which the internal compare signal is activated.
requested.
The contents of
a
compare register can be
Compare mode 0
considered as time stamp at which a dedicated output reacts in a
predefined way (either with a positive or negative transition).
Variation of this time stamp somehow changes the wave of a
rectangular output signal at a port pin. This may - as a variation
of the duty cycle of a periodic signal - be used for pulse width
modulation as well as for a continually controlled generation of any
In mode 0, upon matching the timer and compare register
contents, an output signal changes from low to high. It goes back
to a low level on timer overflow. As long as compare mode 0 is
enabled, the appropriate output pin is controlled by the timer
circuit exclusively. It means that instructions writing to the P1 pin
will have no effect. Figure 5-20 shows a functional diagram of a
port register in compare mode 0. The port register is directly
controlled by the two signals: timer overflow and compare.
kind of square waveforms.
Two compare modes are
implemented to cover a wide range of possible applications. The
compare modes 0 and 1 are selected by bit T2CM in special
Only for CRC
Compare Register CCx
Interrupt
EINTx
Set Register
16-bit comparator
Reset Register
Q
Q
Q
P13
P12
P11
16 - bit timer2
TH2(0xCD)
TL2(0xCC)
T2IF(0xC9)
T2CON(0xC8)
Interrupt
Figure 5-20 The block diagram of compare mode 0 for Timer 2
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Compare mode 1
In compare mode 1, the software adaptively determines the
transition of the output signal. It is commonly used when output
signals are not related to a constant signal period. In compare
mode 1, both transitions of a signal can be controlled. If mode 1
is enabled, and the software writes to an appropriate output
register of P1, a new value will not appear at the output pin until
the next compare match occurs. User can select this way
whether the output signal should make a new transition or should
keep its old value, until the Timer 2 counter matches the stored
compare value. Figure 5-21 shows a functional diagram of Timer
2 in compare mode 1.
Only for CRC
EINTx
Interrupt
Compare Register CCx
Shadow Register
16-bit comparator
Port Register Circuit
Output Register
P12
P13
P11
16 - bit timer2
TH2(0xCD)
TL2(0xCC)
T2IF(0xC9)
T2CON(0xC8)
Interrupt
Figure 5-21 The block diagram of compare mode 1 for Timer 2
5.9.3.4. Capture functions
Each of compare/capture registers from CC1, CC2 and CC3 to
CRC register can be used to latch the current 16-bit value of the
Timer 2 registers TL2 and TH2. Two different modes are
provided for this function.
Capture mode 1
In mode 1, a capture will occur upon writing to the low order byte
of the dedicated 16-bit capture register. This mode is provided to
allow software reading of Timer 2 contents on-the fly. The
capture occurs in response to a write instruction to the low order
byte of a capture register. The write-to-register signal (e.g.
write-to-CRCL) is used to initiate a capture. The value written to
the dedicated capture register is irrelevant for this function. The
Timer 2 contents will be latched into the appropriate capture
register in the cycle following the write instruction. In this mode,
no interrupt request will be generated.
Capture mode 0
In mode 0, an external event latches Timer 2 contents to a
dedicated capture register. The external event causing a capture
is
z for the CC registers 1 to 3: a positive transition on pins
CAPTURE1 to CAPTURE3
z for the CRC register: a positive or negative transition on the
CAPTURE0 pin, depending on the bit I3FR of T2CON. If
the I3FR flag is cleared, a capture occurs in response to a
negative transition; otherwise, a capture occurs in response
to a positive transition on compare0 pin.
Figure 5-22 and Figure 5-23 show functional diagrams of the
Timer 2 capture function.
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T2IF(0xC9)
Interrupt request
16 - bit timer
TH2(0xCD)
TL2(0xCC)
T2CON(0xC8)
Input clock
Overflow
mode0
mode1
0
1
CAPTURE0
(P12)
Capture
CRCH(0xCB)
CRCL(0xCA)
Write to CRCL
Figure 5-22 The block diagram of Timer 2 capture mode 0 for CRCL and CRCH
T2IF(0xC9)
Interrupt request
16 - bit timer
TH2(0xCD)
TL2(0xCC)
Input clock
Overflow
X=1,2,3
CAPTUREx
mode0
mode1
(CAPTURE1=P13)
(CAPTURE2=P14)
(CAPTURE3=P15)
Capture
CCHx(0xC3,0xC5,0xC7)
CCLx(0xC2,0xC4,0xC6)
Write to CCLx
Figure 5-23 The block diagram of Timer 2 capture mode 0 for CCLx and CCHx (x=1,2,3)
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5.9.3.5. Timer 2 Related Registers
SYSCON1
Address: 0xAF
SYSTEM Control1 Register
Bit
7
6
HV_SEL
0
5
SPI1_EN
0
4
SPI0_EN
0
3
--
0
2
--
0
1
--
1
0
--
1
Function
Default
Key Code
T2CLK_SW
0
FF,00
Bit
Function
Type
Description
Condition
7
T2CLK_SW
R/W
Timer 2 timer function input frequency switch
0: SYSCLK/12 (T2PS=0) or SYSCLK/24 (T2PS=1)
1: SYSCLK/1 (T2PS=0) or SYSCLK/2 (T2PS=1)
0: P07/P40/P41 are used as hall-sensors
1: P07/P05/P41 are used as hall-sensors
SPI signals forward to P3[6:4] enable
P3[4]: SPI_CLK
6
5
HV_SEL
SPI1_EN
R/W
R/W
P3[5]: SPI_TX
P3[6]: SPI_RX
4
SPI0_EN
R/W
R/W
SPI signals forward to P0[7:4] enable
P0[4]: SPI_CSB
P0[5]: SPI_CLK
P0[6]: SPI_TX
P0[7]: SPI_RX
3:0
--
Reserved
Table 5-77 SYSCON1 register
T2CON
Bit
Address: 0xC8
Timer2 Configuration Register
7
T2PS
0
6
I3FR
0
5
--
0
4
T2R1
0
3
T2R0
0
2
T2CM
0
1
0
T2I0
0
Function
Default
T2I1
0
Bit
Function
Type
Description
Condition
7
T2PS
R/W
Prescaler select bit
0: SYSCLK/12 or SYSCLK/1
1: SYSCLK/24 or SYSCLK/2
6
I3FR
R/W
Interrupt edge activity selection bit of compare 0 function in combination with
capture 0 function and register CRC
Compare 0:
0: a negative transition on compare0 output can generate interrupt
1: a positive transition on compare0 output can generate interrupt
Capture 0:
0: capture to CRC register occurs on a positive transition of CAPTURE0 pin
1: capture to CRC register occurs on a positive transition of CAPTURE0 pin
Reserved
5
--
R/W
R/W
4:3
T2R[1:0]
Timer 2 reload mode selection bit
T2R1
T2R0
Function
0
1
X
0
Reload disabled
Mode 0: auto-reload upon Timer 2 overflow
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Bit
Function
Type
Description
Condition
1
1
Mode 1: reload upon falling edge at pin T2EX
2
T2CM
R/W
Compare mode select bit for registers CRC, CC1, CC2, and CC3
0: compare mode 0 is selected
1: compare mode 1 is selected
1:0
T2I[1:0]
R/W
Timer 2 input selection bit
T2l1
0
T2l0
0
Function
No input selected, Timer 2 is stopped
Timer function input frequency
SYSCLK/12 or SYSCLK/1(T2PS=0)
SYSCLK/24 or SYSCLK/2(T2PS=1)
No input selected, Timer 2 is stopped
No input selected, Timer 2 is stopped
0
1
1
1
0
1
Table 5-78 T2CON register
CCEN
Bit
Address: 0xCE
Compare/Capture Enable Register
7
CMH3
6
CML3
0
5
CMH2
0
4
CML2
0
3
CMH1
0
2
CML1
0
1
CMH0
0
0
CML0
0
Function
Default
0
Bit
Function
Type
Description
Condition
7:6
CM3[1:0]
R/W
Compare/capture mode for CC3 register
CMH3
CML3
Function
0
0
1
1
0
1
0
1
Compare/capture disabled
Capture on rising edge of CAPTURE3 pin
Compare enabled
Capture on write operation into register CCL3
5:4
3:2
1:0
CM2[1:0]
CM1[1:0]
CM0[1:0]
R/W
R/W
R/W
Compare/capture mode for CC2 register
CMH2
CML2
Function
0
0
1
1
0
1
0
1
Compare/capture disabled
Capture on rising edge of CAPTURE2 pin
Compare enabled
Capture on write operation into register CCL2
Compare/capture mode for CC1 register
CMH1
CML1
Function
0
0
1
1
0
1
0
1
Compare/capture disabled
Capture on rising edge of CAPTURE1 pin
Compare enabled
Capture on write operation into register CCL1
Compare/capture mode for CRC register
CMH2
CML2
Function
0
0
1
1
0
1
0
1
Compare/capture disabled
Capture on falling/rising edge of CAPTURE0 pin
Compare enabled
Capture on write operation into register CRCL
Table 5-79 CCEN register
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T2IF
Address: 0xC9
Timer 2 Interrupt Flag Register
Bit
7
--
0
6
--
0
5
--
0
4
--
0
3
--
0
2
EXEN2
0
1
EXF2
0
0
TF2
0
Function
Default
Bit
7:3
2
Function
--
Type
R/W
R/W
Description
Condition
Reserved
EXEN2
Timer 2 external reload interrupt enable
0: external reload interrupt is disabled
1: external reload interrupt is enabled
Timer 2 external reload flag
Cleared by the software
1
0
EXF2
TF2
R/W
R/W
Timer 2 overflow flag
Cleared by the software
Table 5-80 T2IF register
CCH1
Bit
Address: 0xC3
Timer 2 CC1 Register - high byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC1[15:8]
0
0
0
Bit
Function
Type
R/W
Description
Condition
7:0
CC1[15:8]
Timer2 compare/capture 1 - high byte
Table 5-81 The CCH1 register
CCL1
Bit
Address: 0xC2
Timer 2 CC1 Register - low byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC1[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CC1[7:0]
R/W
Timer2 compare/capture 1 - low byte
Table 5-82 The CCL1 register
CCH2
Bit
Address: 0xC5
Timer 2 CC2 Register - high byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC2[15:8]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CC2[15:8]
R/W
Timer2 compare/capture 2 - high byte
Table 5-83 The CCH2 register
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CCL2
Bit
Address: 0xC4
Timer 2 CC2 Register - low byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC2[7:0]
0
0
0
Bit
Function
Type
R/W
Description
Condition
7:0
CC2[7:0]
Timer2 compare/capture 2 - low byte
Table 5-84 The CCL2 register
CCH3
Bit
Address: 0xC7
Timer 2 CC3 Register - high byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC3[15:8]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CC3[15:8]
R/W
Timer2 compare/capture 3 - high byte
Table 5-85 The CCH3 register
CCL3
Bit
Address: 0xC6
Timer 2 CC3 Register - low byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC3[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CC3[7:0]
R/W
Timer2 compare/capture 3 - low byte
Table 5-86 The CCL3 register
CRCH
Bit
Address: 0xCB
CRC Register - high byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CRC[15:8]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CRC[15:8]
R/W
CRC - high byte
Table 5-87 The CRCH register
CRCL
Bit
Address: 0xCA
CRC Register - low byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CRC[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CRC[7:0]
R/W
CRC - low byte
Table 5-88 The CRCL register
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TH2
Address: 0xCD
Timer 2 High Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TH2[7:0]
0
0
0
Bit
Function
Type
R/W
Description
Condition
7:0
TH2[7:0]
Timer 2 Load value – high byte
Table 5-89 TH2 register
TL2
Address: 0xCC
Timer 2 Low Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TL2[7:0]
0
0
0
Bit
Function
TL2[7:0]
Type
Description
Condition
7:0
R/W
Timer 2 Load value – low byte
Table 5-90 TL2 register
5.10. UART0
UART0 has the same functionality as a standard 8051 UART.
The serial port is full duplex, meaning it can transmit and receive
addressed slave will clear its SM02 bit and prepare to receive the
data bytes that will be coming. The slaves that were not being
addressed leave their SM02 set and ignoring the incoming data.
concurrently.
It is receive double-buffered, meaning it can
commence reception of a second byte before a previously
received byte has been read from the receive register. Writing to
SBUF0 loads the transmit register, and reading SBUF0 reads a
physically separate receive register. The serial port can operate
in 4 modes: one synchronous and three asynchronous modes.
5.10.1. UART0: Mode 0 (Synchronous Shift register)
This mode is used as shift register IO control, and not for real
communication application. The baud rate is fixed at 1/12 of the
system clock frequency and TXD0(P31) output is a shift clock.
Eight bits are transmitted with LSB first. Reception is initialized
by setting the flags in SCON0 as follows: RI0 =0 and REN0 =1.
Figure 5-24 shows the timing diagram of UART0 transmission
mode 0.
Mode
2 and 3 have a special feature for multiprocessor
communications. This feature is enabled by setting SM02 bit in
SCON0 register. The master processor first sends out an
address byte, which identifies the target slave. An address byte
differs from a data byte in that the 9th bit is 1 in an address byte
and 0 in a data byte. With SM02 = 1, no slave will be interrupted
by a data byte. An address byte will interrupt all slaves. The
TXD0(P31)
RXD0(P30)
D0
D1
D2
D3
D4
D5
D6
D7
Figure 5-24 The timing diagram of UART0 transmission mode 0
5.10.2. UART0: Mode 1 (8-Bit UART, Variable Baud Rate, Timer1 Clock Source)
In mode 1, TXD0 serves as serial output. 10 bits are transmitted:
a start bit (always 0), 8 data bits (LSB first), and a stop bit (always
1). On receive, a start bit synchronizes the reception, 8 data bits
are available by reading SBUF0 and stop bit sets the flag RB08 in
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the SFR SCON0. The baud rate is variable and depends from
Timer 1 mode. Figure 5-25 shows the timing diagram of UART0
transmission mode 1.
TX_CLK
TXD0(P31)
START
D0
D1
D2
D3
D4
D5
D6
D7
STOP
Figure 5-25 The timing diagram of UART0 transmission mode 1
5.10.3. UART0: Mode 2 (9-Bit UART, Fixed Baud Rate)
This mode is similar to Mode 1 with two differences. The baud
rate is fixed at 1/32 or 1/64 of system clock frequency, and 11 bits
are transmitted or received: a start bit (0), 8 data bits (LSB first), a
programmable 9th bit, and a stop bit (1). The 9th bit can be used
to control the parity of the UART0 interface: at transmission, bit
TB08 in SCON0 is output as the 9th bit, and at receive, the 9th bit
affects RB08 in SCON0. Figure 5-26 shows the timing diagram
of UART0 transmission mode 2.
TX_CLK
TB8 STOP
TXD0(P31)
START
D0
D1
D2
D3
D4
D5
D6
D7
Figure 5-26 The timing diagram of UART0 transmission mode 2
5.10.4. UART0: Mode 3 (9-Bit UART, Variable Baud Rate, Timer1 Clock Source)
The only difference between Mode 2 and Mode 3 is that the baud
rate is a variable in Mode 3. When REN0 =1 data receiving is
enabled. The baud rate is variable and depends from Timer 1
mode.
TX_CLK
TB8
STOP
D3
TXD0(P31)
START
D0
D1
D2
D4
D5
D6
D7
Figure 5-27 The timing diagram of UART0 transmission mode 3
5.10.5. UART0 Related Registers
The UART0 related registers are: SBUF0(0x99), SCON0(0x98),
PCON(0x87), IE(0xA8) and IP(0xB8). The UART0 data buffer
(SBUF0) consists of two separate registers: transmit and receive
registers. A data written into SBUF0 sets this data in UART0
output register and starts a transmission. A data read from
SBUF0, reads data from the UART0 receive register.
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SBUF0
Bit
Address: 0x99
UART0 Buffer Register
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
SBUF0[7:0]
0
0
0
Bit
Function
Type
R/W
Description
Condition
2:0
SBUF0[7:0]
UART0 buffer
Table 5-91 SBUF0 register
SCON0
Bit
Address: 0x98
UART0 Configuration Register
7
SM00
0
6
SM01
0
5
SM02
0
4
REN0
0
3
TB08
0
2
RB08
0
1
0
RI0
0
Function
Default
TI0
0
Bit
7:6
5
Function
SM0[1:0]
SM02
Type
R/W
R/W
R/W
R/W
R/W
Description
Condition
Mode and baud rate setting which described as below table
Enables a multiprocessor communication feature
Enable serial reception.
4
REN0
3
TB08
The 9th transmitted data bit in Modes 2 and Mode 3
2
RB08
In Mode 0, this bit is not used
In Mode 1, if SM02 is 0, RB08 is the stop bit.
In Mode 2 and Mode 3, it is the 9th data bit received
UART0 transmitter interrupt flag
1
0
TI0
RI0
R/W
R/W
UART0 receiver interrupt flag
Table 5-92 SCON0 register
variable: in Mode1 and Mode 3
Timer
SM00 SM01 Mode Function
Baud rate
Baud rate
0
0
1
0
1
0
0
1
2
Shift register SYSCLK/12
Timer 1 overflow rate
Timer 1 overflow rate
T1ov/32 (SMOD0=0)
T1ov/16 (SMOD0=1)
8-bit UART
9-bit UART
variable
SYSCLK/64(SMOD0=0)
SYSCLK/32(SMOD0=1)
variable
1
1
3
9-bit UART
PCON
Bit
Address: 0x87
Power Configuration Register
7
6
--
0
5
4
PWE
0
3
2
--
0
1
STOP
0
0
Function
Default
SMOD0
0
CPU_IDLE
0
STOP_RST_EN
0
--
0
Bit
7
Function
SMOD0
--
Type
Description
Condition
R/W
R/W
R/W
UART0 double baud rate bit when clocked by Timer1
Reserved
6
5
CPU_IDLE
IDLE mode enable bit
0: IDLE mode disabled;
1: IDLE mode entered
4
PWE
R/W
Program Write Enable (PWE)
0: Disable Flash write activity during MOVX instruction
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Bit
Function
Type
Description
Condition
1: Enable Flash write activity during MOVX instruction
Wakeup state selection bit
0: Next instruction state after wakeup
1: Reset state afer wakeup
Reserved
3
STOP_RST_EN
R/W
2
1
--
R/W
R/W
STOP
STOP mode enable bit
0: Disabled
1: Enabled
0
--
R/W
Reserved
Table 5-93 PCON register
IE
Address: 0xA8
Interrupt Enable Register
Bit
7
EA
0
6
--
0
5
ET2
0
4
ES0
0
3
ET1
0
2
EX1
0
1
ET0
0
0
EX0
0
Function
Default
Bit
7
Function
EA
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Condition
Enable global interrupts
Reserved
6
--
5
ET2
ES0
ET1
EX1
ET0
EX0
Enable Timer 2 interrupt
Enable UART0 interrupt
Enable Timer 1 interrupt
Enable INT1 interrupt
Enable Timer 0 interrupt
Enable INT0 interrupt
4
3
2
1
0
Table 5-94 IE register
IP
Address: 0xB8
Interrupt Priority Register
Bit
7
-
6
PS1
0
5
4
PS0
0
3
PT1
0
2
PX1
0
1
PT0
0
0
PX0
0
Function
Default
PT2
0
0
Bit
7:6
5
Function
--
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Condition
Reserved
PT2
PS0
PT1
PX1
PT0
PX0
Timer 2 priority level control (1: high level)
UART0 priority level control (1: high level)
Timer 1 priority level control (1: high level)
INT1 priority level control (1: high level)
Timer 0 priority level control (1: high level)
INT0 priority level control (1: high level)
Table 5-95 IP register
4
3
2
1
0
5.11. SPI
A
Serial Peripheral Interface (SPI) controller is built in
devices and components. The SPI controller includes four
master modes. There are four control signals on SPI including
GPM8F3132A/3116A/3108A to facilitate communicating with other
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SPI_CSB, SPI_CLK, SPI_TX, and SPI_RX, these four signals are
shared with P0[7:4] or {PXX, P3[6:4]} (PXX is used for SPICSN
and can be a random pin as long as it is not utilized for any other
function) based on SPI0 or SPI1 is chosen. The control share I/O
is set by SYSCON1[5:4]. While SPI module is enabled by
corresponding control bit, these four pins cannot be GPIOs. In
other words, any setting on corresponding GPIO control register
will have no effect. The SPI provides following features.
block. There are two control bits to control the clock phase and
polarity. The transmission starts immediately after SPI_START is
set(SPICON[0]=1,0xFC). The SPI shifts the 8-bit data from MSB
to LSB through the SPI_TX pin during
8 SCK cycles.
Programmer can read SPI data from SPIRXD control register by
setting SPI_RD =1. The following four diagrams depict the timing
scheme on SPI master mode for different operation types (polarity
control bit equals “1” or “0”, phase control bit equals “1” or “0”).
The related registers are SYSCON1 register, SPICON register,
SPITXD register and SPIRXD registers which are tabled as Table
5-96 to Table 5-99.
Programmable phase and polarity of master clock
Programmable master SPI_CLK clock frequency
In master mode, the shifting clock (SPI_CLK) is generated by SPI
SPI_CSB
SPI_CLK
LSB
LSB
SPI_TX
SPI_RX
MSB
MSB
8 bit
Figure 5-28 Master Mode, POLARITY=0, PHASE=0
SPI_CSB
SPI_CLK
SPI_TX
LSB
LSB
MSB
MSB
SPI_RX
8 bit
Figure 5-29 Master Mode, POLARITY=0, PHASE=1
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SPI_CSB
SPI_CLK
LSB
LSB
SPI_TX
SPI_RX
MSB
MSB
8 bit
Figure 5-30 Master Mode, POLARITY=1, PHASE=0
SPI_CSB
SPI_CLK
LSB
LSB
SPI_TX
SPI_RX
MSB
MSB
8 bit
Figure 5-31 Master Mode, POLARITY=1, PHASE=1
SYSCON1
Bit
Address: 0xAF
SYSTEM Control1 Register
7
6
HV_SEL
0
5
SPI1_EN
0
4
SPI0_EN
0
3
--
0
2
--
0
1
--
1
0
--
1
Function
Default
Key Code
T2CLK_SW
0
FF,00
Bit
Function
Type
Description
Condition
7
T2CLK_SW
R/W
Timer 2 timer function input frequency switch
0: SYSCLK/12 (T2PS=0) or SYSCLK/24 (T2PS=1)
1: SYSCLK/1 (T2PS=0) or SYSCLK/2 (T2PS=1)
0: P07/P40/P41 are used as hall-sensors
1: P07/P05/P41 are used as hall-sensors
SPI signals forward to P3[6:4] enable
P3[4]: SPI_CLK
6
5
HV_SEL
SPI1_EN
R/W
R/W
P3[5]: SPI_TX
P3[6]: SPI_RX
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Bit
Function
Type
Description
Condition
4
SPI0_EN
R/W
SPI signals forward to P0[7:4] enable
P0[4]: SPI_CSB
P0[5]: SPI_CLK
P0[6]: SPI_TX
P0[7]: SPI_RX
3:0
--
R/W
Reserved
Table 5-96 SYSCON1 register
SPICON
Bit
Address: 0xFC
SPI Control Register
7
6
5
4
3
2
--
0
1
SPI_RD
0
0
Function
Default
POLARITY
0
PHASE
0
SPI_CLK_SEL[1:0]
CSB_KEEP
0
SPI_START
0
0
0
Bit
Function
Type Description
Condition
7
POLARITY
R/W SPI CLK initial state
0: low state;
R/W SPI CLK type control
0: rising sample; 1: falling sample
1: high state
6
PHASE
5:4
SPI_CLK_SEL[1:0]
R/W SPI Clock output selection:
00: SYSCLK/2
01: SYSCLK/4
10: SYSCLK/8
11: SYSCLK/16
3
2
1
0
CSB_KEEP
--
R/W SPI CSB keep low control, high active
R/W Reserved
SPI_RD
SPI_START
R/W SPI read command
R/W SPI enable(W)/SPI busy flag(R)
Table 5-97 SPICON register
SPITXD
Bit
Address: 0xFD
SPI Output Buffer Register
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
SPITXD[7:0]
0
0
0
Bit
Function
Type
R/W
Description
SPI output buffer
Condition
7:0
SPITXD
Table 5-98 SPITXD register
SPIRXD
Bit
Address: 0xFE
SPI Input Buffer Register
7
0
6
0
5
4
0
3
SPIRXD[7:0]
0
2
1
0
0
0
Function
Default
0
0
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Bit
Function
Type
Description
Condition
7:0
SPIRXD
R/W
SPI input buffer
Table 5-99 SPIRXD register
5.12. ADC
5.12.1. ADC Control
There
is
one
Analog-to-Digital-Converter
(ADC)
in
Eight channels of 12-bit SAR ADC are built in
GPM8F3132A/3116A/3108A.
It provides general purpose
GPM8F3132A/3116A/3108A.
They
are
defined
as
usages such as voice record feature and any other analog
functions.
general-purpose line input P00, P01 … P07. These eight
channels are very suitable for system voltage detection and other
general-purpose usages. In addition, there is an AD_BITSEL
control pin which can choose 8-bit ADC or 12-bit ADC to be used.
Figure 5-32 and Figure 5-33 show the related timing and block
diagrams.
8 Channels, 12-bit resolution (11-bit no-missing code) ADC
Supports programming sample hold and ADC clock function
ADCLK=SYSCLK/4 ~SYSCLK/32=1T (SYSCON2[7]=1)
ADCLK=SYSCLK/8 ~SYSCLK/64=1T
ADEN
ADCLK
SHCLK
READY
2/4/8/16T
> 10T(8 bit mode)
14T(10 bit mode)
Figure 5-32 The timing diagram of ADC control
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ADAEN(0xF3)
START
VCC VSS VREG
P00
P01
P02
P03
ADCON(0xF1)
P04
P05
READY
Interrupt request
Interrupt request
P06
P07
ADCFG(0xF2)
ADC
{ADLB,4'h0}<ADO
<{ADUB,4'h0}
0
1
ADO<{ADLB,4'h0} or
ADO>{ADUB,4'h0}
ADC output
data[11:0]
8 bit mode
0
1
12 bit mode
SYSCON2(0xA7)
Figure 5-33 The block diagram of ADC
ADC Related Register
ADCON
Address: 0xF1
ADC Control Register
Bit
7
6
READYF
0
5
4
WINIE
0
3
ADIE
0
2
--
0
1
PSIDLE
0
0
START
0
Function
Default
WINF
0
WIN_SEL
0
Bit
Function
Type
Description
Condition
7
6
5
WINF
R/W
R/W
R/W
Window detect flag, cleared by 1.
READYF
WIN_SEL
ADC transfer ready flag, cleared by 1.
ADC output window selection
0: ADC output is between ADLB and ADUB
1: ADC output isn’t between ADLB and ADUB
ADC window interrupt enable
4
3
2
1
0
WINIE
ADIE
R/W
R/W
R/W
R/W
R/W
ADC transfer ready interrupt enable
Reserved
--
PSIDLE
START
IDLE mode enable bit (ADC start transfer with suspending CPU clock)
ADC start transfer control
Table 5-100 ADCON register
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ADCFG
Bit
Address: 0xF2
ADC Configuration Register
7
6
0
5
4
0
3
2
1
0
0
0
Function
Default
AD_BITSEL
0
CH_SEL[2:0]
0
SHCLK[1:0]
ADCLK[1:0]
0
0
Bit
Function
Type
Description
Condition
7
AD_BITSEL
CH_SEL[2:0]
R/W
R/W
0: 8-bit ADC;
1: 12-bit ADC
6:4
ADC channel selection
0: P00 is selected
1: P01 is selected
2: P02 is selected
3: P03 is selected
4: P04 is selected
5: P05 is selected
6: P06 is selected
7: P07 is selected
3:2
1:0
SHCLK[1:0]
R/W
R/W
ADC sample and hold period
0: 2T of ADCLK
1: 4T of ADCLK
2: 8T of ADCLK
3: 16T of ADCLK
ADCLK
ADC clock selection
0: ADC conversion clock = 3.0625MHz (FOSC /8)
1: ADC conversion clock = 1.53MHz (FOSC /16)
2: ADC conversion clock = 765.625KHz (FOSC /32)
3: ADC conversion clock = 382.81KHz (FOSC /64)
Table 5-101 ADCFG register
ADAEN
Bit
Address: 0xF3
ADC Analog PAD Enable Register
7
6
5
P05_AEN
0
4
P04_AEN
0
3
P03_AEN
0
2
P02_AEN
0
1
0
P00_AEN
0
Function
Default
P07_AEN
P06_AEN
0
P01_AEN
0
0
Bit
Function
Type
Description
Condition
7
P07_AEN
R/W
P07 analog PAD enable control bit
0: P07 can be I/O PAD
1: P07 can be analog PAD
P06 analog PAD enable control bit
0: P06 can be I/O PAD
6
5
4
3
P06_AEN
P05_AEN
P04_AEN
P03_AEN
R/W
R/W
R/W
R/W
1: P06 can be analog PAD
P05 analog PAD enable control bit
0: P05 can be I/O PAD
1: P05 can be analog PAD
P04 analog PAD enable control bit
0: P04 can be I/O PAD
1: P04 can be analog PAD
P03 analog PAD enable control bit
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Bit
Function
Type
Description
Condition
0: P03 can be I/O PAD
1: P03 can be analog PAD
P02 analog PAD enable control bit
0: P02 can be I/O PAD
2
1
0
P02_AEN
P01_AEN
P00_AEN
R/W
R/W
R/W
1: P02 can be analog PAD
P01 analog PAD enable control bit
0: P01 can be I/O PAD
1: P01 can be analog PAD
P00 analog PAD enable control bit
0: P00 can be I/O PAD
1: P00 can be analog PAD
Table 5-102 ADAEN register
ADOL
Bit
Address: 0xF4
ADC Output Low Data Register
7
0
6
0
5
4
0
3
2
1
0
Function
Default
ADO[3:0]
0
Bit
7:4
3:0
Function
--
Type
R/W
R/W
Description
Condition
Reserved
ADO[3:0]
ADC output data[3:0]
Table 5-103 ADOL register
ADOH
Bit
Address: 0xF5
ADC Output High Data Register
7
6
5
4
3
2
1
0
Function
Default
ADO[11:4]
Bit
Function
Type
Description
ADC output data[11:4]
Table 5-104 ADOH register
Condition
7:0
ADO[11:4]
R/W
ADLB
Bit
Address: 0xF6
ADC Low Boundary register
7
0
6
5
4
0
3
2
1
0
0
Function
Default
ADLB[7:0]
0
0
0
0
0
Bit
Function
Type
Description
Condition
7:0
ADLB
R/W
ADC low boundary, compare to ADC[11:4]
Table 5-105 ADLB register
ADUB
Bit
Address: 0xF7
ADC UP Boundary register
7
0
6
5
4
0
3
ADUB[7:0]
0
2
1
0
0
Function
Default
0
0
0
0
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Bit
Function
Type
Description
Condition
7:0
ADUB
R/W
ADC up boundary, compare to ADC[11:4]
Table 5-106 ADUB register
SYSCON2
Bit
Address: 0xA7
SYSTEM control2 Register
7
6
--
0
5
4
3
2
1
0
Function
SCHMIT_DIS SCHMIT_DIS_ SCHMIT_DIS_ SCHMIT_DIS_
ADCLKX2
0
INT_filter_en GPIO_SSO
_P3
0
P2
0
P1
0
P0
0
Default
0
0
Key Code
FF,00
Bit
7
Function
ADCLKX2
--
Type
R/W
R/W
R/W
Description
Condition
ADCLK double enable bit
Reserved
6
5
INT_filter_en
INT0~INT2 pad filter enable bit
0: no filter
1: 2us
4
GPIO_SSO
R/W
GPIO SSO function enable bit
(Avoid GPIO change simultaneously)
3
2
1
0
SCHMIT_DIS_P3
SCHMIT_DIS_P2
SCHMIT_DIS_P1
SCHMIT_DIS_P0
R/W
R/W
R/W
R/W
P3 schmitt trigger function disable control bit
P2 schmitt trigger function disable control bit
P1 schmitt trigger function disable control bit
P0 schmitt trigger function disable control bit
Table 5-107 SYSCON2 register
5.13. Motor Control Unit
In GPM8F3132A/3116A/3108A, there is one motor control module
utilized to control motors by {P26, P25, P24, P23, P22, P21}.
P21 and P22 are used as PWM0 output and PWM1 output. P23
and P24 are used as PWM2 output and PWM3 output. P25 and
P26 are used as PWM4 output and PWM5 output. The related
registers are tabled as follows. MDPRDL register and MDPRDH
register control PWM frequency. CMP0, CMP1, and CMP2
registers control PWM duty for PWM0/1, PWM2/3 and PWM4/5
separately. In PWMCON1 register, PWMCON1[2] controls the
PWM mode which is edge-aligned or center-aligned. Figure 5-34
and Figure 5-35 show the waveforms of PWM output for these two
modes. PWMCON1[3] control synchronous function of PWM
output. If this bit is set to ‘1’, PWM0/2/4 are complementary to
PWM1/3/5, otherwise, PWM output is controlled by
PWMCON2[2:0] setting.
PWMCON1
Bit
Address: 0xB9
PWM Control Register 1
7
6
5
TMR5EN
0
4
--
0
3
2
TYPE
0
1
0
Function
Default
PWM_EN MATCH_EN
SYNC_RECT
0
PWMCK_SEL[1:0]
0
0
0
0
Bit
Function
Type Description
Condition
7
6
PWM_EN
R/W Enable PWM function
MATCH_EN
R/W Auto phase changing function enable bit
0: Disable auto phase changing function
1: Enable auto phase changing function
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Bit
Function
Type Description
Condition
5
4
3
TMR5EN
--
R/W Enable Timer 5
R/W Reserved
SYNC_RECT
R/W Enable synchronous function
0: PWM0~PWM5 output mode is decided by PWMCON2[2:0]
1: PWM0/2/4 are complementary to PWM1/3/5
R/W 0: edge-aligned (sawtooth wave PWM)
1: center aligned (triangular wave PWM)
R/W PWM clock divider
2
TYPE
1:0
PWMCK_SEL[1:0]
00: SYSCLK
01: SYSCLK/2
10: SYSCLK/4
11: SYSCLK/8
Table 5-108 PWMCON1 register
PWM_CNT
MDPRD
CMP0
0
PWM0
PWM1
Figure 5-34 PWM output if PWM_MODE is edge-aligned(sawtooth wave PWM), independent mode, polarity=0
PWM_CNT
MDPRD
CMP0
0
PWM0
PWM1
Figure 5-35 PWM output if PWM_MODE is center-aligned(triangular wave PWM), independent mode, polarity=0
MDPRDH
Bit
Address: 0xBB
MSB of PWM Cycle Register
7
--
0
6
--
0
5
--
0
4
--
0
3
2
1
0
0
0
Function
Default
MDPRD[11:8]
0
0
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MDPRDL
Bit
Address: 0xBA
LSB of PWM Cycle Register
7
0
6
0
5
4
0
3
2
1
0
0
1
Function
Default
MDPRD[7:0]
0
0
0
Note: MDPRD can not be 0xFFF
Table 5-109 MDPRD register
CMP0H
Address: 0xD2
MSB of PWM Duty Register 0
Bit
7
--
0
6
--
0
5
--
0
4
--
0
3
2
1
0
0
Function
Default
CMP0 compare level: CMP0[11:8]
0
0
0
CMP0L
Bit
Address: 0xD1
LSB of PWM Duty Register 0
7
1
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CMP0[7:0]
1
0
0
Table 5-110 CMP0 register
CMP1H
Bit
Address: 0xD4
MSB of PWM Duty Register 1
7
--
0
6
--
0
5
--
0
4
--
0
3
2
1
0
0
Function
Default
CMP1 compare level: CMP1[11:8]
0
0
0
CMP1L
Bit
Address: 0xD3
LSB of PWM Duty Register 1
7
1
6
0
5
4
1
3
2
1
0
0
0
Function
Default
CMP1[7:0]
1
0
0
Table 5-111 CMP1 register
CMP2H
Bit
Address: 0xD6
MSB of PWM Duty Register 2
7
--
0
6
--
0
5
--
0
4
--
0
3
2
1
0
0
Function
Default
CMP2 compare level: CMP2[11:8]
0
0
0
CMP2L
Bit
Address: 0xD5
LSB of PWM Duty Register 2
7
1
6
1
5
4
0
3
2
1
0
0
0
Function
Default
CMP2[7:0]
0
0
0
Table 5-112 CMP2 register
DTR controls if the dead-time function is enabled. If DTR
register is not equal to zero, dead-time function is enabled, and
the period of dead time is equal to PWMCK * DTR value.
Figure 5-36 and Figure 5-37 show the examples of sawtooth
wave PWM and triangular wave PWM if DTR is not “0”.
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DTR
Address: 0xBC
Dead-timer period Register
Bit
7
0
6
0
5
4
3
2
1
0
0
0
Function
Default
PWM Dead Time Period : DTR[7:0]
0
0
0
0
Table 5-113 DTR register
PWM_CNT
Dead time
Dead time
MDPRD
CMP0
0
PWM0
PWM1
PWM_CNT=0
PWM_CNT=CMP0
Figure 5-36 PWM output if dead-time function is enabled. Complementary mode and polarity =0(sawtooth wave PWM)
PWM_CNT
Dead time
Dead time
MDPRD
CMP0
0
PWM0
PWM1
PWM_CNT=CMP0
PWM_CNT=CMP0
Figure 5-37 PWM output if dead-time function is enabled. Complementary mode and polarity =0(triangular wave PWM)
In PWMCON2 register, PWMCON2[2:0] decides the PWM output
mode of PWM0/1, PWM2/3 and PWM4/5 respectively. If bit 0 is
set to ‘0’, independent mode is chosen for PWM0 and PWM1.
On the contrary, complementary mode is selected. Figure 5-38
and Figure 5-39 show the examples of PWM output of these two
modes. PWMCON2[5:3] control whether the PWM output is
output on {P26, P25, P24, P23, P22, P21}. PWMCON2[7] offers
a mode that ADC conversion can synchronize to PWM output.
There are four positions totally which user can choose where ADC
starts to work in the ADCPWM register. Figure 5-40 and Figure
5-41 show the diagrams of four positions when PWMCON2[7] = 1
for sawtooth wave PWM and triangular wave PWM. In addition,
there is a special function in position 2 that user can shift the
position
forward
a
period
which
equals
to
{ADC_SYNC_SHIFT[2:0], 3’b000} * SYSCLK.
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PWMCON2
Bit
Address: 0xD9
PWM Control Register 2
7
6
--
0
5
4
3
2
1
0
Function
Default
PWMSYNC_ADC
0
PWM45_EN PWM23_EN PWM01_EN PWM45_MODE PWM23_MODE PWM01_MODE
0
0
0
0
0
0
Bit
Function
Type
Description
Condition
7
6
5
PWMSYNC_ADC
--
R/W
R/W
R/W
Enable ADC conversion sync to PWM mode
Reserved
PWM45_EN
0: Disable PWM4/5 output
1: P25 and P26 are PWM4 and PWM5
0: Disable PWM3/2 output
4
3
2
PWM23_EN
PWM01_EN
R/W
R/W
R/W
1: P23 and P24 are PWM2 and PWM3
0: Disable PWM0/1 output
1: P21 and P22 are PWM0 and PWM1
PWM4/5 output mode
PWM45_MODE
0: PWM4 and PWM5 are in independent mode
1: PWM4 and PWM5 are in complementary mode
PWM2/3 output mode
1
0
PWM23_MODE
PWM01_MODE
R/W
R/W
0: PWM2 and PWM3 are in independent mode
1: PWM2 and PWM3 are in complementary mode
PWM0/1 output mode
0: PWM0 and PWM1 are in independent mode
1: PWM0 and PWM1 are in complementary mode
Table 5-114 PWMCON2 register
PWM_CNT
MDPRD
CMP0
0
PWM0
PWM1
Figure 5-38 PWM output in independent mode, polarity =0
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PWM_CNT
MDPRD
CMP0
0
PWM0
PWM1
Figure 5-39 PWM output in complementary mode, polarity =0
ADCPWM
Bit
Address: 0xEE
ADCPWM Control Register
7
--
0
6
--
0
5
--
0
4
0
3
2
1
0
Function
Default
ADC_SYNC_SHIFT[2:0]
0
ADC_SYNC_MODE[1:0]
0
0
0
Bit
Function
Type
Description
Condition
7:5
4:2
1:0
--
R/W
R/W
R/W
Reserved
ADC_SYNC_SHIFT[2:0]
ADC_SYNC_MODE[1:0]
ADC_SYNC PWM shift forward period
ADC sync PWM mode
only in position 2
0: ADC start to convention at position 1
1: ADC start to convention at position 2
2: ADC start to convention at position 3
3: ADC start to convention at position 4
Table 5-115 PWMCON2 register
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AD_START
1
2
3
4
PWM0
PWM_CNT
(CMP0+MDPRD)/2
CMP0
(CMP0)/2
0
If PWMCON2[7]=1 , ADC sync mode
Figure 5-40 ADC sync to PWM mode, independent mode, polarity =0 (sawtooth wave PWM)
AD_START
1
2
3
4
PWM0
PWM_CNT
(CMP0+MDPRD)/2
CMP0
(CMP0)/2
0
If PWMCON2[7]=1 , ADC sync mode
Figure 5-41 ADC sync to PWM mode, independent mode, polarity =0 (triangular wave PWM)
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Besides independent mode and complementary mode, user can
still control PWM polarity respectively by PWMCON9[5:0] register.
In independent mode, If PWMOCN9[0] is set to ‘0’, PWM0 outputs
low when PWM counter equals to CMP0. On the contrary,
PWM0 outputs high when PWM counter equals to CMP0 if
PWMCON9[0] is set to ‘1’. In complementary mode, If
PWMOCN9[1:0] is set to ‘2’b00’, PWM0 outputs high and PWM1
outputs low when PWM counter equals to CMP0. On the
contrary, PWM0 outputs low and PWM1 outputs high when PWM
counter equals to CMP0 if PWMCON9[1:0] is set to ‘2’b11’.
Figure 5-42 and Figure 5-43 show the four modes of PWM0 and
PWM1 for different PWMCON9[1:0] setting and different modes.
PWMCON9
Bit
Address: 0xA9
PWM Control Register 9
7
--
0
6
--
0
5
4
3
2
1
0
Function
Default
PWM5_POL
0
PWM4_POL
0
PWM3_POL
0
PWM2_POL
0
PWM1_POL PWM0_POL
0
0
Bit
Function
Type
Description
Condition
7:6
5
--
R/W
R/W
Reserved
PWM5_POL
PWM5 polarity setting
Independent mode:
0: PWM5 output low when PWM_cnt = CMP2
1: PWM5 output high when PWM_cnt = CMP2
Complementary mode:
0: PWM5 output low when PWM_cnt = CMP2
1: PWM5 output high when PWM_cnt = CMP2
PWM4 polarity setting
4
3
2
1
PWM4_POL
PWM3_POL
PWM2_POL
PWM1_POL
R/W
R/W
R/W
R/W
Independent mode:
0: PWM4 output low when PWM_cnt = CMP2
1: PWM4 output high when PWM_cnt = CMP2
Complementary mode:
0: PWM4 output high when PWM_cnt = CMP2
1: PWM4 output low when PWM_cnt = CMP2
PWM3 polarity setting
Independent mode:
0: PWM3 output low when PWM_cnt = CMP1
1: PWM3 output high when PWM_cnt = CMP1
Complementary mode:
0: PWM3 output low when PWM_cnt = CMP1
1: PWM3 output high when PWM_cnt = CMP1
PWM2 polarity setting
Independent mode:
0: PWM2 output low when PWM_cnt = CMP1
1: PWM2 output high when PWM_cnt = CMP1
Complementary mode:
0: PWM2 output high when PWM_cnt = CMP1
1: PWM2 output low when PWM_cnt = CMP1
PWM1 polarity setting
Independent mode:
0: PWM1 output low when PWM_cnt = CMP0
1: PWM1 output high when PWM_cnt = CMP0
Complementary mode:
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Bit
Function
Type
Description
Condition
0: PWM1 output low when PWM_cnt = CMP0
1: PWM1 output high when PWM_cnt = CMP0
PWM0 polarity setting
0
PWM0_POL
R/W
Independent mode:
0: PWM0 output low when PWM_cnt = CMP0
1: PWM0 output high when PWM_cnt = CMP0
Complementary mode:
0: PWM0 output high when PWM_cnt = CMP0
1: PWM0 output low when PWM_cnt = CMP0
Table 5-116 PWMCON9 register
PWM_CNT
MDPRD
CMP0
0
PWM0
PWM1
If PWMCON9[1:0]=2'b00, independent mode
PWM0
PWM1
If PWMCON9[1:0]=2'b01, independent mode
PWM0
PWM1
If PWMCON9[1:0]=2'b10, independent mode
PWM0
PWM1
If PWMCON9[1:0]=2'b11, independent mode
Figure 5-42 PWM output for different PWMCON9[1:0] setting under independent mode
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PWM_CNT
MDPRD
CMP0
0
PWM0
PWM1
If PWMCON9[1:0]=2'b00, complementary mode
PWM0
PWM1
If PWMCON9[1:0]=2'b01, complementary mode
PWM0
PWM1
If PWMCON9[1:0]=2'b10, complementary mode
PWM0
PWM1
If PWMCON9[1:0]=2'b11, complementary mode
Figure 5-43 PWM output for different PWMCON9[1:0] setting under complementary mode
In PWMCON3 register, PWMCON3[7] controls if writing data to
PWMCON3[5:0] register by software is synchronized to PWM
counter. If this bit is set, writing to PWMCON3 register is
succeeded when a complete PWM output is accomplished to
avoid glitch of PWM output. PWMCON3[5:0] control the PWM
output condition respectively. If corresponding bit is set to ‘1’,
PWM output is controlled by PWM time base such. On the
contrary, PWM output is controlled by the setting of PWMOVRD
register. Figure 5-44 shows the diagram of PWM output for
different PWMCON3[1:0] setting.
PWMCON3
Bit
Address: 0xDA
PWM Control Register 3
7
6
--
0
5
4
3
2
1
0
Function
Default
PWM_SYNC
0
PWM5_AUTO PWM4_AUTO PWM3_AUTO PWM2_AUTO PWM1_AUTO PWM0_AUTO
0
0
0
0
0
0
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Bit
Function
Type
Description
Condition
7
PWM_SYNC
R/W
Synchronous PWM output mode
0: S/W Directly control PWM output
1: Sync S/W control to PWM output to avoid PWM glitch
Reserved
6
--
R/W
R/W
5:0
PWMx_AUTO
(x=0~5)
PWM auto function mode
0: PWM output is controlled by PWMOVRD register
1: PWM output is controlled by PWM time base
Table 5-117 PWMCON3 register
PWMOVRD
Bit
Address: 0xDB
PWM Output Override Register
7
0
6
0
5
4
3
2
1
0
Function
Default
PWM5_OVRD PWM4_OVRD PWM3_OVRD PWM2_OVRD PWM1_OVRD PWM0_OVRD
0
0
0
0
0
0
Bit
Function
Type Description
R/W PWM override level
Condition
5:0
PWMx_OVRD
(x=0~5)
0: PWM output is forced to output low level
1: PWM output is forced to output high level
Table 5-118 PWMOVRD register
PWM_CNT
MDPRD
CMP0
0
PWM0
PWM1
If PWMCON3[1:0]=2'b11, independent mode
PWM0
PWM1
If PWMCON3[1:0]=2'b00, PWMOVRD[1:0]=2'b10
Figure 5-44 PWM output for different PWMCON3[1:0] setting
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5.13.1. Hall Sensors Detection and Built-in Comparators Control
In PWMCON4 register, PWMCON4[7:5] latch the data of
HU/HV/HW, the value of PWMCON4[7:5] equals to {HW, HV, HU}.
User can read this register to know the condition of three phases
of hall-sensors which shows the three positions of rotors.
PWMCON4[3:0] is related to auto phase changing function. The
enable bit is setting by PWMCON1[6]. If ROTOR_STATUS[2:0]
equals to MATCH_VALUE[2:0], MATCHF is set to ‘1’ and the
PWMCON3_BUF[5:0] and PWMOVRD_BUF[5:0] would copy to
PWMCON3[5:0] and PWMOVRD[5:0] automatically.
PWMCON4
Bit
Address: 0xE1
PWM Control Register 4
7
0
6
5
4
--
0
3
MATCHF
0
2
1
0
0
Function
Default
ROTOR_STATUS[2:0]
0
MATCH_VALUE[2:0]
0
0
0
Bit
Function
Type
Description
Condition
7:5
4
ROTOR_STATUS[2:0]
R
ROTOR_STATUS[2:0] = {HW/HV/HU}
Reserved
--
R/W
R/W
3
MATCHF
Match flag when ROTOR_STATUS[2:0]=
MATCH_VALUE[2:0], cleared by 1
2:0
MATCH_VALUE[2:0]
R/W
Matching values in auto phase changing mode
Table 5-119 PWMCON4 register
PWMCON1
Bit
Address: 0xB9
PWM Control Register 1
7
6
5
TMR5EN
0
4
--
0
3
2
TYPE
0
1
0
Function
Default
PWM_EN MATCH_EN
SYNC_RECT
0
PWMCK_SEL[1:0]
0
0
0
0
Bit
Function
Type Description
Condition
7
6
PWM_EN
R/W Enable PWM function
MATCH_EN
R/W Auto phase changing function enable bit
0: Disable auto phase changing function
1: Enable auto phase changing function
R/W Enable Timer 5
5
4
3
TMR5EN
--
R/W Reserved
SYNC_RECT
R/W Enable synchronous function
0: PWM0~PWM5 output mode is decided by PWMCON2[2:0]
1: PWM0/2/4 are complementary to PWM1/3/5
R/W 0: edge-aligned (sawtooth wave PWM )
1: center aligned (triangular wave PWM)
R/W PWM clock divider
2
TYPE
1:0
PWMCK_SEL[1:0]
00: SYSCLK
01: SYSCLK/2
10: SYSCLK/4
11: SYSCLK/8
Table 5-120 PWMCON1 register
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PWMCON3_BUF
Bit
Address: 0xDC
PWMCON3 Buffer Register
7
0
6
0
5
4
3
2
1
0
0
0
Function
Default
PWMCON3_BUF[5:0]
0
0
0
0
Table 5-121 PWMCON3_BUF register
PWMOVRD_BUF
Bit
Address: 0xEA
PWMOVRD Buffer Register
7
0
6
0
5
4
3
2
1
0
0
0
Function
Default
PWMOVRD_BUF[5:0]
0
0
0
0
Table 5-122 PWMOVRD_BUF register
PWMCON6[1:0] and SYSCON1[6] choose which of three inputs
are used as hall-sensors. They can come from GPIOs or three
built-in comparator outputs. PWMCON6[7:5] can switch the
hall-sensor signals and PWMCON6[4:2] can even inverse the
hall-sensors. Figure 5-45 shows the overall diagram of
HU/HV/HW for each case.
PWMCON6
Bit
Address: 0xD7
PWM Control Register 6
7
0
6
5
4
HW_INV
0
3
HV_INV
0
2
HU_INV
0
1
CAP_SEL
0
0
HS_SEL
0
Function
Default
HS_SWITCH[2:0]
0
0
Bit
Function
Type
Description
Condition
7:5
R/W
PWMCON6[7:5] HU_pre_o
HV_pre_o
HV_pre
HW_pre
HU_pre
HW_pre
HU_pre
HV_pre
HV_pre
HV_pre
HW_pre_o
HW_pre
HV_pre
HW_pre
HU_pre
HV_pre
HU_pre
HW_pre
HW_pre
0
1
2
3
4
5
6
7
HU_pre
HU_pre
HV_pre
HV_pre
HW_pre
HW_pre
HU_pre
HU_pre
HS_SWITCH[2:0]
4
3
2
HW_INV
HV_INV
HU_INV
R/W
R/W
R/W
HW inverse control bit
0: HW=HW_pre_o
1: HW=~HW_pre_o
HV inverse control bit
0: HV=HV_pre_o
1: HV=~HV_pre_o
HU inverse control bit
0: HU=HU_pre_o
1: HU=~HU_pre_o
Hall-sensors switch bit
1
0
CAP_SEL
HS_SEL
R/W
R/W
0: P12/P13/P14 are used as hall-sensors
1: Built-in comparator output are used as hall-sensors
Table 5-123 PWMCON6 register
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SYSCON1
Bit
Address: 0xAF
SYSTEM Control1 Register
7
6
HV_SEL
0
5
SPI1_EN
0
4
SPI0_EN
0
3
--
0
2
--
0
1
--
1
0
--
1
Function
Default
Key Code
T2CLK_SW
0
FF,00
Bit
Function
Type
Description
Condition
7
T2CLK_SW
R/W
Timer 2 timer function input frequency switch
0: SYSCLK/12 (T2PS=0) or SYSCLK/24 (T2PS=1)
1: SYSCLK/1 (T2PS=0) or SYSCLK/2 (T2PS=1)
0: P07/P40/P41 are used as hall-sensors
1: P07/P05/P41 are used as hall-sensors
SPI signals forward to P3[6:4] enable
P3[4]: SPI_CLK
6
5
HV_SEL
SPI1_EN
R/W
R/W
P3[5]: SPI_TX
P3[6]: SPI_RX
4
SPI0_EN
R/W
R/W
SPI signals forward to P0[7:4] enable
P0[4]: SPI_CSB
P0[5]: SPI_CLK
P0[6]: SPI_TX
P0[7]: SPI_RX
3:0
--
Reserved
Table 5-124 SYSCON1 register
HS_SEL
PWMCON6 [0]
CAP_SEL
PWMCON6 [1]
P12/P13/P14
IO mode
PWMCON6 [7:2]
P43/P40/P41
+
-
Analog input mode
HU_Pre
HV_Pre
HW_Pre
HU
HV
HW
P07/P40/P41
Analog input mode
PWM
Sensorless
Comparator
HU_DET_SEL
CMPCON1 [2]
P07/P40/P41
IO mode
P07/P05/P41
IO mode
HV_SEL
SYSCON1 [6]
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HU/HV/HW Swith3:
PWMCON6[7:5]
PWMCON6[2]
PWMCON6[4]
PWMCON6[7:5]
PWMCON6[7:5]
PWMCON6[3]
HU_pre
HU_pre
HU_pre
HV_pre
HW_pre
HU_pre_o
HV_pre
HW_pre
HW_pre_o
HV_pre
HW_pre
HV_pre_o
0
1
0
1
0
1
HU
HW
HV
Figure 5-45 HU/HV/HW input diagrams
For cost consideration or possible damage of hall sensors,
sensorless motor are developed. In GPM8F3132A/3116A,
built-in three comparators are used to replace hall sensors to
provide the position of the rotors and the related control registers
are CMPCON1. Figure 5-46 shows the diagram of built-in three
comparators.
CMPCON1
Bit
Address: 0xAA
Comparator Control Register 1
7
--
0
6
--
0
5
--
0
4
P41_AEN
0
3
P40_AEN
0
2
1
0
CMP_EN
0
Function
Default
HU_DET_SEL SCHMIT_EN
1
0
Bit
Function
Type
Description
Condition
7:5
4
--
R/W
R/W
Reserved
P41_AEN
P41 analog PAD enable control bit
0: P41 can be I/O PAD
1: P41 can be analog PAD
P40 analog PAD enable control bit
0: P40 can be I/O PAD
3
2
R/W
R/W
P40_AEN
1: P40 can be analog PAD
HU_DET pad select control bit
0: P43 is used as HU_DET pad
1: P07 is used as HU_DET pad
0: Disable schmitt window
HU_DET_SEL
1
0
SCHMIT_EN
CMP_EN
R/W
R/W
1: Enable schmitt window (30mV)
Enable three comparators to produce sensorless signals
Table 5-125 CMPCON1 register
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GPM8F3132A/3116A/3108A
5V
10K
Resistance
Regulator
24V
0V
Inside CHIP
CMP_EN
Outside
CHIP
HU_DET_SEL
P43
2K
HU_DET
2K
R1
P07
P40
HU_LESS
HV_LESS
MU
MV
MW
+
110K
R3
CMPU
0.1u
0.22u
R2
R2
-
MU
MV
2K
R1
2K
2K
HV_DET
0.1u
+
110K
R3
CMPV
0.22u
-
2K
R1
P41
MW
HW_DET
0.1u
HW_LESS
+
110K
R3
CMPW
-
R2
Note: 1. R1< R3/(5~7), R3=110K or 160K
2. 24V*R2/(R1+R2) < 4V
3. CMPU/V/W schmitt-window = 0V
@SCHMIT_EN=0 (default)
schmitt-window = 30mV @SCHMIT_EN=1
Figure 5-46 Built-in three comparators
5.13.2. Protective Circuits
In GPM8F3132A/3116A/3108A, there is a protective circuit for
over-current protective circuit. The related control register are in
PWMCON5[0] as tabled in Table 5-126. PWMCON5[0] is the
enable bit of protection of over-current. If PWMCON5[0] is set to
‘1’, PWM output will be disabled while the input of OC(P15 or
CMPOC output) is low. Meanwhile, the related flag(OCF) is set
to ‘1’ (falling edge active). When the OC is keep in low state, it is
useless to enable PWM output(PWMCON2[5:3]) and PWM
function(PWMCON1[7]) by software. In addition to this, for
protecting power switches against burnout, MOS protect function
is also achieved in this chip. User can turn on the protect
function by PWMCON8[0] and choose different protection ways by
PWMCON8[2:1]. For measuring the current of power switches,
additional OP and comparator are also included, and the related
control registers are CMPCON2. If P0[6:2] are needed to be
analog pad, ADAEN must be set first to enable analog pad
function. Figure 5-47 shows the diagram of built-in OP and
comparators.
PWMCON5
Bit
Address: 0xCF
PWM Control Register 5
7
6
0
5
4
0
3
2
1
--
0
0
OC_EN
0
Function
Default
OC_FILTER_SEL
0
TIMER5_CKSEL[2:0]
0
PERIOD_TRIG_MD[1:0]
0
0
Bit
Function
Type Description
Condition
7
OC_FILTER_SEL
R/W Over-current pad filter selection
0: 4us filter
1: 0.4us filter
6:4
TIMER5_CKSEL[2:0]
R/W Timer 5 clock select bits
000: SYSCLK /8
001: SYSCLK /16
010: SYSCLK /32
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Bit
Function
Type Description
011: SYSCLK /64
Condition
100: SYSCLK /128
101: SYSCLK /256
110: SYSCLK /512
111: SYSCLK /1024
3:2
PERIOD_TRIG_MD[1:0]
R/W PWM period triggered mode
00: every 1 PWM period trigger
01: every 2 PWM periods trigger
10: every 4 PWM periods trigger
11: every 8 PWM periods trigger
R/W Reserved
1
0
--
OC_EN
R/W Enable over-current protection
Table 5-126 PWMCON5 register
PWMCON8
Bit
Address: 0xB5
PWM Control Register 8
7
6
5
4
0
3
--
0
2
1
0
Function
Default
SIN_LOSE_LEVEL[3:0]
MOS_PRO_SEL[1:0]
MOS_PRO_EN
0
0
0
0
0
0
Bit
Function
Type Description
Condition
7:4
SIN_LOSE_LEVEL[3:0]
R/W 0: 7’h07
1: 7’h0F
2: 7’h17
3: 7’h1F
4: 7’h27
5: 7’h2F
6: 7’h37
7: 7’h3F
8: 7’h47
9: 7’h4F
10: 7’h57
11: 7’h5F
12: 7’h67
13: 7’h6F
14: 7’h77
15: 7’h7F
R/W Reserved
3
--
2:1
MOS_PRO_SEL[1:0]
R/W Power MOS protection mode selection
00: disable PWM output if PWM0/PWM2/PWM4 and PWM1/PWM3/PWM5
output low
01: disable PWM output if PWM0/PWM2/PWM4 output high and
PWM1/PWM3/PWM5 output low
10: disable PWM output if PWM0/PWM2/PWM4 output low and
PWM1/PWM3/PWM5 output high
11: disable PWM output if PWM0/PWM2/PWM4 and PWM1/PWM3/PWM5
output high
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GPM8F3132A/3116A/3108A
Bit
Function
Type Description
Condition
0
MOS_PRO_EN
R/W Enable power MOS protect function
Table 5-127 PWMCON8 register
CMPCON2
Bit
Address: 0xAB
Comparator Control Register 2
7
--
0
6
--
0
5
OC_status
0
4
3
2
OC_SEL
0
1
0
OP_EN
0
Function
Default
TRIM_VOSP TRIM_VOSN
CMPOC_EN
0
0
0
Bit
Function
Type
Description
Condition
7:6
5
--
R/W
R/W
R/W
R/W
R/W
Reserved
OC status
OC_status
TRIM_VOSP
TRIM_VOSN
OC_SEL
4
Trimming bit for OP offset (V+)
Trimming bit for OP offset (V+)
3
2
0: OC is come from built-in CMPOC output
1: OC is come from P15
1
0
CMPOC_EN
OP_EN
R/W
R/W
Enable CMPOC function for current measuring
Enable OP function
Table 5-128 CMPCON2 register
5V
20K
1.2K
P02
V+
V-
OC
+
CMPOC
I_MOTOR
-
P03
1K
CMPOC_EN
OP_EN
Note: 1. CMPOC schmitt-window = 0V
P04
V+
1K
1K
10K
To ADC channel 6
+
P05
OP
-
V-
P06
10K
OP_OUT
Figure 5-47 Built-in OP and comparator
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5.13.3. 16-bit Capture Unit Control
Besides PWM output, there is a TIMER 5 for counting periods of
HU/HV/HW signals. PWMCON1[5] is set to ‘1’ to enable TIMER
every falling edge of capture signal. If CAPnCON[1:0] is set to
‘10’, capture occurs at every rising edge of capture signal. If
CAPnCON[1:0] is set to ‘11’, capture occurs at every falling and
rising edge of capture signal. At each capture, the current 16-bit
5
function and the counting frequency is controlled by
PWMCON5[6:4]. CAP0CON, CAP1CON and CAP2CON register
control the capture modes of HU/HV/HW respectively. In
value of TIMER5 is latched to CAPnBUF register.
As to
CAPnCON register, CAPnCON[1:0] determine the condition of
capture. If CAPnCON[1:0] is set to ‘00’, capture function is
turned off. If CAPnCON[1:0] is set to ‘01’, capture occurs at
CAPnCON[3], it controls whether TIMER5 is reset for every
capture. Figure 5-48 and Figure 5-49 show the diagram of
capture function for different CAPnCON setting.
PWMCON1
Bit
Address: 0xB9
PWM Control Register 1
7
6
5
TMR5EN
0
4
--
0
3
2
TYPE
0
1
0
Function
Default
PWM_EN MATCH_EN
SYNC_RECT
0
PWMCK_SEL[1:0]
0
0
0
0
Bit
Function
Type Description
Condition
7
6
PWM_EN
R/W Enable PWM function
MATCH_EN
R/W Auto phase changing function enable bit
0: Disable auto phase changing function
1: Enable auto phase changing function
R/W Enable Timer 5
5
4
3
TMR5EN
--
R/W Reserved
SYNC_RECT
R/W Enable synchronous function
0: PWM0~PWM5 output mode is decided by PWMCON2[2:0]
1: PWM0/2/4 are complementary to PWM1/3/5
R/W 0: edge-aligned (sawtooth wave PWM )
1: center aligned (triangular wave PWM)
R/W PWM clock divider
2
TYPE
1:0
PWMCK_SEL[1:0]
00: SYSCLK
01: SYSCLK/2
10: SYSCLK/4
11: SYSCLK/8
Table 5-129 PWMCON1 register
PWMCON5
Bit
Address: 0xCF
PWM Control Register 5
7
6
0
5
4
0
3
2
1
--
0
0
Function
Default
OC_FILTER_SEL
0
TIMER5_CKSEL[2:0]
0
PERIOD_TRIG_MD[1:0]
OC_EN
0
0
0
Bit
Function
Type Description
Condition
7
OC_FILTER_SEL
R/W Over-current pad filter selection
0: 4us filter
1: 0.4us filter
6:4
TIMER5_CKSEL[2:0]
R/W Timer 5 clock select bits
000: SYSCLK /8
001: SYSCLK /16
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Bit
Function
Type Description
010: SYSCLK /32
Condition
011: SYSCLK /64
100: SYSCLK /128
101: SYSCLK /256
110: SYSCLK /512
111: SYSCLK /1024
3:2
PERIOD_TRIG_MD[1:0]
R/W PWM period triggered mode
00: every 1 PWM period trigger
01: every 2 PWM periods trigger
10: every 4 PWM periods trigger
11: every 8 PWM periods trigger
R/W Reserved
1
0
--
OC_EN
R/W Enable over-current protection
Table 5-130 PWMCON5 register
CAP0CON
Bit
Address: 0xDD
PWM CAP0 Control Register
7
--
0
6
5
--
0
4
TF5
0
3
2
--
0
1
0
Function
Default
--
0
CAP0_TMR5_RST
0
CAP0_MODE[1:0]
0
0
Bit
Function
Type
Description
Condition
7:5
4
--
R/W
R/W
R/W
R/W
Reserved
TF5
Timer 5 overflow flag
3
CAP0_TMR5_RST
CAP0_MODE[1:0]
1: Timer 5 will be reset while CAPTURE0 is triggered
00: CAPTURE0 is off
1:0
01: CAPTURE0 captures at every falling edge
10: CAPTURE0 captures at every rising edge
11: CAPTURE0 captures at every state change
Table 5-131 CAP0CON register
CAP1CON
Bit
Address: 0xDE
PWM CAP1 Control Register
7
--
0
6
5
--
0
4
--
0
3
2
--
0
1
0
Function
Default
--
0
CAP1_TMR5_RST
0
CAP1_MODE[1:0]
0
0
Bit
Function
Type
Description
Condition
7:4
3
--
R/W
R/W
R/W
Reserved
CAP1_TMR5_RST
CAP1_MODE[1:0]
1: Timer 5 will be reset while CAPTURE1 is triggered
00: CAPTURE1 is off
1:0
01: CAPTURE1captures at every falling edge
10: CAPTURE1 captures at every rising edge
11: CAPTURE1 captures at every state change
Table 5-132 CAP1CON register
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CAP2CON
Bit
Address: 0xDF
PWM CAP2 Control Register
7
--
0
6
--
0
5
--
0
4
--
0
3
2
--
0
1
0
Function
Default
CAP2_TMR5_RST
0
CAP2_MODE[1:0]
0
0
Bit
Function
Type
Description
Condition
7:4
3
--
R/W
R/W
R/W
Reserved
CAP2_TMR5_RST
CAP2_MODE[1:0]
1: Timer 5 will be reset while CAPTURE2 is triggered
00: CAPTURE 2 is off
1:0
01: CAPTURE 2 captures at every falling edge
10: CAPTURE 2 captures at every rising edge
11: CAPTURE 2 captures at every state change
Table 5-133 CAP2CON register
CAP0BUFH
Bit
Address: 0xE3
MSB of PWM Capture0 Buffer
7
0
6
0
5
4
0
3
CAP0BUF[15:8]
0
2
1
1
0
0
Function
Default
0
0
CAP0BUFL
Bit
Address: 0xE2
LSB of PWM Capture0 Buffer
7
1
6
0
5
4
1
3
CAP0BUF[7:0]
1
2
1
0
0
0
Function
Default
0
1
Table 5-134 CAP0BUF register
CAP1BUFH
Bit
Address: 0xE5
MSB of PWM Capture1 Buffer
7
0
6
0
5
4
0
3
CAP1BUF[15:8]
0
2
1
1
0
0
Function
Default
0
0
CAP1BUFL
Bit
Address: 0xE4
LSB of PWM Capture1 Buffer
7
1
6
0
5
4
1
3
CAP1BUF[7:0]
1
2
1
0
0
0
Function
Default
0
1
Table 5-135 CAP1BUF register
CAP2BUFH
Bit
Address: 0xE7
MSB of PWM Capture2 Buffer
7
0
6
0
5
4
0
3
CAP2BUF[15:8]
0
2
1
1
0
0
Function
Default
0
0
CAP2BUFL
Bit
Address: 0xE6
LSB of PWM Capture2 Buffer
7
1
6
0
5
4
1
3
CAP2BUF[7:0]
1
2
1
0
0
0
Function
Default
0
1
Table 5-136 CAP2BUF register
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TIMER5_CLK
TIMER5
1
5
0
0
1
2
3
1
2
3
4
0
HU
CAP0BUF[15:0]
0
3
5
If CAP0CON[1:0]=2'b11, CAP0CON[3]=1
Figure 5-48 The diagram of capture function if CAP0CON[1:0]=2’b11 and CAP0CON[3]=1
TIMER5_CLK
TIMER5
8
9
8
6
0
1
2
3
4
5
7
HU
CAP0BUF[15:0]
0
If CAP0CON[1:0]=2'b10, CAP0CON[3]=0
Figure 5-49 The diagram of capture function if CAP0CON[1:0]=2’b10 and CAP0CON[3]=0
5.13.4. Interrupt Sources
In GPM8F3132A/3116A/3108A, there are seven types for interrupt
sources for PWM module. Each interrupt source can be
individually enabled or disabled by setting or cleaning
corresponding bit in PWMIE register. If PWM interrupt is
each PWM period is completed. If PWMCON5[3:2] is set to
2’b01, period interrupt will occur while every two PWM period is
completed. If PWMCON5[3:2] is set to 2’b10, period interrupt will
a
occur while every four PWM period is completed.
If
occurred, PWMIF register can be monitored to see which interrupt
source is produced except MATCHF and the PWM flag is need to
be cleared by software. OCF is set to be ‘1’ if protect function is
enabled and corresponding OC is low. CAP0F~CAP2F are set to
PWMCON5[3:2] is set to 2’b11, period interrupt will occur while
every eight PWM period is completed. HS_CHGF is set to be ‘1’
if Hall-sensor changes. MATCHF(shown by PWMCON4[3]) is set
to be ‘1’ if ROTOR_STATUS[2:0]= MATCH_VALUE[2:0] while
MATCH function is enabled. Figure 5-50 and Figure 5-51 show
the diagram of period interrupt for different PWMCON5[3:2] and
PWMCON1[2] setting.
be ‘1’ if capture function is occurred.
PWMCON5[3:2] controls the mode of period interrupt of PWMIE[5]
and PWMIF[5], and the related flag is PERIODF. If
PWMCON5[3:2] is set to 2’b00, period interrupt will occur while
In PWMCON5,
PWMIF
Bit
Address: 0xB1
PWM Interrupt Flag Register
7
--
0
6
HS_CHGF
0
5
PERIODF
0
4
CAP2F
0
3
CAP1F
0
2
CAP0F
0
1
--
0
0
OCF
0
Function
Default
Bit
Function
Type
Description
Condition
7
6
5
--
R/W
R/W
R/W
Reserved
HS_CHGF
PERIODF
HS change interrupt flag, cleared by 1
PWM period interrupt flag, cleared by 1
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Bit
Function
Type
Description
Condition
4
3
2
1
0
CAP2F
CAP1F
CAP0F
--
R/W
R/W
R/W
R/W
R/W
CAPTURE2 pad interrupt flag, cleared by 1
CAPTURE 1 pad interrupt flag, cleared by 1
CAPTURE 0 pad interrupt flag, cleared by 1
Reserved
OCF
Over-current interrupt flag, cleared by 1
Table 5-137 PWMIF register
PWMIE
Bit
Address: 0xB2
PWM Interrupt enable Register
7
6
5
4
CAP2IE
0
3
CAP1IE
0
2
CAP0IE
0
1
--
0
0
OCIE
0
Function
Default
MATCHIE HS_CHGIE
PERIODIE
0
0
0
Bit
Function
Type
Description
Enable MATCH interrupt
Condition
7
6
5
4
3
2
1
0
MATCHIE
HS_CHGIE
PERIODIE
CAP2IE
CAP1IE
CAP0IE
--
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enable Hall-sensor changes interrupt
Enable PWM period interrupt
Enable CAPTURE 2 pad interrupt
Enable CAPTURE 1 pad interrupt
Enable CAPTURE 0 pad interrupt
Reserved
OCIE
Enable over-current interrupt
Table 5-138 PWMIE register
PWMCON5
Bit
Address: 0xCF
PWM Control Register 5
7
6
5
4
0
3
2
1
--
0
0
OC_EN
0
Function
Default
OC_FILTER_SEL
0
TIMER5_CKSEL[2:0]
0
PERIOD_TRIG_MD[1:0]
0
0
0
Bit
Function
Type Description
Condition
7
OC_FILTER_SEL
R/W Over-current pad filter selection
0: 4us filter
1: 0.4us filter
6:4
TIMER5_CKSEL[2:0]
R/W Timer 5 clock select bits
000: SYSCLK /8
001: SYSCLK /16
010: SYSCLK /32
011: SYSCLK /64
100: SYSCLK /128
101: SYSCLK /256
110: SYSCLK /512
111: SYSCLK /1024
3:2
PERIOD_TRIG_MD[1:0]
R/W PWM period triggered mode
00: every 1 PWM period trigger
01: every 2 PWM periods trigger
10: every 4 PWM periods trigger
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Bit
Function
Type Description
11: every 8 PWM periods trigger
R/W Reserved
Condition
1
0
--
OC_EN
R/W Enable over-current protection
Table 5-139 PWMCON5 register
PWM_CNT
MDPRD
CMP0
0
PWM0
PWM1
PERIOD INTERRUPT
PWMCON5[3:2]=2'b00
PERIOD INTERRUPT
PWMCON5[3:2]=2'b01
PERIOD INTERRUPT
PWMCON5[3:2]=2'b10
PERIOD INTERRUPT
PWMCON5[3:2]=2'b11
Figure 5-50 The diagram of period interrupt for different PWMCON5[3:2] setting(sawtooth wave PWM)
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PWM_CNT
MDPRD
CMP0
0
PWM0
PWM1
PERIOD INTERRUPT
PWMCON5[3:2]=
2'b00 and 2'b01
PERIOD INTERRUPT
PWMCON5[3:2]=2'b10
PERIOD INTERRUPT
PWMCON5[3:2]=2'b11
Figure 5-51 The diagram of period interrupt for different PWMCON5[3:2] setting (triangular wave PWM)
5.13.5. Sine-wave PWM control (only in GPM8F3132A)
In addition to traditional PWM output for trapezoid waveform,
PWM output for sinusoidal waveform is also realized in this chip.
position of hall U and motor rotate direction. If PWMSINCON[2]
is set to ‘1’, rising of Hall U is the start position, otherwise, falling
of Hall U is the start position. If PWMSINCON[3] is set to ‘1’
motor rotate direction is reverse, otherwise, rotate direction is
forward.
The
related
control
registers
are
PWMSINCON,
ADDR_OFFSET[15:0] and PWMCON8[7:4], which are described
as below. PWMSINCON[2] and PWMSINCON[3] control the start
PWMSINCON
Bit
Address: 0xBD
PWMSIN Control Register
7
6
0
5
--
0
4
0
3
2
1
0
SIN_EN
0
Function
Default
SFR_ANG_EN
0
PHASE_DIRECT HALL_SATRT FLOAT_DIS
0
0
0
Bit
Function
Type Description
Condition
7
SFR_ANG_EN
R/W Angle address readable enable bit
0: NA
1: ANGLE_ADDRESS[8:0]= ADDR_OFFSET[15:7]
LOSE_ADDR[6:0] = ADDR_OFFSET[6:0]
6:4
3
--
R/W Reserved
PHASE_DIRECT
R/W Motor rotate direction
0: Forward
1: Reverse
2
1
HALL_SATRT
FLOAT_DIS
R/W Hall U start position
0: Falling
1: Rising
R/W PWM output control while angle address equals to 512
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Bit
Function
Type Description
0: PWMs keep on output
Condition
1: PWMs output low
0
SIN_EN
R/W Enable sin wave function
Table 5-140 PWMSINCON register
ADDR_OFFSETH
Bit
Address: 0xBF
ADDR_OFFSETH Register
7
0
6
0
5
4
3
2
1
0
0
0
Function
Default
ADDR_OFFSET[15:8]
0
0
0
0
ADDR_OFFSETL
Bit
Address: 0xBE
ADDR_OFFSETL Register
7
0
6
0
5
4
3
2
1
0
0
0
Function
Default
ADDR_OFFSET[7:0]
0
0
0
0
Table 5-141 ADDR_OFFSET register
PWMCON8
Bit
Address: 0xB5
PWM Control Register 8
7
0
6
5
4
0
3
--
0
2
1
0
Function
Default
SIN_LOSE_LEVEL[3:0]
MOS_PRO_SEL[1:0]
MOS_PRO_EN
0
0
0
0
0
Bit
Function
Type Description
Condition
7:4
SIN_LOSE_LEVEL[3:0]
R/W 0: 7’h07
1: 7’h0F
2: 7’h17
3: 7’h1F
4: 7’h27
5: 7’h2F
6: 7’h37
7: 7’h3F
8: 7’h47
9: 7’h4F
10: 7’h57
11: 7’h5F
12: 7’h67
13: 7’h6F
14: 7’h77
15: 7’h7F
R/W Reserved
3
--
2:1
MOS_PRO_SEL[1:0]
R/W Power MOS protection mode selection
00: disable PWM output if PWM0/PWM2/PWM4 and PWM1/PWM3/PWM5
output low
01: disable PWM output if PWM0/PWM2/PWM4 output high and
PWM1/PWM3/PWM5 output low
10: disable PWM output if PWM0/PWM2/PWM4 output low and
PWM1/PWM3/PWM5 output high
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Bit
Function
Type Description
11: disable PWM output if PWM0/PWM2/PWM4 and PWM1/PWM3/PWM5
output high
Condition
0
MOS_PRO_EN
R/W Enable power MOS protect function
Table 5-142 PWMCON8 register
5.14. Audio Unit
In GPM8F3132A/3116A/3108A, there is one audio control unit
utilized for audio application. The related control registers are
AUDCON and AUDBUF. When audio function is enabled, P36
and P37 are used as AUDIO_N and AUDIO_P in default setting,
user can disable the output of AUDIO_N and leave P36 as GPIO
by setting SYSCON0[4]. Figure 5-52 shows the diagram of P36
and P37 output for different AUDCON settings.
AUDCON
Bit
Address: 0xB3
Audio Control Register
7
-
6
-
5
--
0
4
--
0
3
2
AUDIOIE
0
1
0
Function
Default
AUDIO_MODE
0
AUDIO_FREQ_SEL
0
AUDIO_EN
0
0
0
Bit
Function
Type
Description
Condition
7:4
3
--
R/W
R/W
Reserved
AUDIO_MODE
Audio mode selection
0: x
1: PWM mode
2
1
AUDIOIE
R/W
R/W
Enable audio interrupt
Audio output frequency selection
0: AUDIO_24KHz output
1: AUDIO_32KHz output
Enable audio function
AUDIO_FREQ_SEL
0
AUDIO_EN
R/W
Table 5-143 AUDCON register
AUDBUF
Bit
Address: 0xB4
Audio Buffer Register
7
1
6
0
5
4
0
3
AUDBUF[7:0]
0
2
1
0
0
0
Function
Default
0
0
Table 5-144 AUDBUF register
SYSCON0
Bit
Address: 0xAE
SYSTEM control0 Register
7
6
5
4
3
--
0
2
1
0
Function
SCHMIT_DIS_
LVRENB
--
0
--
0
AUDIO_N_DIS
0
CLKOUT_EN CCOUTENB
P4
0
Default
0
0
0
Key Code
FF,00
Bit
Function
Type
Description
Condition
7
LVRENB
R/W
LVR enable control
0: enable LVR function
1: disable LVR function
Reserved
6:5
--
--
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Bit
Function
Type
Description
Condition
4
AUDIO_N_DIS
R/W
AUDIO_N disable bit available only if audio function is enabled
0: P36/P37 are output simultaneously as AUDIO_N/P
1: Only P37 is output as AUDIO_P
3
2
1
--
--
Reserved
CLKOUT_EN
CCOUTENB
R/W
R/W
Clock output enable bit (SYSCLK is output on P35)
Disable output function of compare mode in Timer2
0: P1[3:1] = {compare3,compare2,compare1}
1: P1[3:1] is GPIO
0
SCHMIT_DIS_P4
R/W
P4 schmitt trigger function disable control bit
Table 5-145 SYSCON0 register
AUDIO_CNT
8'hff
AUDBUF[7:0]
0
F= 24KHz
AUDIO_P
AUDIO_N
If AUDCON[7:0]=8'h09 (Audio 24KHz output)
AUDIO_CNT
8'hff
AUDBUF[7:0]
0
F= 32KHz
AUDIO_P
AUDIO_N
If AUDCON[7:0]=8'h0A (Audio 32KHz output)
Figure 5-52 The diagram of P36(AUDIO_N) and P37(AUDIO_P) output for audio application
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5.15. Alphabetical List of Instruction Set
5.15.1. Arithmetic Operations
Mnemonic
ADD A,Rn
ADD A,direct
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,direct
ADDC A,@Ri
ADDC A,#data
SUBB A,Rn
SUBB A,direct
SUBB A,@Ri
SUBB A,#data
INC A
Description
Code
0x28-0x2F
0x25
Bytes
Cycles
Add register to accumulator
Add direct byte to accumulator
Add indirect RAM to accumulator
Add immediate data to accumulator
Add register to accumulator with carry flag
Add direct byte to A with carry flag
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment accumulator
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
1
2
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
2
3
3
1
2
3
3
1
2
6
3
0x26-0x27
0x24
0x38-0x3F
0x35
0x36-0x37
0x34
0x98-0x9F
0x95
0x96-0x97
0x94
0x04
INC Rn
Increment register
0x08-0x0F
0x05
INC direct
INC @Ri
Increment direct byte
Increment indirect RAM
0x06-0x07
0x14
DEC A
Decrement accumulator
DEC Rn
Decrement register
0x18-0x1F
0x15
DEC direct
DEC @Ri
INC DPTR
MUL A,B
Decrement direct byte
Decrement indirect RAM
0x16-0x17
0xA3
Increment data pointer
Multiply A and B
0xA4
DIV A,B
Divide A by B
0x84
DA A
Decimal adjust accumulator
0xD4
5.15.2. Logic Operations
Mnemonic
ANL A,Rn
Description
Code
0x58-0x5F
0x55
Bytes
Cycles
AND register to accumulator
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
1
2
2
2
3
3
1
2
2
2
3
3
1
2
2
2
ANL A,direct
ANL A,@Ri
AND direct byte to accumulator
AND indirect RAM to accumulator
AND immediate data to accumulator
AND accumulator to direct byte
AND immediate data to direct byte
OR register to accumulator
0x56-0x57
0x54
ANL A,#data
ANL direct,A
ANL direct,#data
ORL A,Rn
0x52
0x53
0x48-0x4F
0x45
ORL A,direct
ORL A,@Ri
ORL A,#data
ORL direct,A
ORL direct,#data
XRL A,Rn
OR direct byte to accumulator
OR indirect RAM to accumulator
OR immediate data to accumulator
OR accumulator to direct byte
0x46-0x47
0x44
0x42
OR immediate data to direct byte
Exclusive OR register to accumulator
Exclusive OR direct byte to accumulator
Exclusive OR indirect RAM to accumulator
Exclusive OR immediate data to accumulator
0x43
0x68-0x6F
0x65
XRL A,direct
XRL A,@Ri
0x66-0x67
0x64
XRL A,#data
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Mnemonic
XRL direct,A
XRL direct,#data
CLR A
Description
Code
0x62
0x63
0xE4
0xF4
0x23
0x33
0x03
0x13
0xC4
Bytes
Cycles
Exclusive OR accumulator to direct byte
Exclusive OR immediate data to direct byte
Clear accumulator
2
3
1
1
1
1
1
1
1
3
3
1
1
1
1
1
1
1
CPL A
Complement accumulator
RL A
Rotate accumulator left
RLC A
Rotate accumulator left through carry
Rotate accumulator right
RR A
RRC A
Rotate accumulator right through carry
Swap nibbles within the accumulator
SWAP A
5.15.3. Boolean Operations
Mnemonic
CLR C
Description
Code
Bytes
Cycles
Clear carry flag
0xC3
0xC2
0xD3
0xD2
0xB3
0xB2
0x82
0xB0
0x72
0xA0
0xA2
0x92
1
2
1
2
1
2
2
2
2
2
2
2
1
3
1
3
1
3
2
2
2
2
2
3
CLR bit
Clear direct bit
SETB C
Set carry flag
SETB bit
CPL C
Set direct bit
Complement carry flag
Complement direct bit
AND direct bit to carry flag
AND complement of direct bit to carry
OR direct bit to carry flag
OR complement of direct bit to carry
Move direct bit to carry flag
Move carry flag to direct bit
CPL bit
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
MOV bit,C
5.15.4. Data Transfers
Mnemonic
MOV A,Rn
Description
Code
0xE8-0xEF
0xE5
Bytes
Cycles
Move register to accumulator
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
2
2
2
1
3
2
2
2
3
3
3
2
3
2
3
5
4
MOV A,direct
Move direct byte to accumulator
Move indirect RAM to accumulator
Move immediate data to accumulator
Move accumulator to register
MOV A,@Ri
0xE6-0xE7
0x74
MOV A,#data
MOV Rn,A
0xF8-0xFF
0xA8-0xAF
0x78-0x7F
0xF5
MOV Rn,direct
MOV Rn,#data
MOV direct,A
Move direct byte to register
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
MOV direct,Rn
MOV direct1,direct2
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
0x88-0x8F
0x85
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate data to direct byte
Move accumulator to indirect RAM
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Load 16-bit constant into active DPH and DPL in LARGE mode
Move code byte relative to DPTR to accumulator
Move code byte relative to PC to accumulator
0x86-0x87
0x75
0xF6-0xF7
0xA6-0xA7
0x76-0x77
0x90
MOV @Ri,direct
MOV @Ri,#data
MOV DPTR,#data16
MOVC A,@A+DPTR
MOVC A,@A+PC
0x93
0x83
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Mnemonic
Description
Code
Bytes
Cycles
XDM
3*
3
MOVX A,@Ri
Move external RAM (8-bit address) to A
0xE2-0xE3
1
SXDM
XDM
2*
2
MOVX A,@DPTR
MOVX @Ri,A
Move external RAM (16-bit address) to A
0xE0
1
1
SXDM
Move A to external XDM (8-bit ODE inside ROM/RAM
4*
5*
address)
Other cases
0xF2-0xF3
Move A to external SXDM (8-bit
address)
All cases
3
Move A to external XDM (16-bit CODE inside ROM/RAM
3*
4*
address)
Other cases
MOVX @DPTR,A
0xF0
1
Move A to external SXDM (16-bit
address)
All cases
2
PUSH direct
POP direct
Push direct byte onto IDM stack
Pop direct byte from IDM stack
Exchange register with accumulator
Exchange direct byte with accumulator
0xC0
0xD0
2
2
1
2
1
1
3
2
2
3
3
3
XCH A,Rn
0xC8-0xCF
0xC5
XCH A,direct
XCH A,@Ri
XCHD A,@Ri
Exchange indirect RAM with accumulator
0xC6-0xC7
0xD6-0xD7
Exchange low-order nibble indirect RAM with A
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GPM8F3132A/3116A/3108A
5.15.5. Program Branches
Mnemonic
ACALL addr11
LCALL addr16
RET
Description
Code
0x11-0xF1
0x12
Bytes
Cycles
Absolute subroutine call
2
3
1
1
2
3
2
1
2
2
2
2
3
3
3
3
3
3
3
2
3
1
4
4
4
4
3
4
3
5
4
4
3
3
5
5
5
5
4
4
5
4
5
1
Long subroutine call
Return from subroutine
0x22
RETI
Return from interrupt
0x32
AJMP addr11
LJMP addr16
SJMP rel
Absolute jump
0x01-0xE1
0x02
Long jump
Short jump (relative address)
Jump indirect relative to the DPTR
Jump if accumulator is zero
Jump if accumulator is not zero
Jump if carry flag is set
0x80
JMP @A+DPTR
JZ rel
0x73
0x60
JNZ rel
0x70
JC rel
0x40
JNC
Jump if carry flag is not set
0x50
JB bit,rel
Jump if direct bit is set
0x20
JNB bit,rel
Jump if direct bit is not set
0x30
JBC bit,direct rel
CJNE A,direct rel
CJNE A,#data rel
CJNE Rn,#data rel
CJNE @Ri,#data rel
DJNZ Rn,rel
DJNZ direct,rel
NOP
Jump if direct bit is set and clear bit
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to reg. and jump if not equal
Compare immediate to ind. and jump if not equal
Decrement register and jump if not zero
Decrement direct byte and jump if not zero
No operation
0x10
0xB5
0xB4
0xB8-0xBF
0xB6-0xB7
0xD8-0xDF
0xD5
0x00
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GPM8F3132A/3116A/3108A
6. ELECTRICAL CHARACTERISTICS
6.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
V+
VIN
-0.3V ~ 6.0V
-0.3V to V+ + 0.3V
-40℃ to +85℃
100mA
Input Voltage Range
Operating Temperature
VDD Total MAX Current
VSS Total MAX Current
TA
IVDDM
IVSSM
150mA
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
conditions see AC/DC Electrical Characteristics.
6.2. AC Characteristics (TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
±2% at 2.4V~5.5V
Min.
Typ.
Max.
IOSC Frequency
FOSC
24.5×(1-2%)
24.5
24.5×(1+2%)
MHz
6.3. DC Characteristics (TA = 25℃)
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Operating Voltage
Operating Current
VDD
IOP
VLVR
-
-
5.5
V
SYSCLK= 24.5MHz @ 5.0V,
no load
-
10.0
mA
Standby Current
Input High Level
ISTBY
VIH
-
-
-
5.0
uA
V
VDD = 5.5V
0.7*VDD
-
0.3*VDD
-
VDD = 5.0V(with Schmitt trigger)
VDD = 5.0V(with Schmitt trigger)
IOH = -8mA at VDD = 5.0V
IOL = 20mA at VDD = 5.0V
VDD = 5.0V
Input Low Level
VIL
-
-
V
Output High Level
VOH
VOL
0.8*VDD
-
V
Output Low Level
-
-
0.2*VDD
70
V
Input Pull High Resistor 1
Input Pull High Resistor 1
Low Voltage Reset 1
Low Voltage Reset 2
RPH1
RPL1
VLVR1
VLVR2
30
50
50
2.2
3.9
KΩ
KΩ
V
30
70
VDD = 5.0V
2.2×(1-5%)
3.9×(1-5%)
2.2×(1+5%)
3.9×(1+5%)
CONGIF_BYTE[5]=1
CONGIF_BYTE[5]=0
V
6.4. ADC Characteristics (TA = 25℃)
6.4.1. 12 bit mode
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Operating Voltage
ADC Input Voltage Range
ADC Clock Period
Input Channel
VDD
VADCIN
TAD
VLVR
-
5.5
VDD
-
V
V
0
0.3265
-
-
-
-
us
ADCLKmax=24.5MHz/8
8
channel
Bit
Resolution
12
10
-
No Missing Code
bits
us
ADC Conversion Time
Integral Linearity Error
Differential Linearity Error
TCON
EINL
5.224
-
ADCLK*16@ADCFG[1:0]=2’b00
-
-
±2
-1~+2
±3
LSB
LSB
EDNL
-1~+3
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GPM8F3132A/3116A/3108A
6.4.2. 8 bit mode
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Operating Voltage
ADC Input Voltage Range
ADC Clock Period
Input Channel
VDD
VADCIN
TAD
VLVR
-
5.5
VDD
-
V
V
0
0.3265
-
-
-
us
ADCLKmax=24.5MHz/8
-
8
channel
Bit
Resolution
8
8
No Missing Code
bits
us
ADC Conversion Time
Integral Linearity Error
Differential Linearity Error
TCON
EINL
3.918
-
-
ADCLK*12@ADCFG[1:0]=2’b00
-
-
±0.5
±0.25
±1
LSB
LSB
EDNL
±0.5
6.5. OP and Comparators Characteristics (TA = 25℃)
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Operating Voltage
OP Input Offset
Built-in Resistor
VDD
Vin_op
R110K
VLVR
-
-
7
5.5
-
V
mV
KΩ
VDD=5.0V
VDD=5.0V
88
110
132
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7. PACKAGE INFORMATION
7.1. Ordering Information
Product Number
Package Type
GPM8F3132A – QL01x
GPM8F3116A – QL01x
Halogen Free Package
Halogen Free Package
Halogen Free Package
GPM8F3108A – QL01x
Note1: Package form number (x = 1 - 9, serial number).
7.2. Package Information
7.2.1. LQFP 44
Millimeter
Symbol
Min.
-
Nom.
Max.
1.60
0.15
1.45
0.16
A
A1
A2
c1
D
-
0.05
1.35
0.09
-
1.40
-
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.80 BSC
0.37
D1
E
E1
e
b
0.30
0.45
0.45
0.75
L
0.60
L1
θ°
1.00 REF
3.5°
0°
7°
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GPM8F3132A/3116A/3108A
8.DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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Preliminary
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9. REVISION HISTORY
Date
Revision #
Description
Page
Nov. 07, 2014
0.6
1. Modify Figure 5-45.
114
2. Modify UART mode2 spec.
3. Add FLASHCON register description.
Modify electrical characteristics
Dec. 01, 2010
Oct. 21, 2010
Aug. 23, 2010
0.4
0.3
0.2
114
104
56
Add body GPM8F3116A and GPM8F3108A.
1. Modify the Table 5-75 CCEN register.
2. Modify the Figure 5-46 Built-in three comparators.
3. Modify the Figure 5-47 Built-in OP and comparator.
Original
81
83
Jul. 07, 2010
0.1
99
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