GPR25L322B-LS13x [GENERALPLUS]
32M-BIT [x1 / x2] CMOS SERIAL FLASH;
| 型号： | GPR25L322B-LS13x |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 32M-BIT [x1 / x2] CMOS SERIAL FLASH |
| 文件： | 总38页 (文件大小：850K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPR25L322B
32M-BIT [x1 / x2] CMOS SERIAL FLASH
Jun. 06, 2014
Version 1.3
GENERALPLUS TECHNOLOGY INC. reserves the rig ht to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPR25L322B
Table of Contents
PAGE
1. FEATURES.................................................................................................................................................................................................. 4
1.1. GENERAL .............................................................................................................................................................................................. 4
1.2. PERFORMANCE...................................................................................................................................................................................... 4
1.3. SOFTWARE FEATURES ........................................................................................................................................................................... 4
1.4. HARDWARE FEATURES .......................................................................................................................................................................... 4
2. GENERAL DESCRIPTION.......................................................................................................................................................................... 5
3. PIN CONFIGURATIONS ............................................................................................................................................................................. 5
3.1. 8-PIN SOP (209MIL) ............................................................................................................................................................................. 5
4. PIN DESCRIPTION...................................................................................................................................................................................... 5
5. BLOCK DIAGRAM ...................................................................................................................................................................................... 6
6. MEMORY ORGANIZATION ........................................................................................................................................................................ 7
7. DEVICE OPERATION ................................................................................................................................................................................. 8
8. DATA PROTECTION................................................................................................................................................................................... 9
9. HOLD FEATURE....................................................................................................................................................................................... 11
10.COMMAND DESCRIPTION ...................................................................................................................................................................... 12
10.1.WRITE ENABLE (WREN)...................................................................................................................................................................... 13
10.2.WRITE DISABLE (WRDI) ...................................................................................................................................................................... 13
10.3.READ STATUS REGISTER (RDSR)........................................................................................................................................................ 13
10.4.WRITE STATUS REGISTER (WRSR)...................................................................................................................................................... 14
10.5.READ DATA BYTES (READ)................................................................................................................................................................. 15
10.6.READ DATA BYTES AT HIGHER SPEED (FAST_READ) ......................................................................................................................... 15
10.7.DUAL OUTPUT MODE (DREAD) ........................................................................................................................................................... 15
10.8.SECTOR ERASE (SE)........................................................................................................................................................................... 15
10.9.BLOCK ERASE (BE) ............................................................................................................................................................................. 15
10.10. CHIP ERASE (CE) ........................................................................................................................................................................... 15
10.11. PAGE PROGRAM (PP) ..................................................................................................................................................................... 16
10.12. DEEP POWER-DOWN (DP)............................................................................................................................................................... 16
10.13. RELEASE FROM DEEP POWER-DOWN (RDP), READ ELECTRONIC SIGNATURE (RES)......................................................................... 16
10.14. READ IDENTIFICATION (RDID) ......................................................................................................................................................... 16
10.15. READ ELECTRONIC MANUFACTURER ID & DEVICE ID (REMS).......................................................................................................... 17
10.16. ENTER SECURED OTP (ENSO)....................................................................................................................................................... 17
10.17. EXIT SECURED OTP (EXSO) .......................................................................................................................................................... 17
10.18. READ SECURITY REGISTER (RDSCUR)........................................................................................................................................... 17
10.19. WRITE SECURITY REGISTER (WRSCUR)......................................................................................................................................... 18
10.20. READ SFDP MODE (RDSFDP)........................................................................................................................................................ 18
11.POWER-ON STATE .................................................................................................................................................................................. 19
11.1.INITIAL DELIVERY STATE ...................................................................................................................................................................... 19
12.ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 20
12.1.ABSOLUTE MAXIMUM RATINGS............................................................................................................................................................. 20
12.2.CAPACITANCE TA = 25°C, F = 1.0 MHZ................................................................................................................................................ 20
12.3.DC CHARACTERISTICS......................................................................................................................................................................... 21
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GPR25L322B
12.4.AC CHARACTERISTICS......................................................................................................................................................................... 22
12.5.TIMING ANALYSIS................................................................................................................................................................................. 23
13.OPERATING CONDITIONS ...................................................................................................................................................................... 34
13.1.AT DEVICE POWER-UP AND POWER-DOWN........................................................................................................................................... 34
14.ERASE AND PROGRAMMING PERFORMANCE.................................................................................................................................... 35
14.1.DATA RETENTION ................................................................................................................................................................................ 35
14.2.LATCH-UP CHARACTERISTICS............................................................................................................................................................... 35
15.PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 36
15.1.ORDERING INFORMATION ..................................................................................................................................................................... 36
15.2.PACKAGE INFORMATION....................................................................................................................................................................... 36
15.2.1. Package Outline for SOP 8L (209MIL)............................................................................................................................... 36
16.DISCLAIMER............................................................................................................................................................................................. 37
17.REVISION HISTORY................................................................................................................................................................................. 38
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GPR25L322B
32M-BIT [x 1/ x 2] CMOS SERIAL FLASH
1. FEATURES
1.1. General
•
•
Typical 100,000 erase/program cycles
20 years of data retention
•
Single Power Supply Operation
1.3. Software Features
- 2.7 to 3.6 volt for read, erase, and program operations
Serial Peripheral Interface compatible -- Mode 0 and Mode 3
•
Input Data Format
•
•
- 1-byte Command code
33,554,432 x 1 bit structure or 16,777,216 x
Output mode) structure
2 bits (Dual
•
Advanced Security Features
- Block lock protection
•
•
•
1024 Equal Sectors with 4K byte each
- Any Sector can be erased individually
64 Equal Blocks with 64K byte each
- Any Block can be erased individually
Program Capability
The BP3~BP0 status bit defines the size of the area to
software protection against program and erase instructions
- Additional 512 bits secured OTP for unique identifier
Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
be
•
- Byte base
- Automatically programs and verifies data at selected page
by an internal algorithm t hat automatically times the
program pulse widths (Any page to be programmed should
have page in the erased state first)
- Page base (256 bytes)
•
•
Latch-up protected to 100mA from -1V to VCC +1V
GPR25L322B is compatible with MX25L3206E
•
•
Status Register Feature
1.2. Performance
Electronic Identification
•
High Performance
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- Fast access time: 86MHz serial clock
- Serial clock of Dual Output mode : 80MHz
- REMS commands for 1- byte manufacturer ID a nd 1-byte
device ID
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page
- Byte program time: 9us (typical)
- Fast erase time: 60ms(typ.) /sector ; 0.7s(typ.) /block
Low Power Consumption
1.4. Hardware Features
•
y
PACKAGE
- Low active read current: 25mA(max.) at 86MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Standby current: 40uA (max.)
- 8-pin SOP (209mil)
- RoHS Compliant
- Deep power-down mode 5uA (typical)
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2. GENERAL DESCRIPTION
3. PIN CONFIGURATIONS
3.1. 8-PIN SOP (209mil)
The device feature a serial per ipheral interface and sof tware
protocol allowing operation on a simple 3-wire bus. The three
bus signals are a clock input (SCLK), a serial data input (SI), and
a serial data output (SO). Serial access to the device is enabled
by CS# input.
When it is in Dual Output read mode, the SI and SO pins become
SIO0 and SIO1 pins for data output.
The device provides sequential read operation on whole chip.
After program/erase command i s issued, auto program/erase
algorithms which program/ erase and verify the specified page or
sector/block locations will be ex ecuted. Progra m command is
executed on byte basis, or p age basis, or word basis for erase
command is executes on sector, or block, or whole chip basis.
To provide user with ease of interface, a status register is
included to indicate the st atus of the chip. The status read
command can be issued to detect completion status of a program
or erase operation via WIP bit.
4. PIN DESCRIPTION
Symbol
Description
CS#
Chip Select
Serial Data Input (for 1 x I/O)/ Serial Data Input
& Output (for Dual Output mode)
Serial Data Output (for 1 x I/O)/ Serial Data
Output (for Dual Output mode)
Clock Input
SI/SIO0
SO/SIO1
Advanced security features enhance the protection and security
functions, please see security features section for more details.
When the device is not in operation and CS# is h igh, it is put in
standby mode.
SCLK
WP#
Write protection
Hold, to pause the device w ithout deselecting
the device
HOLD#
The device relia bly stores memory contents even after typical
100,000 program and erase cycles.
VCC
GND
+ 3.3V Power Supply
Ground
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GPR25L322B
5. BLOCK DIAGRAM
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GPR25L322B
6. MEMORY ORGANIZATION
Table1. Memory Organization
Block
Sector
1023
:
Address Range
3FF000h
: :
3FFFFFh
63
62
1008
1007
:
3F0000h
3EF000h
: :
3F0FFFh
3EFFFFh
992
3E0000h
3E0FFFh
:
:
:
:
:
:
:
:
15
:
00F000h
: :
00FFFFh
3
2
1
0
003000h
002000h
001000h
000000h
003FFFh
002FFFh
001FFFh
000FFFh
0
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7. DEVICE OPERATION
1. Before a command is issued,
status register should be
5. For the follow ing instructions: RDID, RDSR, RDSCUR,
READ, FAST_READ, DREAD, RES, and REM S the shif t-
checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this LS I, this LSI
becomes standby mode and keeps the standby mode until
next CS# falling edge. In standby mode, SO pin of this LSI
ed-in instruction sequence is follow ed by
a data-out
sequence. After any bit of dat a being shifted out, the CS#
can be high. For the following instructions: WREN, WRDI,
WRSR, SE, BE, CE, PP , RDP, DP, ENSO, EXSO, and
WRSCUR, the CS# must go high exactly at the b yte
boundary; otherwise, the instruction will be rejected and not
executed.
should be High-Z. The CS# falling t
tCHCL spec.
ime needs to follow
3. When correct command is inp utted to this L SI, this LSI
becomes active mode and keeps the active mode until next
CS# rising edg e. The CS# rising time needs to follow
tCLCH spec.
6. During the progress of Write Status Register, Program, Erase
operation, to access the memor y array is neglected and not
affect the current operation of Write Status Register, Program,
Erase.
4. Input data is latched on the rising edge of Serial Clock(SCLK)
and data shifts out on the falling edge of S CLK. The
difference of Serial mode 0 and mode 3 is shown in Figure 1.
Figure1. Serial Modes Supported
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase.
The combination of CPOL bit and CPHA bit decides which Serial mode is supported.
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8. DATA PROTECTION
The device is designed to of fer protection against accidental
erasure or programming caused by spurious system level signals
that may exist during po wer transition. During po wer up the
device automatically resets the state machine in the standby mode.
In addition, with its control register architecture, alteration of the
memory contents only occurs after successful completion of
specific command sequences. T he device also incorporates
several features to prevent inadvertent write cycles resulting from
VCC power-up and power-down transition or system noise.
-
-
Block Erase (BE) command completion
Chip Erase (CE) command completion
•
•
Deep Power Down Mode: By entering deep power down mode,
the flash device also is under protected from writing all
commands except Release fro m deep po wer down mode
command (RDP) and Read Electronic Sig nature command
(RES).
Advanced Security Features: there are some pr otection and
security features which protect content from inadvertent write
and hostile access.
•
•
Valid command length checking: The command le ngth will be
checked whether it is at b yte base and comple ted on byte
boundary.
I. Block lock protection
- The Software Protected Mode (SPM):
Write Enable (WREN) command: WREN command is required
to set the Write Enable Latch bit (WEL) before other command
to change data. The WEL bit will return to reset stage under
following situation:
GPR25L322B: use (BP3, BP2, B P1, BP0) bits to allow part of
memory to be p rotected as rea d only. The protected area
definition is sho wn as table of "Protected Area Sizes", the
protected areas are more flexible which may protect various
area by setting value of BP0-BP3 bits.
-
-
-
-
-
Power-up
Write Disable (WRDI) command completion
Write Status Register (WRSR) command completion
Page Program (PP) command completion
Sector Erase (SE) command completion
Please refer to table of "protected area sizes".
- The Hardware Protected Mode (HPM) uses WP# to protect
the GPR25L322B: BP3-BP0 bits and SRWD bit.
Table2. Protected Area Sizes
Status bit
BP1
Protect Level
BP3
0
BP2
0
BP0
0
32Mb
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0 (none)
0
0
1
1 (1block, block 63rd)
0
0
0
2 (2blocks, block 62nd-63rd)
3 (4blocks, block 60th-63rd)
4 (8blocks, block 56nd-63rd)
5 (16blocks, block 48nd-63rd)
6 (32blocks, block 32nd-63rd)
7 (64blocks, all)
0
0
1
0
1
0
0
1
1
0
1
0
0
1
1
1
0
0
8 (64blocks, all)
1
0
1
9 (32blocks, block 0th-31st)
10 (48blocks, block 0th-47th)
11 (56blocks, block 0th-55th)
12 (60blocks, block 0th-59th)
13 (62blocks, block 0th-61st)
14 (63blocks, block 0th-62nd)
15 (64blocks, all)
1
0
0
1
0
1
1
1
0
1
1
1
1
1
0
1
1
1
II. Additional 512 bits secured OTP for unique identifier: to
provide 512 bit s one-time pr ogram area fo r setting device
unique serial number - Which ma y be set by factory or system
customer. Please refer to Table 3. 512 bits secured OTP
definition.
- Security register bit 0 ind icates whether the chip is locked by
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GPR25L322B
factory or not.
set customer lock-down bit1 as " 1". Please refer to table of
"security register definition" for security register bit definition
and Table 3 "512 bits secured OTP de finition" for address
range definition.
- To program the 512 bits secured OTP by entering 512 bits
secured OTP mode (with ENSO command), and going through
normal program procedure, and then exiting 512 bits secured
OTP mode by writing EXSO command.
- Note: Once lock-dow n whatever by factory or customer, it
cannot be changed any more. While in 512 bits secured OTP
mode, array access is not allowed.
- Customer ma y lock-down the customer lockable secured
OTP by writing WRSCUR(write security register) command to
Table3. 512 bit Secured OTP Definition
Address Range
xxxx00~xxxx0F
xxxx10~xxxx3F
Size
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
128-bit
384-bit
Determined by customer
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9. HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with
the device. The HOLD feature will not stop the operation of write
status register, programming, or erasing in progress.
(SCLK) signal is being low (if Seri al Clock signal is not being low,
HOLD operation will not start until Serial C lock signal being low).
The HOLD condition ends on the rising edge of HOLD# pin signal
while Serial Clock(SCLK) signal is being low (if Serial Clock signal
is not being low, HOLD operation will not end until Serial C lock
being low), see Figure 2.
The operation of HOLD requires Chip Select(CS#) keeping low
and starts on falling edge of HO LD# pin signal while Serial Clock
Figure2. Hold Condition Operation
The Serial Data Output (SO) is high impedanc e, both Serial Dat a Input (SI) a nd Serial Clock (SCLK) are do n't care during the HOLD
operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication
with chip, the HOLD# must be at high and CS# must be at low.
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GPR25L322B
10. COMMAND DESCRIPTION
Table4. Command Definition
Command
(byte)
WREN (write WRDI (write WRSR (write RDID
RDSR (read READ (read FAST READ
enable)
disable)
status
(read
status
data)
(fast
read
register)
identification)
register)
data)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
06 (hex)
04 (hex)
01 (hex)
9F (hex)
05 (hex)
03 (hex)
AD1
0B (hex)
AD1
AD2
AD2
AD3
AD3
Dummy
sets
the resets
the to write ne w outputs JEDEC to read out
ID: 1-byte the values of
enable latch enable latch status register Manufacturer ID the status goes high
n bytes read n bytes read
(WEL) write (WEL) write values to the
out until CS#
out until CS#
goes high
bit
bit
& 2-byte Device register
ID
Command
(byte)
RES
(read REMS (read DREAD
SE
(sector BE
erase)
(block CE
erase)
(chip PP
(page
electronic ID)
electronic
(Double
erase)
program)
manufacturer
& device ID)
Output Mode
command)
1st byte
AB (hex)
90 (hex)
3B (hex)
20 (hex)
52
or
D8 60 or C7
(hex)
02 (hex)
(hex)
AD1
AD2
AD3
2nd byte
3rd byte
4th byte
5th byte
Action
x
x
x
x
AD1
AD1
AD2
AD3
AD1
AD2
AD3
x
AD2
ADD (Note 1)
AD3
Dummy
to read out
output
the
n
bytes read to erase the
out by Dual selected
Output until sector
to erase t he to
erase to
program
1-byte Device Manufacturer
ID ID & Device ID
selected
block
whole chip
the selected
page
CS# goes high
Command
(byte)
RDSCUR (read WRSCUR
(write ENSO
(enter EXSO
(exit DP (Deep power RDP
(Release
deep
security
register)
security register)
secured OTP)
secured OTP)
down)
from
power down)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
2B (hex)
2F (hex)
B1 (hex)
C1 (hex)
B9 (hex)
AB (hex)
to read value
to set the lock-down bit to enter the 512
to exit the 512 enters
secured bits secured power
OTP mode mode
deep release
down deep
from
of
security as
"1" (once
lock-down, cannot be
updated)
bits
power
register
OTP mode
down mode
Note1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note2: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode.
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10.1. Write Enable (WREN)
progress. When WIP bit sets to 1, w hich means the device is
busy in program/erase/write status register progress. When WIP
bit sets to 0, w hich means th e device is not in progress of
program/erase/write status register cycle.
The Write Enable (WREN) instru ction is for settin g Write Enable
Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and
WRSR, which are intended to change the device content, should
be set every time after the WREN instruction setting the WEL bit.
The sequence is shown as Figure 11.
WEL bit. The Write Enable Latch (WEL) bit,
a volatile bit,
indicates whether the device is se t to internal write enable latch.
When WEL bit sets to 1, w hich means the internal w rite enable
latch is set, the device can acc
ept program/erase/write status
10.2. Write Disable (WRDI)
register instruction. When WEL bit set s to 0, which means no
internal write enable latch; the device w ill not accept
The Write Disable (WRDI) instruction is for resetting W rite Enable
Latch (WEL) bit.
program/erase/write
status
register instruction. The
The sequence is shown as Figure 12.
The WEL bit is reset by following situations:
- Power-up
program/erase command will be ignored and not af fect value of
WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3-BP0) bit s,
non-volatile bits, indicate the protected area (as defined in table 2)
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
of the device to against the program/e
rase instruction w ithout
hardware protection mode being set. To write the Block Protect
(BP3-BP0) bits requires the W rite Status Register (WRSR)
instruction to be executed. Those bits define the protected area
of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase (B E) and Chip E rase (CE) instructions (only if all
Block Protect bits set to 0, the CE instruction can be executed).
SRWD bit. The Status Register W rite Disable (SR WD) bit,
non-volatile bit, is operated to gether with Write Protection (WP#)
pin for providin g hardware protection mode. The hard ware
protection mode requires SRWD sets to 1 and WP# pin signal is
low stage. In the hardware protection mode, t he Write Status
Register (WRSR) instruction is no longer accepted for execution
and the SRWD bit and Block Protect bits (BP3-BP0) are read only.
10.3. Read Status Register (RDSR)
The RDSR instruction is for rea ding Status Register Bits. The
Read Status Register can be read at an
y time (even in
program/erase/write status register condition) an d continuously.
It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status
register operation is in progress.
The sequence is shown as Figure 13.
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates
whether the device is busy in program/erase/write status register
Status Register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SRWD (status
register write
protect)
BP3
BP2
BP1
BP0
WEL
(write enable
latch)
WIP
0
(level of
(level of
(level of
(level of
(write in
protected block) protected block) protected block) protected block)
progress bit)
1=write
1=write enable
0=not write
enable
1=status register
write disable
operation
0=not in write
operation
volatile bit
0
0
(note 1)
(note 1)
(note 1)
(note 1)
Non-volatile bit
Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit
volatile bit
Note1: see the table "Protected Area Size".
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10.4. Write Status Register (WRSR)
The WRSR instruction is for
changing the v alues of S tatus
The WRSR instruction has no e ffect on b6, b1, b0 of the st atus
register.
Register Bits. Before sendin g WRSR instru ction, the W rite
Enable (WREN) instruction must be decoded and executed to set
the Write Enable Latch (WEL ) bit in ad vance. The WRSR
instruction can change the value of Block Protect (BP3-BP0) bits
to define the pr otected area of memory (as shown in t able 1).
The WRSR also can set or reset the Status Register Write Disable
(SRWD) bit in accordance with Write Protection (WP#) pin signal.
The WRSR instruction cannot be executed onc e the Hard ware
Protected Mode (HPM) is entered.
The CS# must go high exactly at the b yte boundary; otherwise,
the instruction will be rejected and not e xecuted. The self-timed
Write Status Register cycle time (tW) is initiated as soon as Chip
Select (CS#) goes high. The Write in Progress (WIP) bit still can
be check out during the Write Status Register cycle is in progress.
The WIP sets 1 during the tW timing, and sets 0 when Write Status
Register Cycle is completed, and the Write Enable Latch (WEL) bit
is reset.
The sequence is shown as Figure 14.
Table 5. Protection Modes
Mode
Status register condition
protection Status register can be written in (WEL WP#=1 and S RWD bit=0, o r
bit is set to "1") and the S RWD, WP#=0 and S RWD bit=0, o r
WP# and SRWD bit status
Memory
Software
The protected area cannot
be program or erase.
mode (SPM)
BP3-BP0 bits can be changed
protection The SRWD, BP3-BP0 of status register
bits cannot be changed
WP#=1 and SRWD=1
Hardware
The protected area cannot
be program or erase.
WP#=0, SRWD bit=1
mode (HPM)
Note:
Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status
Register even if the WEL bit has previously been set. It is rejected to write
the Status Register and not be executed.
As defined by the values in the Block Protect (BP3-BP0) bits of the Status
Register, as shown in Table 2.
As the above table showing, the summary of the Software Protected Mode
(SPM) and Hardware Protected Mode (HPM).
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP# is low (or WP# is low before SRWD
bit=1), it enters the hardware protected mode (HPM). The da ta of the
protected area is protected by software protected mode by BP3-BP0 and
hardware protected mode by the WP# to against data modification.
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP# is low or high, the WREN instruction
may set the WEL bit and can change the values of SRWD, BP3-BP0. The
protected area, which is defined by BP3-BP0 is at software protected mode
(SPM).
Note: to exit the hardware protected mode requires WP# driving high once
the hardware protected mode is entered.
If the WP# pin is permanently connected to high, the hardware protected
mode can never be ente red; only can use software protected mode v ia
BP3-BP0.
- When SRWD bit=1 and WP# is high, the WREN instruction may set the
WEL bit can change the values of SRWD, BP3-BP0. T he protected area,
which is defined by BP3-BP0 is at software protected mode (SPM).
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10.5. Read Data Bytes (READ)
sector. A Write Enable (WREN) instruction must execute to set
the Write Enable Latch (WEL) bit before sending t he Sector Erase
(SE). Any address of the sector (see table 1 ) is a valid address
for Sector Erase (SE) instruction. The CS# must go high exactly
at the b yte boundary (the latest eighth of addr ess byte been
latched-in); otherwise, the instruction w ill be rej ected and not
executed.
The read instru ction is for reading data out. The address is
latched on rising edge of SC LK, and data shifts o ut on the f alling
edge of SCLK at a maximum frequenc y fR. T he first address
byte can b e at any location. The ad dress is automatically
increased to th e next higher address after each byte data is
shifted out, so t he whole memory can be read out at a single
READ instruction. The address counter rolls over to 0 w hen the
highest address has been reached.
Address bits [Am-A12] (Am is the most significant address) select
the sector address.
The sequence is shown as Figure 18.
The sequence is shown as Figure 15.
The self-timed Sector Erase Cycle time (tSE) is i nitiated as soon
as Chip Select (CS#) goes high. The Write in Progress (WIP) bit
still can be check out during the Sect or Erase cycle is in progress.
The WIP sets 1 during the tSE timing, and sets 0 w hen Sector
Erase Cycle is completed, and the Write Enable Latch (WEL) bit is
reset. If the page is protected by BP3-BP0 bits, the Sector Erase
(SE) instruction will not be executed on the page.
10.6. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The
address is latched on rising edge of SCLK, and data of each bit
shifts out on the falling edge of SCLK at a maximum frequency fC.
The first addres s byte can be a t any location. The address is
automatically increased to the next higher address after each byte
data is sh ifted out, so the w hole memory can be read out at a
single FAST_READ instruction. The address counter rolls over
to 0 when the highest address has been reached.
10.9. Block Erase (BE)
The Block Eras e (BE) instruction is for e rasing the da ta of the
chosen block to be "1". The in
struction is u sed for 64K-b yte
The sequence is shown as Figure 16.
sector erase operation. A Write Enable (WREN) instruction must
execute to set t he Write Enable Latch (WEL) bit before sending
the Block Erase (BE). Any address of the block (see table 1) is a
valid address for Block Erase (BE) instruction. The CS# must go
high exactly at the byte boundary (the latest eighth of address byte
been latched-in); otherwise, the instruction will be rejected and not
executed.
While Program/Erase/Write Status Register cycle is in prog ress,
FAST_READ instruction is rejected w ithout any impact on the
Program/Erase/Write Status Register current cycle.
10.7. Dual Output Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash
in read mode. The address is latched on rising edge of SCLK,
and data of every two bits(interleave on 1I/2O pins) shift out on the
falling edge of SCLK at a maximum frequenc y fT. The first
The sequence is shown as Figure 19.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as
Chip Select (CS#) goes high. The Write in Progress (WIP) bit still
can be check out during the Se ctor Erase cycle is in progress.
The WIP sets 1 during the tBE timing, and sets 0 w hen Sector
Erase Cycle is completed, and the Write Enable Latch (WEL) bit is
reset. If the page is protected b y BP3-BP0 bits, the Block Erase
(BE) instruction will not be executed on the page.
address byte can be at an
y location. The address is
automatically increased to the next higher address after each byte
data is sh ifted out, so the w hole memory can be read out at a
single DREAD instruction.
The address counter rolls over to 0 when the highest address has
been reached. Once writing DREAD instruction, the follo wing
address/dummy/data out will perform as 2-bit instead of previous
1-bit.
10.10. Chip Erase (CE)
The Chip Erase (CE) instruction is for e rasing the data of t he
whole chip to b e "1". A Write Enable (WREN) instruction must
execute to set t he Write Enable Latch (WEL) bit before sending
the Chip Erase (CE). Any address of the sector (see table 1) is a
valid address for Chip Erase (CE ) instruction. The CS# must go
high exactly at the byte boundary(the latest eighth of address byte
been latched-in); otherwise, the instruction will be rejected and not
executed.
The sequence is shown as Figure 17.
While Program/Erase/Write Status Register cycle is in prog ress,
DREAD instruction is rejected
without any impact on the
Program/Erase/Write Status Register current cycle.
The DREAD only perform read operation. Program/Erase /Read
ID/Read status....operation do not support DREAD throughputs.
10.8. Sector Erase (SE)
The sequence is shown as Figure 20.
The Sector Er ase (SE) instruction is for erasing the data of th
e
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as
chosen sector to be "1". The instruction is used for any 4K-byte
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Chip Select (CS#) goes high. The Write in Progress (WIP) bit still
can be check out during the Chip Erase cycle is in progress. The
WIP sets 1 during the tCE timing, and sets 0 w hen Chip Erase
Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
If the chip is protected b y BP3-BP0 bits, the C hip Erase (CE)
instruction will not be ex ecuted. It will be onl y executed when
BP3-BP0 all set to "0".
the ID being r eading out).
When Power-down, the de ep
power-down mode automatically stops, and when power-up, the
device automatically is in standby mode. For RDP instruction the
CS# must go high exactl y at the byte boundary (the latest eighth
bit of instruction code been latched-in); othe rwise, the instruction
will not ex ecuted. As soon as Chip Select (CS #) goes high, a
delay of tDP is required bef ore entering the Deep Power-down
mode and reducing the current to ISB2.
10.11. Page Program (PP)
10.13. Release from Deep Power-down (RDP), Read
Electronic Signature (RES)
The Page Program (PP) instruction is for pro gramming the
memory to be "0".
A Write E nable (WREN) instruction must
execute to set t he Write Enable Latch (WEL) bit before sending
the Page Program (PP). If the eight least significant address bits
(A7-A0) are not all 0, all transmitted data which goes beyond the
end of the current page are programmed from the start address if
The Release from Deep Pow
er-down (RDP) instruction is
terminated by driving Chip Select (CS#) High. When Chip Select
(CS#) is driven High, the device is put in the S tand-by Power
mode. If the device was not previously in the Deep Power-down
mode, the transition to the Stand-by Power mode is immediate. If
the device was previously in the Deep Power-down mode, though,
the transition to the Stand-by Power mode is delayed by tRES2,
and Chip Select (CS#) must remain High for at least tRES2(max),
as specified in Table 9. Once in the Stand-by Power mode, the
device waits to be selected, so that it can r eceive, decode and
execute instructions.
the same page (from the add
ress whose 8 least signif icant
address bits (A7-A0) are all 0). The CS# must keep during the
whole Page Program cycle. The CS# must go high exactly at the
byte boundary(the latest eighth of address b yte been latched-in);
otherwise, the instruction w ill be rejected and not ex ecuted. If
more than 256 bytes are sent t o the device, th e data of the last
256-byte is pro grammed at the request page and previous data
will be disregarded. If less than 256 bytes are sent to the device,
the data is pr ogrammed at the request address of the pag e
without effect on other address of the same page.
RES instruction is for reading out the old style of 8-bit Electronic
Signature, whose values are shown as table of ID Definitions.
This is not the same as RDID in struction. It is not recommended
The sequence is shown as Figure 21.
to use for new design. Fo
r new design, please use RDID
The self-timed Page Program Cycle time (tPP) is initiated as soon
as Chip Select (CS#) goes high. The Write in Progress (WIP) bit
instruction. Even in Deep power-down mode, the RDP and RES
are also allow ed to be e xecuted, only except the device is in
progress of pr ogram/erase/write cycle; there's no effect on the
current program/erase/write cycle in progress.
still can be ch eck out during the Page Pro
gram cycle is i n
progress. The WIP sets 1 during the tPP timing, and sets 0 when
Page Program Cycle is complet ed, and the Write Enable Latch
(WEL) bit is reset. If the page is protected b y BP3-BP0 bits, the
Page Program (PP) instruction will not be executed.
The sequence is shown in Figure 23 and Figure 24.
The RES instruction is ended by CS# goes high after the ID bee n
read out at least once. The ID outputs repeatedly if continuously
send the additional clock cycles on SCLK while CS# is at low. If
the device was not previously in Deep Power-down mode, the
device transition to standb y mode is immediate . If the device
was previously in Deep Po wer-down mode, th ere's a dela y of
tRES2 to transit to standby mode, and CS# must remain to high at
least tRES2(max). Once in the standb y mode, the device waits
10.12. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on
the minimizing the po wer consumption (to entering the Deep
Power-down mode), the standby current is reduc ed from ISB1 t o
ISB2). The Deep Po
wer-down mode requires the Deep
to be selected, so it can be
instruction.
receive, decod e, and execute
Power-down (DP) instruction to enter, du
Power-down mode, the device is not a
ring the Deep
ctive and a ll
The RDP instruction is for releasing from Dee p Power Down
Mode.
Write/Program/Erase instruction are ignored . W hen CS# goes
high, it's only in standby mode not deep power-down mode. It's
different from Standby mode.
10.14. Read Identification (RDID)
The sequence is shown as Figure 22.
Once the DP instruction is set, all instruction will be ignored except
the Release f rom Deep Po wer-down mode (RDP) and Read
Electronic Signature ( RES) instruction. (those in structions allow
The RDID instruction is for readi ng the manufacturer ID of 1-byte
and followed by Device ID of 2-byte. The Manufacturer ID and
Device ID are listed as table of "ID Definitions".
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The sequence is shown as Figure 25.
Power-down/Device ID instruction. The instruction is initiated by
While Program/Erase operation is in progress, it will not decode
the RDID instruction, so ther e's no effect on the c ycle of
program/erase operation which is currentl y in progress. When
CS# goes high, the device is at standby stage.
driving the CS# pin low
and shift the instruction code "90h"
followed by two dummy bytes and one b ytes address (A7~A0).
After which, the Manufacturer ID and the Device ID are shifted out
on the falling edge of SCLK with most significant bit (MSB) first as
shown in Figure 26. The Device ID values are listed in Table of
ID Definitions. If the one-byte address is initially set to 01h, then
the device ID w ill be read first and then fo llowed by the
Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is
completed by driving CS# high.
10.15. Read Electronic Manufacturer ID & Device ID
(REMS)
The REMS inst ruction is an alternative to the
Release from
Power-down/Device ID instruction that p rovides both the JEDEC
assigned manufacturer ID and the specific device ID.
The REMS ins truction is ver y similar to the Release from
Table6. ID Definitions
Command Type
GPR25L322B
manufacturer ID
RDID Command
memory type
memory density
16
C2
20
electronic ID
15
RES Command
manufacturer ID
device ID
15
REMS Command
C2
10.16. Enter Secured OTP (ENSO)
10.18.Read Security Register (RDSCUR)
The ENSO instruction is for entering the a dditional 512 bits
secured OTP m ode. The additional 512 bits secured OTP is
independent from main arra y, which may use to store unique
serial number for s ystem identifier. After entering the Secured
OTP mode, and then follow standard read or program, procedure
The RDSCUR instruction is for reading the value of Securit
y
Register bits. The Read Security Register can be read at any
time (even in p rogram/erase/write status register/ write security
register condition) and continuously.
The sequence is shown as Figure 27.
to read out the data or update data. The Secured OTP dat
cannot be updated again once it is lock-down.
a
The definition of the Security Register bits is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows
the chip is locked by factory before ex- factory or not. When it is
"0", it indicates non- factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR
instruction, the LDSO bit may be set to "1" for customer lock-down
purpose. Ho wever, once the bit is set to "1" (lock-down), the
LDSO bit and th e 512 bits Secured OTP a rea cannot be update
Please note that WRSR/WRSCUR commands are not acceptable
during the access of secure OTP region, once security OTP is lock
down, only read related commands are valid.
10.17. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 512 bits secured
OTP mode.
any more. While it is in 512 bits secured OTP mode, arra
access is not allowed.
y
Table7. Security Register Definition
bit7
bit6
bit5
bit4
x x
bit3
bit2
x
bit1
bit0
Secured
indicator bit
LDSO (indicate if
lock-down
OTP
x
x
x
reserved
reserved
reserved
reserved
reserved
reserved
0 = not lockdown
1 = lock-down
(cannot
0 = non-factory lock
1 = factory lock
program/erase OTP)
non-volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
17
volatile bit
non-volatile bit
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10.19. Write Security Register (WRSCUR)
LDSO bit is set to "1", the Secured OTP area cannot be updated
any more.
The WRSCUR instruction is for changing the val ues of Securit y
Register Bits. Unlike write status register, the WREN instruction
is not required before sending WRSCUR instruction. The
The CS# must go high e xactly at the bou ndary; otherwise, the
instruction will be rejected and not executed.
The sequence is shown as Figure 28.
WRSCUR instruction may change the values of bit1 (LDSO bit) for
customer to lock-down the 512 bits Secured OTP area. Once the
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11. POWER-ON STATE
The device is at below states when power-up:
VCC minimum level, the correct operation is n
ot guaranteed.
The read, write, erase, and program command should be sent
after the below time delay:
-
-
Standby mode (please note it is not deep power-down mode)
Write Enable Latch (WEL) bit is reset
-
tVSL after VCC reached VCC minimum level
The device m ust not be selected during pow
er-up and
The device can accept read co mmand after VCC reached V CC
minimum and a time delay of tVSL.
power-down stage unless the VCC achieves below correct level:
-
-
VCC minimum at po wer-up stage and then af ter a dela y of
Please refer to the figure of "power-up timing".
tVSL
GND at power-down
Note:
Please note that a pull-up resistor on CS# may ensure a safe and
proper power-up/down level.
-
To stabilize the VCC level, th e VCC rail decoupled b y a
suitable capacitor close to packa ge pins is
recommended.(generally around 0.1uF)
An internal power-on reset (POR) circuit may protect the device
from data corruption and inadvertent data change during power up
state.
11.1. Initial Delivery State
The device is delivered w ith the memory array erased: all bits are
set to 1 (each byte contains FFh).
For further protection on the device, if the VCC does not reach the
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12. ELECTRICAL SPECIFICATIONS
12.1. Absolute Maximum Ratings
Rating
Value
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
Industrial grade
-40°C to 85°C
-55°C to 125°C
-0.5V to 4.6V
-0.5V to 4.6V
-0.5V to 4.6V
VCC to Ground Potential
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and
functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot VSS to -2.0V and VCC to +2.0V for periods up to 20ns, see Figure 3 and 4.
Figure 3.Maximum Negative Overshoot Waveform
Figure 4. Maximum Positive Overshoot Waveform
12.2. Capacitance TA = 25°C, f = 1.0 MHz
Symbol
CIN
Parameter
Min.
Typ.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
Output Capacitance
-
-
-
-
6
8
COUT
pF
VOUT = 0V
Figure5. Input Test Waveforms and Measurement Level
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Figure6. Output Loading
12.3. DC Characteristics
Symbol
Parameter
Notes
Min.
Typ.
Max.
Units
Test Conditions
VCC = VCC Max,
ILI
Input Load Current
1
-
-
± 2
uA
VIN = VCC or GND
VCC = VCC Max,
ILO
Output Leakage Current
1
-
-
± 2
uA
VIN = VCC or GND
VIN = VCC or GND, CS# = VCC
VIN = VCC or GND, CS# = VCC
f=86MHz
ISB1
ISB2
VCC Standby Current
1
-
-
-
-
40
20
uA
uA
Deep Power-down Current
5
25
20
mA
mA
fT=80MHz
(2
x I/O re
ad)
SCLK=0.1VCC/0.9VCC, SO=Open
f=66MHz, SCLK=0.1VCC/0.9VCC,
SO=Open
ICC1
VCC Read
1
-
-
f=33MHz, SCLK=0.1VCC/0.9VCC,
SO=Open
10
20
20
mA
mA
mA
ICC2
ICC3
VCC Program Current (PP)
VCC Write Status Register
(WRSR) Current
1
-
-
-
-
-
Program in Progress, CS# = VCC
Program
status
register in
progress, CS#=VCC
VCC Sector Er ase Current
(SE)
ICC4
ICC5
1
1
-
-
-
-
20
20
mA
mA
Erase in Progress, CS#=VCC
Erase in Progress, CS#=VCC
VCC Chip Era se Current
(CE)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-
-
-
-
-0.5
0.7VCC
-
-
-
-
-
0.3VCC
V
V
V
V
VIH
VOL
VCC+0.4
0.4
-
IOL = 1.6mA
IOH = -100uA
VOH
VCC-0.2
Notes:
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Not 100% tested.
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12.4. AC Characteristics
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI, RDID, RDSR,
WRSR
fSCLK
fC
DC
-
86
MHz
fRSCLK
fTSCLK
fR
fT
Clock Frequency for READ instructions
Clock Frequency for DREAD instructions
DC
DC
5.5
13
5.5
13
0.1
0.1
7
-
-
33
MHz
MHz
ns
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
ms
us
ms
ms
s
80
fC=86MHz
-
-
tCH(1)
tCL(1)
tCLH
tCLL
Clock High Time
fR=33MHz
-
-
fC=86MHz
-
-
Clock Low Time
fR=33MHz
-
-
tCLCH(2)
tCHCL(2)
tSLCH
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
Data In Setup Time
-
-
-
-
tCSS
-
-
tCHSL
7
-
-
tDVCH
tCHDX
tCHSH
tSHCH
tDSU
tDH
2
-
-
Data In Hold Time
5
-
-
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
5
-
-
-
5
-
Read
15
40
-
-
-
tSHSL
tCSH
CS# Deselect Time
Write
-
-
tSHQZ(2)
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX(2)
tHLQZ(2)
tWHSL(4)
tSHWL (4)
tDP(2)
tRES1(2)
tRES2(2)
tW
tDIS
tV
Output Disable Time
-
8
Clock Low to Output Valid(15pF loading)
Output Hold Time
-
-
6
tHO
0
-
-
HOLD# Setup Time (relative to SCLK)
HOLD# Hold Time (relative to SCLK)
HOLD Setup Time (relative to SCLK)
HOLD Hold Time (relative to SCLK)
HOLD to Output Low-Z
5
-
-
5
-
-
5
-
-
5
-
-
tLZ
-
-
8
tHZ
HOLD# to Output High-Z
-
-
8
Write Protect Setup Time
20
100
-
-
-
Write Protect Hold Time
-
-
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic Signature Read
CS# High to Standby Mode with Electronic Signature Read
Write Status Register Cycle Time
Byte-Program
-
10
8.8
8.8
40
300
5
-
-
-
-
-
5
9
1.4
60
0.7
25
-
tBP
-
tPP
Page Program Cycle Time
-
tSE
Sector Erase Cycle Time
-
300
2
tBE
Block Erase Cycle Time
-
tCE
Chip Erase Cycle Time
-
50
-
s
tRPD1
CS# High to Power-Down
100
ns
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC. For Fast Read, tCL/tCH=5.5/5.5.
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Test condition is shown as Figure 5.
6. The CS# rising time needs to follow tCLCH spec and CS# falling time needs to follow tCHCL spec.
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12.5. Timing Analysis
Figure7. Serial Input Timing
Figure8. Output Timing
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Figure9. Hold Timing
* SI is "don't care" during HOLD operation.
Figure10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1
Figure11. Write Enable (WREN) Sequence (Command 06)
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Figure12. Write Disable (WRDI) Sequence (Command 04)
Figure13. Read Status Register (RDSR) Sequence (Command 05)
Figure14. Write Status Register (WRSR) Sequence (Command 01)
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GPR25L322B
Figure15. Read Data Bytes (READ) Sequence (Command 03)
Figure16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
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Figure17. Dual Output Read Mode Sequence (Command 3B)
Figure18. Sector Erase (SE) Sequence (Command 20)
Note: SE command is 20(hex).
Figure19. Block Erase (BE) Sequence (Command 52 or D8)
Note: BE command is 52 or D8(hex).
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Figure20. Chip Erase (CE) Sequence (Command 60 or C7)
Note: CE command is 60(hex) or C7(hex).
Figure21. Page Program (PP) Sequence (Command 02)
Figure22. Deep Power-down (DP) Sequence (Command B9)
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Figure23. Release from Deep Power-down (RDP) Sequence (Command AB)
Figure24. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
Figure25. Read Identification (RDID) Sequence (Command 9F)
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Figure26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
Note:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
Figure27. Read Security Register (RDSCUR) Sequence (Command 2B)
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Figure 28. Write Security Register (WRSCUR) Sequence (Command 2F)
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Figure 29. Program/ Erase flow with read array data
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Figure 30. Power-up Timing
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table10. Power-Up Timing
Symbol
Parameter
Min.
Max.
Unit
tVSL(1)
VCC(min) to CS# low
200
-
us
Note: 1.The parameter is characterized only.
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13. OPERATING CONDITIONS
13.1. At Device Power-Up and Power-down
AC timing illustrated in Figu re 31 and Figure 32 are the supply
applied on VCC to keep the device not be se lected. The CS#
can be driven low when VCC reach Vcc(min.) and wait a period of
tVSL.
voltages and the control sig
nals at device pow er-up and
power-down. If the timing in the figures is ignored, the device will
not operate correctly.
During power-up and power down, CS# need to follow the voltage
Figure 31. AC Timing at Device Power-Up
Symbol
Parameter
Notes
Min.
Max.
Unit
tVR
VCC Rise Time
1
20
500000
us/V
Notes:
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table.
Figure 32. Power-Down Sequence
During power down, CS# need to follow the voltage drop on VCC to avoid mis-operation.
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14. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Min.
Typ.(1)
Max.(2)
40
Unit
ms
ms
s
Write Status Register Time
Sector Erase Time
-
-
-
-
-
-
-
5
60
0.7
300
2
Block Erase Time
Chip Erase Time
25
50
s
Byte Program Time (via page program command)
Page Program Time
9
300
5
us
1.4
ms
cycles
Erase/Program Cycle
100,000 -
Notes:
1. Typical program and erase time assumes the following conditions: 25℃, 3.3V, and checker board pattern.
2. Under worst conditions of 85℃ and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
4. Erase/Program cycles comply with JEDEC JESD-47 & JESD22-A117A standard.
14.1. Data Retention
Parameter
Condition
Min.
Max.
UNIT
Data retention
55°C
20
-
years
14.2. Latch-up Characteristics
Min.
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
-1.0V
-1.0V
2 VCCmax
VCC + 1.0V
+100mA
-100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
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15. PACKAGE/PAD LOCATIONS
15.1. Ordering Information
Product Number
Package Type
GPR25L322B-QS13x
Package Form - SOP 8L 209mil RoHS (Green Package)(Tube)
GPR25L322B-LS13x
Package Form - SOP 8L 209mil RoHS (Green Package)(Tape and Reel)
Note: x = 1 - 9, serial number.
15.2. Package Information
15.2.1. Package Outline for SOP 8L (209MIL)
15.2.1.1. Dimensions (Inch dimensions are derived from the original mm dimensions)
Symbol
Θ
A
A1
A2
b
C
D
E
E1
e
L
L1
S
Unit
Min.
Nom.
Max.
Min.
-
0.05
0.15
1.70
1.80
0.36
0.41
0.19
0.20
5.13
5.23
7.70
7.90
5.18
5.28
-
0.50
0.65
1.21 0.62
1.31 0.74
1.41 0.88
0
5
8
0
5
8
mm
-
1.27
2.16
0.20
1.91
0.51
0.25
5.33
8.10
5.38
-
0.80
-
-
0.002
0.006
0.008
0.067
0.071
0.075
0.014
0.016
0.020
0.007
0.008
0.010
0.202
0.206
0.210
0.303
0.311
0.319
0.204
0.208
0.212
-
0.050
-
0.020
0.026
0.031
0.048 0.024
0.052 0.029
0.056 0.035
inch
Nom.
Max.
0.085
Reference
DWG. NO.
Revision
Issue Date
JEDEC
EIAJ
6110-1406
2
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16. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms
of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication
or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY
OF MERCHANTABILITY OR FITNESS FOR A NY PURPOSE. GENERALP LUS reserves th e right to halt production or al ter the
specifications and prices at an y time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. milit ary equipment or medical lif e support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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17. REVISION HISTORY
Date
Revision
1.3
Description
Page
Jun. 06, 2014
Apr. 07, 2011
Modify 15.1 Ordering Information.
36
4
1.2
1. Modified description for RoHS compliance.
2. Removed SFDP related description.
4,8,12,
18
3. Added CS# rising and falling time description.
4. Modified tW from 40ms(typ.)/100ms(max) to 5ms(typ.)/40ms(max).
5. Modified tCLQV(15pF loading) from 8ns(max) to 6ns(max)
6. Modified tCHSH/tSHCH from 7ns(min) to 5ns(min).
7. Added RDSCUR & WRSCUR diagram form.
Add writer compatible information in section 1.1
Original
8,22
22,35
22
22
30,31
4
Dec. 14, 2010
Aug. 25, 2010
1.1
1.0
40
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