GPUSB101A [GENERALPLUS]
USB Bridge Controller;
| 型号： | GPUSB101A |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | USB Bridge Controller |
| 文件： | 总37页 (文件大小：927K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
USB Bridge Controller
Sep 24, 2014
Version 1.4
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPUSB101A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 4
2. APPLICATION FIELD.................................................................................................................................................................................. 4
3. FEATURES.................................................................................................................................................................................................. 4
4. BLOCK DIAGRAM ...................................................................................................................................................................................... 4
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
5.1. PIN MAP ............................................................................................................................................................................................... 6
5.2. PAD ASSIGNMENT ................................................................................................................................................................................. 7
6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 8
6.1. POWER SAVING MODE ........................................................................................................................................................................... 8
6.2. PLL (PHASE LOCK LOOP)....................................................................................................................................................................... 8
6.3. I/O........................................................................................................................................................................................................ 8
6.4. PARALLEL BUS....................................................................................................................................................................................... 9
6.4.1 The description of parallel bus I/O ............................................................................................................................................ 9
6.4.2 The function of parallel bus....................................................................................................................................................... 9
6.4.3 Timing diagram ......................................................................................................................................................................... 9
6.4.4 Timing constrain...................................................................................................................................................................... 10
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 11
7.1. ABSOLUTE MAXIMUM RATINGS ..............................................................................................................................................................11
7.2. DC CHARACTERISTICS (VDD = 3.3V, TA = 25℃) ...................................................................................................................................11
7.3. REGULATOR CHARACTERISTICS.............................................................................................................................................................11
8. APPLICATION CIRCUITS......................................................................................................................................................................... 13
9. PACKAGE/ORDERING INFORMATION................................................................................................................................................... 14
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 14
9.2. PACKAGE INFORMATION ....................................................................................................................................................................... 14
10.GPUSB101A USER'S GUIDE ................................................................................................................................................................... 17
10.1.INTRODUCTION .................................................................................................................................................................................... 17
10.1.1. Features ............................................................................................................................................................................. 17
10.2.SYSTEM FUNCTION DIAGRAM ............................................................................................................................................................... 17
10.2.1. SPI interface: 4 GPIO + 4 SPI............................................................................................................................................ 17
10.2.2. Parallel Bus 8 bit interface: 5 GPIO control pin + 8 GPIO data pin .................................................................................... 18
10.2.3. Parallel Bus 4 bit interface: 5 GPIO control pin + 4 GPIO data pin .................................................................................... 19
10.2.4. Software UART: 2 GPIO pin ............................................................................................................................................... 20
10.3.USB BULK ONLY COMMAND PROTOCOL ............................................................................................................................................... 21
10.3.1. Command Block Wrapper (CBW)....................................................................................................................................... 21
10.3.2. Command Status Wrapper (CSW) ..................................................................................................................................... 22
10.4.VENDER COMMAND ............................................................................................................................................................................. 23
10.4.1. Get IC version..................................................................................................................................................................... 24
10.4.2. SPI Flash Read .................................................................................................................................................................. 24
10.4.3. SPI Flash Write................................................................................................................................................................... 25
10.4.4. SPI Flash Sector Erase ...................................................................................................................................................... 26
10.4.5. SPI Flash Chip Erase ......................................................................................................................................................... 26
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GPUSB101A
10.4.6. Set Vender ID ..................................................................................................................................................................... 27
10.4.7. Reserved write.................................................................................................................................................................... 28
10.4.8. Reserved Read................................................................................................................................................................... 28
10.5.GPUSB INTERFACE PROTOCOL COMMAND LIST ................................................................................................................................... 29
10.6.GPUSB PROGRAM FLOW .................................................................................................................................................................... 30
10.6.1. SPI interface protocol ......................................................................................................................................................... 31
10.6.2. Parallel bus 8 bit mode....................................................................................................................................................... 32
10.6.3. Parallel bus 4 bit mode....................................................................................................................................................... 34
10.6.4. S/W UART mode................................................................................................................................................................ 35
11. DISCLAIMER............................................................................................................................................................................................. 36
12.REVISION HISTORY ................................................................................................................................................................................. 37
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GPUSB101A
USB BRIDGE CONTROLLER
1. GENERAL DESCRIPTION
3. FEATURES
The GPUSB101A carries an 8-bit processor, 16K bytes OTP ROM,
256 bytes working SRAM, six 64 bytes buffer SRAM, 2 set 12-bit
Working Voltage: 2.4V - 3.6V (without USB)
3.0V - 3.6V (with USB)
timers, and 20 general I/Os.
programmed as parallel bus or SPI.
The general I/Os can be
IOA, IOB Working Voltage: 2.4V - 5.5V
IOC Working Voltage: 2.4V - 3.6V
CPU Speed: 0.09375MHz - 12MHz
ROM Size: 16 K bytes OTP ROM
RAM Size: 256 bytes working SRAM
Six 64 bytes buffer SRAM
There are three main functions for the bridge IC.
USB to parallel bus
USB to SPI
Parallel bus to SPI
Two 12-bit timers/counters
On-chip Voltage Regulator: 3.3 V output
USB Specification 2.0 compliant; full-speed (12 Mbps)
USB supports Bulk IN, Bulk OUT, Interrupt IN, Isochronous IN
and Isochronous OUT transfer mode
20 GPIO port (Parallel bus and SPI share with GPIO)
Supports parallel bus 4 bit mode (5 pin for control and 4 pin for
data)
2. APPLICATION FIELD
USB Bulk transfer for download
USB Isochronous IN transfer for MIC in (needs extra ADC)
USB Isochronous OUT transfer for speaker out(needs extra
DAC)
Supports parallel bus 8 bit mode (5 pin for control and 8 pin for
data)
USB Interrupt IN transfer for small data communication
Supports SPI master mode
Supports SPI slave mode
Supports SPI transparent mode (Host IC can control SPI slave
device through bridge IC )
4. BLOCK DIAGRAM
SPI
HOST IC
I/O
CPU
RAM
256 B
OTP
16K
Parallel Bus
6502
+Timer
+ Int
SPI transparent
BUS_SEL
PLL
12 M
BUF0
64 B
BUF3
64 B
SPI slave
BUF1
64 B
BUF4
64 B
SPI Flash
SPI M/S
SPI master
CPU_USB
IF
CLK_DIV
BUF2
64 B
BUF5
64 B
USB
PHY
PC
UDC
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GPUSB101A
5. SIGNAL DESCRIPTIONS
Pad Name
PIN NO.
LQFP64
PIN NO.
Type
Description
XI
6
7
2
3
1
9
8
6
7
2
3
1
9
8
I
O
P
G
P
I
Oscillator crystal input
XO
Oscillator crystal output
V50_REG
VSS_REG
V33_REG
RESETB
TEST
Regulator power 5V input
Regulator power ground input
Regulator power 3.3V output
System reset pin (active low)
I
TEST Mode selection pin, high is test mode and low is normal mode (Pad internal
pull low)
VDD
VSS
10
11
10
11
P
G
Positive power supply for core and IOC (2.4V~3.6V)
Ground reference for core
AVDD3
AVSS3
V33_USB
VSS_USB
DPLS
4
4
P
Positive power supply for analog circuit
Ground reference for analog circuit
USB power 3.3V input
5
5
G
41
45
P
38
42
G
USB power ground input
40
44
I/O
I/O
I/O
USB DPLS
DMNS
39
43
USB DMNS
IOA[7:0]
22-19,
36-33
32-27,
24-23
18-15
13
22-19,
40-37
36,31-27,
24-23,
18-15
13
bi-directional I/O ports, power source from IOVDD5(2.4V~5.5V)
IOB[7:0]
I/O
bi-directional I/O ports, power source from IOVDD5(2.4V~5.5V)
IOC[3:0]
OTPSCK
OTPSDA
IOVDD5
I/O
I
bi-directional I/O ports, power source from VDD(2.4V~3.6V)
OTP writer clock input (Pad internal pull low)
OTP writer data input/output (Pad internal pull low)
IOA and IOB power source input (2.4V~5.5V)
IOA and IOB power source ground input
14
14
I/O
P
25
25
IOVSS5
26
26
G
I
OTPPARA
VPP
12
12
OTP test pin (Pad internal pull low)
37
41
P
OTP high voltage power supply for programming
Total: 41 Pads
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GPUSB101A
5.1. PIN Map
LQFP 64 Package Top View
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
V33_REG
V50_REG
VSS_REG
AVDD3
AVSS3
XI
NC
2
3
47
NC
46
45
44
NC
4
V33_USB
DPLS
DMNS
5
6
43
42
41
GPUSB101A
LQFP64
7
VSS_USB
VPP
XO
8
TEST
9
IOA3
IOA2
IOA1
IOA0
IOB7
NC
RESETB
VDD
40
39
38
37
10
11
12
VSS
OTPPARA
OTPSCK
OTPSDA
IOC0
13
14
15
16
36
35
34
33
NC
IOC1
NC
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
17
SSOP 20 Package Top View
NC
V33_REG
V50_REG
AVDD3
XI
1
2
20
19
18
17
16
15
14
13
12
11
NC
TEST
VDD
3
4
V33_USB
DPLS
DMNS
VPP
5
GPUSB101A
XO
6
RESETB
OTPSCK
OTPSDA
IOA7
7
8
IOA1
9
IOVSS5
IOVDD5
10
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GPUSB101A
5.2. PAD Assignment
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GPUSB101A
6. FUNCTIONAL DESCRIPTIONS
6.1. Power Saving Mode
Suppose system operating voltage is running at 3.3V, then
IOVDD5 (power for I/O) operates from 3.3V to 5.5V. In such
condition, the I/O pad is capable of operating from 0V through
IOVDD5. The following diagram is an I/O schematic. Although
data can be written into the same register through Port_Data and
Port_Buffer, they can be read from different places, Buffer (R) and
Data (R).
The GPUSB101A features a power saving mode(or called standby
mode) for low power application. To enter standby mode, the
desired key wakeup port(IOA[7:0]) must be configured to input first.
And read the P_IOA_Data to latch the IOA state before entering
the standby mode.
6.2. PLL (Phase Lock Loop)
Buffer(R)
The purpose of PLL is to provide stable output frequency which
reference a base frequency (from crystal). The PLL output
frequency is 48MHz. It is used for USB device core.
Port_Data(W)
Register
pull high
pull low
Port_Buffer(W)
Port_DIR(R/W)
Port_ATTR(R/W)
Pin pad
Control
logic
6.3. I/O
Three I/O ports are built in GPUSB101A - PortA, PortB and PortC,
total has 20 bit-programmable I/Os. The PortA is a general
purpose I/O with programmable wakeup capability, i.e. IOA [7:0] is
the key wakeup port. To activate key wakeup function, latch data
on P_IOA_Data and enable the key wakeup function. Wakeup is
triggered when the PortA state is different from at the time latched.
Furthermore, the I/O ports can be operated at 5V level(only PortA
and PortB), higher than the CPU core which is a 3.3V level system.
Data(R)
In addition to a general purpose I/O port function, PortA/B/C also
shares some special functions. A summary of PortA/B/C special
functions is listed as follows:
Port A
Port A
Wakeup
Parallel
IOA[7]
IOA[6]
IOA[5]
IOA[4]
ˇ
IOA[3]
ˇ
IOA[2]
ˇ
IOA[1]
ˇ
IOA[0]
ˇ
ˇ
ˇ
ˇ
-
-
-
para_int
para_wrb
para_rdb
para_csb
para_cdb
Port B
Port B
Parallel
IOB[7]
IOB [6]
IOB[5]
IOB [4]
IOB [3]
IOB [2]
IOB [1]
IOB [0]
para_data[7] para_data[6] para_data[5] para_data[4] para_data[3] para_data[2] para_data[1] para_data[0]
SPI slave
spi_rxd
spi_txd
spi_clk
spi_csb
-
-
-
-
Port C
Port C
IOC [3]
spi_rxd
IOC [2]
IOC [1]
IOC [0]
SPI master
spi_txd
spi_clk
spi_csb
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GPUSB101A
6.4. Parallel Bus
There is a parallel bus slave side on GPUSB101A. The host IC as a parallel bus master role. Host IC can use GPIO toggle to implement
signals like section 6.4.3. According to host IC GPIOs number. The customer can select 8 bit mode (5 control pin and 8 data pin) or 4 bit
mode (5 control pin and 4 data pin). Besides Para_int is input pin, others control pin are output pin. If the GPUSB101A has request to
host IC. GPUSB101A may issues Parallel_int pin then host IC must polling the status register and knows what request from GPUSB101A.
6.4.1 The description of parallel bus I/O
Pad name
Para_cdb
Type
IO
Description
I
I
IOA[0]
IOA[1]
IOA[2]
IOA[3]
IOA[4]
IOB[7:0]
Parallel bus for command or data transfer (high is command and low is data)
Parallel bus chip enable (active low)
Parallel bus write enable (active low)
Parallel bus read enable (active low)
Parallel bus interrupt out
Para_csb
Para_rdb
I
Para_wrb
I
Para_int
O
I/O
Para_data[7:0]
Parallel bus bi-directional data
6.4.2 The function of parallel bus
Para_cdb
Para_wrb
Para_rdb
Description
1
1
0
0
0
1
0
1
1
0
1
0
Write command register
Read status register
Write data
Read data
Note1: command register is read only bridge IC.
Note2: status register is read only for host IC.
6.4.3 Timing diagram
8 bit mode
Write command
Write data
T1
T2
T3
T4
T6
T1
T2
T3
T4
T5
T6
para_cdb
para_cdb
para_csb
para_csb
para_wrb
para_wrb
1st data
2nd data
last data
para_data[7:0]
command
para_data[7:0]
Read data
T8
Read status
T1
T2
T7
T5
T6
para_cdb
T1
T2
T7
T8
T6
para_cdb
para_csb
para_rdb
para_csb
para_rdb
para_data[7:0]
1st data
2nd data
last data
para_data[7:0]
status
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GPUSB101A
6.4.4 Timing constrain
Unit
Characteristics
Symbol
Unit
Min.
100
100
100
200
100
100
300
0
Typ.
Max.
cdb to csb delay time
csb to wrb(rdb) delay time
wrb to data setup time
wrb to data hold time
wrd to csb delay time
csb to cdb delay time
Data out stable time
Latch data hold time
T1
T2
T3
T4
T5
T6
T7
T8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
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GPUSB101A
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
Min.
Max.
Unit
IOA , IOB PAD Supply Voltage
IOC PAD Supply Voltage
Analog Supply Voltage
IOVDD5
VDD
AVDD3
VDD
VESD
-0.3
-0.3
-0.3
-0.3
2K
5.5
3.6
3.6
3.6
-
V
V
V
Core Supply Voltage
V
ESD Protection(HBM)
V
℃
℃
Operating Temperature Range
Storage Temperature Range
TA
0
+60
+150
TSTO
-50
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions,
see DC Electrical Characteristics.
7.2. DC Characteristics (VDD = 3.3V, TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Core Operating Voltage
IOA, IOB PAD Operating Voltage
IOC PAD Operating Voltage
Analog Operating Voltage
Operating Current
VDD
IOVDD5
VDD
AVDD3
IOP
2.4
3.3
3.6
V
V
2.4
-
5.5
2.4
3.3
3.6
V
2.4
-
3.6
V
-
4.3
6
mA
μA
μA
V
FCPU = 12MHz @ 3.3V(Typ.), USB OFF
VDD = 3.3V, whole chip with regulator ON
VDD = 3.3V, whole chip with regulator OFF
ISTBY1
ISTBY2
VIH1
-
3
5
Standby Current
-
1
3
Input High Level (IOA,IOB)
Input Low Level (IOA,IOB)
Input High Level (IOC)
Input Low Level (IOC)
0.7Vdd
-
-
VIL1
-
-
0.3Vdd
V
VIH2
0.7Vdd
-
-
V
VIL2
-
-2
-4
3
6
-2
3
-
-
-
0.3Vdd
V
-
-
-
-
-
-
-
-
-
-
-
-
VOH = 0.9*IOVDD5, IOVDD5=3.3V
VOH = 0.9*IOVDD5, IOVDD5=5V
VOL = 0.1*IOVDD5, IOVDD5=3.3V
VOL = 0.1*IOVDD5, IOVDD5=5V
VOH = 0.9*VDD, VDD=3.3V
VOL = 0.1*VDD, VDD=3.3V
Vin = GND, IOVDD5=3.3V
Vin = GND, IOVDD5=5V
Output High Current (IOA,IOB)
Output Sink Current (IOA,IOB)
IOH1
mA
mA
-
-
IOL1
-
Output High Current (IOC)
Output Sink Current (IOC)
IOH2
IOL2
-
mA
mA
-
170
95
160
95
110
130
Pull-up Resistor (IOA,IOB)
RPU1
KΩ
KΩ
-
-
Vin = IOVDD5, IOVDD5=3.3V
Vin = IOVDD5, IOVDD5=5V
Vin = GND, VDD=3.3V
Pull-down Resistor (IOA,IOB)
RPD1
-
Pull-up Resistor(IOC)
RPU2
RPD2
-
KΩ
KΩ
Pull-down Resistor(IOC)
-
Vin = VDD, VDD=3.3V
7.3. Regulator Characteristics
Characteristics
Unit
Symbol
Unit
Test Condition
Min.
2.4
-
Typ.
Max.
5.5
Input Voltage
V50_REG
IREGO
-
-
V
Maximum Current Output
60
mA
V50_REG>=3.3V, VDROP<0.2V
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GPUSB101A
Unit
Typ.
3.3
-
Characteristics
Output Voltage
Symbol
Unit
Test Condition
Min.
Max.
3.6
200
2
V33_REG
VDROP
3.0
V
Note1
V50_REG=3.3V, IREGO=60mA
Drop Voltage
-
-
mV
uA
Standby Current
IREGS
-
Note1: When input voltage below 3.3V will limit the output of the regulator to V50_REG- VDROP
.
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GPUSB101A
8. APPLICATION CIRCUITS
GPUSB101A
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GPUSB101A
9. PACKAGE/ORDERING INFORMATION
9.1. Ordering Information
Product Number
Package Type
GPUSB101A-NnnV-C
GPUSB101A-NnnV-QL02x
GPUSB101A-NnnV-HG02x
Chip form
Halogen Free 64 pin LQFP Package
Green Package - SSOP 20 (209mil)
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
Note3: Package form number (x = 1 - 9, serial number).
9.2. Package Information
LQFP 64
Symbols
Min.
Nom.
Max.
A
-
-
-
1.60
0.15
A1
0.05
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GPUSB101A
Symbols
Min.
Nom.
Max.
A2
b
1.35
0.17
0.09
11.75
9.90
11.75
9.90
1.40
0.22
1.45
0.27
c1
D
-
0.16
12.00
12.25
10.10
12.25
10.10
D1
E
10.00
12.00
E1
e
10.00
0.50 BSC
0.60
L
0.45
0.75
L1
S
1.00 REF
0.20 REF
3.5° REF
5.0° REF
12° REF
12° REF
0.16 REF
0.15 REF
θ
θ1
θ2
θ3
R1
R2
Thermally enhanced dimension(shown in mm)
E2
D2
Pad Size
Min.
Max.
Min.
Max.
210x21E
260x26E
4.27
5.28
5.33
6.60
4.27
5.28
5.33
6.60
Notes:
1. JEDEC Outline:
MS-026 BCD
MS-026 BCD-HD(Thermally Enhanced Variations Only)
2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions
including mold mismatch.
3. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more
than 0.08mm.
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GPUSB101A
SSOP 20
Millimeter
Nom.
Symbol
Min.
--
Max.
2.0
A
A1
A2
b
--
--
0.05
1.65
0.22
0.09
6.90
7.40
5.00
--
1.75
--
1.85
0.38
0.21
7.50
8.20
5.60
c
--
D
7.20
7.80
5.30
0.65 BSC
0.75
1.25 REF
--
E
E1
e
L
0.55
0.95
L1
R1
θ°
0.09
--
0°
4°
8°
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GPUSB101A
10. GPUSB101A USER'S GUIDE
10.1. Introduction
10.1.1. Features
program on PC also can interact with the host controller to perform
some applications such as playing songs, driving LEDs or motors
through USB vender commands.
GPUSB101A is a bridge IC which provides the interface between
PC and a host controller through USB1.1 Vender Command.
When PC detects that GPUSB101A is plugged in, PC will indicate
that a new USB device is inserted on device manager, and the PC
application can access that new USB device via Generalplus USB
driver. In GPUSB101A, there are 4 interfaces to interface with a
host controller, including SPI interface, Parallel Bus 8 bit interface,
Parallel Bus 4 bit interface, and Software UART. Moreover, the
communication protocol between GPUSB101A and PC follows the
USB1.1 specification.
Interface
I/O
Function
SPI
8
1. PC Download data to SPI flash
2. PC access HOST IC
3. HOST IC access SPI flash
1. PC Download data to SPI flash
2. PC access HOST IC
Parallel 8 bit
Parallel 4 bit
S/W UART
13
9
3. HOST IC access SPI flash
1. PC Download data to SPI flash
2. PC access HOST IC
By GPUSB101A, PC is able to write, read and erase SPI Flash as
a mass storage device and then the host controller can access
SPI Flash either through SPI interface of the host controller or
through the interfaces of GPUSB101A. Moreover, the application
3. HOST IC access SPI flash
1. PC access HOST IC
2
10.2. System Function Diagram
10.2.1. SPI interface: 4 GPIO + 4 SPI
Application
Download
Path
Class
Transfer
Bulk
Note
PC Æ GPUSB101A Æ SPI Master mode Æ SPI flash
PC Æ GPUSB101A Æ SPI Slave mode Æ Host IC
Host IC Æ SPI/Transparent mode Æ SPI flash
Mass storage
Mass storage
Mass storage
Vendor command
Vendor command
Vendor command
PC link Host IC
Bulk
Host IC access flash
Bulk
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GPUSB101A
10.2.2. Parallel Bus 8 bit interface: 5 GPIO control pin + 8 GPIO data pin
Application
Download
Path
Class
Transfer
Bulk
Note
PC Æ GPUSB101A Æ SPI Master mode Æ SPI flash
PC Æ GPUSB101A Æ Parallel bus 8 bit Æ Host IC
GPIC Æ Parallel bus 8 bit Æ GPUSB101A Æ SPI Master
mode Æ SPI flash
Mass storage
Mass storage
Mass storage
Vendor command
Vendor command
Vendor command
PC link Host IC
Bulk
Host IC access flash
Bulk
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GPUSB101A
10.2.3. Parallel Bus 4 bit interface: 5 GPIO control pin + 4 GPIO data pin
Application
Download
Path
Class
Transfer
Bulk
Note
PC Æ GPUSB101A Æ SPI Master mode Æ SPI flash
PC Æ GPUSB101A Æ Parallel bus 4 bit Æ Host IC
GPIC Æ Parallel bus 4 bit Æ GPUSB101A Æ SPI Master
mode Æ SPI flash
Mass storage
Mass storage
Mass storage
Vendor command
Vendor command
Vendor command
PC link Host IC
Bulk
Host IC access flash
Bulk
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GPUSB101A
10.2.4. Software UART: 2 GPIO pin
Application
PC link Host IC
Path
PC Æ GPUSB101A Æ I/O(S/W UART) Æ Host IC
Class
Transfer
Note
Mass storage
Bulk
Vendor command
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GPUSB101A
10.3. USB Bulk Only Command Protocol
GPUSB101A must receive USB vendor command from USB Host (PC). The command format is following USB mass storage device
class command.
Figure 1 - Command/Data/Status Flow shows the flow for Command Transport, Data-In, Data-Out and Status Transport. The following
sections define Command and Status Transport.
10.3.1. Command Block Wrapper (CBW)
The CBW shall start on a packet boundary and shall end as a short packet with exactly 31 (1Fh) bytes transferred. Fields appear aligned
to byte offsets equal to a multiple of their byte size. All subsequent data and the CSW shall start at a new packet boundary. All CBW
transfers shall be ordered with the LSB (byte 0) first (little endian). Refer to the USB Specification Terms and Abbreviations for
clarification.
TABLE 7.3.1. Command Block Wrapper
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GPUSB101A
dCBWSignature:
bCBWLUN:
Signature that helps identify this data packet as a CBW. The
signature field shall contain the value 43425355h (little endian),
indicating a CBW.
The device Logical Unit Number (LUN) to which the command
block is being sent. For devices that support multiple LUNs, the
host shall place into this field the LUN to which this command
block is addressed. Otherwise, the host shall set this field to
zero.
dCBWTag:
A Command Block Tag sent by the host. The device shall echo
the contents of this field back to the host in the dCSWTag field of
the associated CSW. The dCSWTag positively associates a
CSW with the corresponding CBW.
bCBWCBLength:
The valid length of the CBWCB in bytes. This defines the valid
length of the command block. The only legal values are 1
through 16 (01h through 10h). All other values are reserved.
dCBWDataTransferLength:
CBWCB:
The number of bytes of data that the host expects to transfer on
the Bulk-In or Bulk-Out endpoint (as indicated by the Direction bit)
during the execution of this command. If this field is zero, the
device and the host shall transfer no data between the CBW and
the associated CSW, and the device shall ignore the value of the
Direction bit in bmCBWFlags.
The command block to be executed by the device. The device
shall interpret the first bCBWCBLength bytes in this field as a
command block as defined by the command set identified by
bInterfaceSubClass. If the command set supported by the device
uses command blocks of fewer than 16 (10h) bytes in length, the
significant bytes shall be transferred first, beginning with the byte
at offset 15 (Fh). The device shall ignore the content of the
CBWCB field past the byte at offset (15 + bCBWCBLength - 1).
bmCBWFlags:
The bits of this field are defined as follows:
Bit
7 Direction - the device shall ignore this bit if the
10.3.2. Command Status Wrapper (CSW)
dCBWDataTransferLength field is zero, otherwise:
0 = Data-Out from host to the device,
The CSW shall start on a packet boundary and shall end as a
short packet with exactly 13 (0Dh) bytes transferred. Fields
appear aligned to byte offsets equal to a multiple of their byte size.
All CSW transfers shall be ordered with the LSB (byte 0) first (little
endian). Refer to the USB Specification Terms and Abbreviations
for clarification.
1 = Data-In from the device to the host.
Bit 6 Obsolete. The host shall set this bit to zero.
Bits 5...0 Reserved - the host shall set these bits to zero.
TABLE 7.3.2. Command Status Wrapper
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GPUSB101A
processed by the device. For Data-In the device shall report in
the dCSWDataResidue the difference between the amount of data
expected as stated in the dCBWDataTransferLength and the
dCSWSignature:
Signature that helps identify this data packet as a CSW. The
signature field shall contain the value 53425355h (little endian),
indicating CSW.
actual amount of relevant data sent by the device.
The
dCSWDataResidue shall not exceed the value sent in the
dCBWDataTransferLength.
dCSWTag:
The device shall set this field to the value received in the
dCBWTag of the associated CBW.
bCSWStatus:
bCSWStatus indicates the success or failure of the command.
The device shall set this byte to zero if the command completed
successfully. A non-zero value shall indicate a failure during
command execution according to the following table:
dCSWDataResidue:
For Data-Out the device shall report in the dCSWDataResidue the
difference between the amounts of data expected as stated in the
dCBWDataTransferLength, and the actual amount of data
10.4. Vender Command
PC <-> GPUSB
Command Block Wrapper 15th byte-30th byte
Byte Bit
7
6
5
4
3
2
1
0
0
Operation Code
1
2
(MSB)
3
Reserved
4
5
6
7
(MSB)
Transfer Length
8
9
10
11
Command
OP Code
F0 10
Description
Get IC Version
Generalplus verify
SPI Flash Read
SPI Flash Write
SPI Flash Sector Erase
SPI Flash Chip Erase
Set Vender ID
FD 28
FD 2A
FD 20
FD FF
FF F0
Ex xx.
Dx xx
SPI Flash physical read
SPI Flash physical write
SPI Flash sector erase, erase size = 64K Bytes
SPI Flash sector erase, erase size = 4M Bytes
Generalplus verify
Reserved write
PC write data to Host IC
Reserved read
PC read data from Host IC
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GPUSB101A
10.4.1. Get IC version
Command Block Wrapper 15th byte-30th byte
Byte Bit
7
6
5
4
3
2
1
0
0
F0 10
1
2
(MSB)
3
Reserved
Reserved
4
5
6
7
(MSB)
8
9
10
11
Operation Code
0xF010
Function
Comment
Set vendor ID
*CBW Byte 15: 0xF0
*CBW Byte 16: 0x10
*CBW Byte 29-30: GP Tag
*IN 11 Bytes for IC Version information
10.4.2. SPI Flash Read
Command Block Wrapper 15th byte-30th byte
Byte Bit
7
6
5
4
3
2
1
0
0
FD 28
1
2
(MSB)
3
LBA (Logical Block Address)
Transfer Length (scoters)
4
5
6
06
7
(MSB)
8
9
10
11
1 scoters = 512 bytes
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GPUSB101A
Operation Code
0XFD28
Function
Comment
SPI flash Physical Read
*CBW Byte 15: 0XFD
*CBW Byte 16: 0x28
*CBW Byte 17: High word High byte Address
*CBW Byte 18: High word Low byte Address
*CBW Byte 19: Low word High byte Address
*CBW Byte 20: Low word Low byte Address
*CBW Byte 21: 0x06. it mean SPI Nor Flash
*CBW Byte 22: High Operation Data Length
*CBW Byte 23: Low Operation Data Length
*CBW Byte 29-30: GP Tag
10.4.3. SPI Flash Write
Command Block Wrapper 15th byte-30th byte
Byte Bit
7
6
5
4
3
2
1
0
0
FD 2A
1
2
(MSB)
3
LBA (Logical Block Address)
Transfer Length (sectors)
4
5
6
06
7
(MSB)
8
9
10
11
1 sectors = 512 bytes
Operation Code
Function
SPI flash Physical Write
Comment
0XFD2A
*CBW Byte 15: 0xFD
*CBW Byte 16: 0x2A
*CBW Byte 17: High word High byte Address
*CBW Byte 18: High word Low byte Address
*CBW Byte 19: Low word High byte Address
*CBW Byte 20: Low word Low byte Address
*CBW Byte 21: 0x06 .it mean SPI NorFlash
*CBW Byte 22: High Operation Data Length
*CBW Byte 23: Low Operation Data Length
*CBW Byte 29-30: GP Tag
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GPUSB101A
10.4.4. SPI Flash Sector Erase
Command Block Wrapper 15th byte-30th byte
Byte Bit
7
6
5
4
3
2
1
0
0
FD 20
1
2
(MSB)
3
LBA (Logical Block Address)
Transfer Length (sectors)
4
5
6
06
7
(MSB)
8
9
10
11
1 sectors = 512 bytes
Operation Code
Function
SPI flash Physical scoter erase, erase size *CBW Byte 15: 0xFD
= 64K Bytes(GPR25L320A) *CBW Byte 16: 0x20
Comment
0XFD20
*CBW Byte 17: High word High byte Address
*CBW Byte 18: High word Low byte Address
*CBW Byte 19: Low word High byte Address
*CBW Byte 20: Low word Low byte Address
*CBW Byte 21: 0x06 .it mean SPI Nor Flash
*CBW Byte 22: High Operation Data Length
*CBW Byte 23: Low Operation Data Length
*CBW Byte 29-30: GP Tag
10.4.5. SPI Flash Chip Erase
Command Block Wrapper 15th byte-30th byte
Byte Bit
7
6
5
4
3
2
1
0
0
FD FF
1
2
(MSB)
3
LBA ( Logical Block Address )
Transfer Length (sectors)
4
5
6
06
7
(MSB)
8
9
10
11
1 sectors = 512 bytes
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GPUSB101A
Operation Code
0XFDFF
Function
Comment
SPI flash Physical scoter erase, erase size *CBW Byte 15: 0xFD
= 4MBytes(GPR25L320A)
*CBW Byte 16: 0xFF
*CBW Byte 17: High word High byte Address
*CBW Byte 18: High word Low byte Address
*CBW Byte 19: Low word High byte Address
*CBW Byte 20: Low word Low byte Address
*CBW Byte 21: 0x06 .it mean SPI Nor Flash
*CBW Byte 22: High Operation Data Length
*CBW Byte 23: Low Operation Data Length
*CBW Byte 29-30: GP Tag
10.4.6. Set Vender ID
Command Block Wrapper 15th byte-30th byte
Byte Bit
7
6
5
4
3
2
1
0
0
FF F0
1
2
(MSB)
3
Reserved
4
5
6
7
(MSB)
Transfer Length (bytes)
8
9
10
11
Operation Code
0xFFF0
Function
Comment
Set vendor ID
*CBW Byte 15: 0xFF
*CBW Byte 16: 0xF0
*CBW Byte 29-30: GP Tag
*IN 10 Bytes for IC Version information
This command can make sure Generalplus device.
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GPUSB101A
10.4.7. Reserved write
Command Block Wrapper 15th byte-30th byte
Byte Bit
7
6
5
4
3
2
1
0
0
EX XX
1
2
(MSB)
3
Reserved
Reserved
4
5
6
7
(MSB)
8
9
10
11
Operation Code
0xEX XX
Function
Comment
Reserved write
*CBW Byte 15: 0xEX
*CBW Byte 16: 0xXX
*CBW Byte 29-30: GP Tag
Example:
1. Application: PC + GPUSB101A + GPF8
2. PC issue customer command 0xE000 to GPF8
3. *CBW Byte 15 = 0xE0 & *CBW Byte 16 = 0x00,
4. GPUSB101A will transfer two bytes data 0xE0, 0x00 to GPF8, and then continue transfer N bytes data to GPF8. N = CBW Byte 8-11
dCBWDataTransferLength:
10.4.8. Reserved Read
Command Block Wrapper 15th byte-30th byte
Byte Bit
7
6
5
4
3
2
1
0
0
DX XX
1
2
(MSB)
3
Reserved
Reserved
4
5
6
7
(MSB)
8
9
10
11
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GPUSB101A
Operation Code
0xDX XX
Function
Comment
Reserved read
*CBW Byte 15 :0xDX
*CBW Byte 16 :0xXX
*CBW Byte 29-30: GP Tag
Example:
1. Application: PC + GPUSB101A + GPF8
2. PC issue to read GPF8 status
3. *CBW Byte 15 = 0xD0 & *CBW Byte 16 = 0x00,
4. GPUSB101A will transfer two bytes data 0xD0, 0x00 to GPF8, and then continue transfer N bytes data from GPF8. N = CBW Byte
8-11 dCBWDataTransferLength:
10.5. GPUSB Interface Protocol Command List
GPUSB -> Host IC
Command
USB Plug in
OP Code
C0 00
Description
USB plug in issue
PC suspend
C0 01
USB Plug out or PC suspend issue
PC resume issue
PC resume
C0 02
Vender command Write
Vender command Read
EX XX
DX XX
Customer define
Customer define
Example Vender command Write
1. E0 00: KEY 1 (PC issue PLAY)
2. E0 01: KEY 2 (PC issue NEXT)
3. E0 02: KEY 3 (PC issue PREVIOUS)
Example Vender command Read
1. D0 00: status1 (PC read Host IC I/O status)
2. D0 01: status2 (PC read Host IC Program status)
Host IC -> GPUSB
Command
OP Code
Description
Host IC issue GPUSB101A SPI transparent mode
SPI transparent mode
B0 01
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10.6. GPUSB Program Flow
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GPUSB101A
10.6.1. SPI interface protocol
Example
1. If GPUSB101A command Host IC to do something, op code = E0 01, Data = 12H, 34H, 56H, 78H
2. GPUSB101A command REQ1 = Hi, and wait Ack1 = Hi (when Host IC receive REQ1 = Hi, Host IC must stop access SPI Flash data,
and command ACK1 = Hi)
3. When Ack1 = Hi, GPUSB101A will issue SPI Slave mode and command REQ1 = Low
4. Then Host IC can start SPI TX protocol, and latch two bytes OP CODE = E0 01, command ACK1 = low
5. GPUSB101A continue command REQ1 = Hi, wait Ack1 = Hi
6. Host IC command ACK1 = Hi, GPUSB101A command REQ1 = Low
7. Then Host IC can start SPI TX protocol, and latch four bytes data =12H, 34H, 56H, 78H, command ACK1 = low
8. OP code must be two bytes, data transfer max = 64bytes/frame
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GPUSB101A
SPICLK
SPICSN
SPIRX
MSB
MSB
LSB MSB
SPITX
SPIOE
LSB MSB
8 bits
Fig1. Master Mode, SPO = 0, SPH = 0
10.6.2. Parallel bus 8 bit mode
Write command:
T1
T2
T3
T4
T6
para_cdb
para_csb
para_wrb
command
para_data[7:0]
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GPUSB101A
Read status:
T1
T2
T7
T8
T6
para_cdb
para_csb
para_rdb
para_data[7:0]
status
Write data:
T1
T2
T3
T4
T5
T6
para_cdb
para_csb
para_wrb
1st data
2nd data
last data
para_data[7:0]
Read data:
T8
T1
T2
T7
T5
T6
para_cdb
para_csb
para_rdb
para_data[7:0]
1st data
2nd data
last data
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GPUSB101A
10.6.3. Parallel bus 4 bit mode
Write command:
para_cdb
para_csb
para_wrb
command
LSB
command
MSB
para_data[3:0]
Read status:
para_cdb
para_csb
para_rdb
status
LSB
status
MSB
para_data[3:0]
Note: After Para_rdb falling edge, para_data is output until para_csb rising edge.
Write data:
para_cdb
para_csb
para_wrb
1st data
LSB
1st data
MSB
2nd data
LSB
2nd data
MSB
last data
LSB
last data
MSB
para_data[3:0]
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GPUSB101A
Read data:
para_cdb
para_csb
para_rdb
1st data
LSB
1st data
MSB
2nd data
LSB
2nd data
MSB
last data
LSB
last data
MSB
para_data[3:0]
Timing constrain
Characteristics
Unit
Symbol
Unit
Min.
Typ.
Max.
cdb to csb delay time
csb to wrb(rdb) delay time
wrb to data setup time
wrb to data hold time
wrd to csb delay time
csb to cdb delay time
Data out stable time
Latch data hold time
T1
T2
T3
T4
T5
T6
T7
T8
100
100
100
200
100
100
300
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
Note: The 4 bit mode time constrain is the same as 8 bit mode.
10.6.4. S/W UART mode
UART Data Frame Format
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GPUSB101A
11. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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GPUSB101A
12. REVISION HISTORY
Date
Revision #
Description
Page
7
SEP 24, 2014
1.4
1. Modify section 5.2 Pin Map.
2. Modify section 9.1 Ordering Information.
3. Modify section 9.2 Package Information.
Modify 6.4.2 The function of parallel bus.
Modify 10.1.1 Features.
15
16
9
MAY 13, 2011
MAR. 18, 2010
JUN. 13, 2008
1.3
1.2
1.1
15
5
1. Add pin description of VDD power range.
2. Add section 5.2 Pin Map.
6
3. Modify section 7.2 DC Characteristics of IOH, IOL, RPU & RPD
4. Add section 7.3 Regulator Characteristics.
5. Modify section 9.1 Ordering Information.
6. Add section 9.2 Package Information.
1. Modify section 5. SIGNAL DESCRIPTIONS.
2. Modify section 5.1 PAD Assignment.
Original
.
10
11
13
13
5
JAN. 30, 2008
OCT. 23, 2007
1.0
0.1
6
33
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