GL3224-OIYXX [GENESYS]
USB 3.0 Dual/Single LUN Memory Card Reader Controller;
| 型号： | GL3224-OIYXX |
| 厂家： | 
GENESYS LOGIC |
| 描述： | USB 3.0 Dual/Single LUN Memory Card Reader Controller |
| 文件： | 总25页 (文件大小：691K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Genesys Logic, Inc.
GL3224
USB 3.0 Dual/Single LUN
Memory Card Reader Controller
Datasheet
Revision 1.04
May 07, 2015
GL3224 Datasheet
Copyright
Copyright © 2015 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any
form or by any means without prior written consent of Genesys Logic, Inc.
Ownership and Title
Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein.
Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and
any other propriety rights. No license is granted hereunder.
Disclaimer
All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise,
regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual
property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any
direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys
Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice.
Genesys Logic, Inc.
12F., No. 205, Sec. 3, Beixin Rd., Xindian Dist. 231,
New Taipei City, Taiwan
Tel : (886-2) 8913-1888
Fax : (886-2) 6629-6168
http ://www.genesyslogic.com
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 2
GL3224 Datasheet
Revision History
Revision
Date
01/14/2014 First formal release
Description
1.00
1. Remove CF, xD description in Chapter.2 p.7
2. Modify pin description in p.14
1.01
01/15/2014
1.02
1.03
1.04
06/18/2014 Update SPI FLASH MEMORY SUPPORT LIST in Ch6, p22.
06/24/2014 Revise PACKAGE DIMENSION in Ch7, p23,24
05/07/2015 Modify Ch2 Features
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 3
GL3224 Datasheet
Table of Contents
CHAPTER 1 GENERAL DESCRIPTION .......................................................................... 6
CHAPTER 2 FEATURES...................................................................................................... 7
CHAPTER 3 PIN ASSIGNMENT........................................................................................ 9
3.1 QFN 48 Pinout........................................................................................................... 9
3.2 QFN 32 Pinout......................................................................................................... 10
3.3 Pin Description........................................................................................................ 11
CHAPTER 4 BLOCK DIAGRAM ..................................................................................... 16
4.1 Super Speed and HS/FS PHY ................................................................................ 17
4.2 USB Controller........................................................................................................ 17
4.3 EPFIFO.................................................................................................................... 17
4.4 MCU......................................................................................................................... 17
4.5 MHE (Media Hardware Engine)........................................................................... 17
4.6 Regulator ................................................................................................................. 17
CHAPTER 5 ELECTRICAL CHARACTERISTICS ...................................................... 18
5.1 Temperature Conditions......................................................................................... 18
5.2 Operating Conditions ............................................................................................. 18
5.3 DC Characteristics.................................................................................................. 18
5.4 AC Characteristics of Reset Timing...................................................................... 19
5.4.1 Reset Timing..................................................................................................... 19
5.4.2 SD/MMC Card Clock Frequency................................................................... 20
5.4.3 e•MMC Clock Frequency................................................................................ 21
5.4.4 MS Card Clock Frequency ............................................................................. 21
CHAPTER 6 SPI FLASH MEMORY SUPPORT LIST................................................... 22
CHAPTER 7 PACKAGE DIMENSION ............................................................................ 23
CHAPTER 8 ORDERING INFORMATION.................................................................... 25
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 4
GL3224 Datasheet
List of Figures
Figure 3.1 – QFN48 Pinout Diagram...................................................................................... 9
Figure 3.2 – QFN32 Pinout Diagram.................................................................................... 10
Figure 4.1 – QFN48 Functional Block Diagram.................................................................. 16
Figure 4.2 – QFN32 Functional Block Diagram.................................................................. 16
Figure 5.1 - Timing Diagram of Reset Width ...................................................................... 19
Figure 5.2 - Timing Diagram of Power Good to USB Command Receive Ready ............ 20
Figure 7.1 - QFN 48 Pin Package.......................................................................................... 23
Figure 7.2 - QFN 32 Pin Package.......................................................................................... 24
List of Tables
Table 3.1 - QFN48 Pin Description ....................................................................................... 11
Table 3.2 - QFN32 Pin Description ....................................................................................... 14
Table 5.1 - Absolute Maximum Ratings ............................................................................... 18
Table 5.2 - Operating Conditions.......................................................................................... 18
Table 5.3 - DC Characteristics .............................................................................................. 18
Table 5.4 - Reset Timing......................................................................................................... 20
Table 5.5 - SD/MMC Card Clock Frequency ...................................................................... 20
Table 5.6 - e•MMC Clock Frequency ................................................................................... 21
Table 5.7 - MS Card Clock Frequency ................................................................................. 21
Table 6.1 - SPI Flash Memory Support List ........................................................................ 22
Table 8.1 - Ordering Information ......................................................................................... 25
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 5
GL3224 Datasheet
CHAPTER 1 GENERAL DESCRIPTION
The GL3224 is a crystal-less USB 3.0 Dua/Single LUN card reader controller, it provides 2 LUNs (Logic Unit
Number) which can support various types of memory cards, such as Secure DigitalTM(SD), SDHC, miniSD,
microSD (T-Flash), MultiMediaCardTM (MMC), RS-MMC, MMCmicro, MMCmobile, Memory StickTM (MS),
Memory Stick DuoTM (MS Duo), High Speed Memory StickTM (HS MS), Memory Stick PROTM (MS PRO),
Memory Stick PROTM Duo (MS PRO Duo), Memory Stick PRO-HGTM (MS PRO-HG), MS PRO Micro in one
chip. It also supports SDXC and Memory Stick XC high density memory cards (capacity up to 2TB) and high
speed SD3.0 UHS-I memory cards.
The GL3224 can be configured as single LUN to support e•MMC v4.5, 1/4/8bit data bus, High Speed SDR/
High Speed DDR/ HS200 mode, and it is compatible with e•MMC v5.0.
The GL3224 also provide small package QFN32 (5x5mm) to support single LUN: SD3.0 only for extreme small
PCBA design
The GL3224 integrates a high speed 8051 microprocessor and a high efficiency hardware engine for the best
data transfer performance between USB and various memory card interfaces. It supports Serial Peripheral
Interface (SPI) for firmware upgrade to SPI Flash Memory via USB port. It also integrates 5V to 3.3V and 3.3V
to 1.2V regulators and power MOSFETs which can reduce system BOM cost.
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 6
GL3224 Datasheet
CHAPTER 2 FEATURES
USB specification compliance
-
-
-
-
-
Comply with Universal Serial Bus 3.0 Specification rev. 1.0 (USB 3.0)
Comply with Universal Serial Bus Specification rev. 2.0 (USB 2.0)
Comply with USB Mass Storage Class Specification rev. 1.0
Support USB Mass Storage Class Bulk-Only Transport (BOT)
Support 1 device address and up to 3 endpoints: Control (0) / Bulk Data Read In (1) / Bulk Data Write
Out (2)
-
-
Support 5 Gbps SuperSpeed, 480 Mbps high-speed, and 12 Mbps full-speed transfer rates
Integrated USB building blocks
USB2.0 transceiver macrocell (UTM), Serial Interface Engine (SIE), embedded Power-On Reset
(POR)
Embedded high speed 8051 micro-controller
High efficient DMA hardware engine improves transfer rate between USB and flash card interfaces
Support Ssecure DigitalTM v1.0/ v1.1/ v2.0/ SDHC/ SDXC (Capacity up to 2TB)
Support Secure DigitalTM v3.01 UHS-I (Ultra High Speed): SDR12/ SDR25/ SDR50/ DDR50/ SDR104
TM (MMC)
Support MultiMediaCard
-
-
MMC specification v3.x/ v4.0/ v4.1/ v4.2
x1/ x4/ x8 bit data bus
(
)
Support Embedded MultiMediaCard TM e•MMC
-
-
e•MMC specification v4.3/ v4.4/ v4.5/ v5.0
High Speed SDR/ High Speed DDR/ HS200
Support Memory StickTM/ Memory Stick PROTM/ Memory Stick PRO DuoTM/ Memory Stick PRO Duo
Mark2TM/ Memory Stick MicroTM (M2)/ Memory Stick PRO-HGTM/ Memory Stick PRO-HG DuoTM
Memory Stick PRO-HG Duo HXTM
/
-
-
Compliant with Memory Stick Series Specification: MS v1.43, MS PRO v1.05, MS Micro v1.04 (MS
HG Micro v1.00), MS PRO-HG Duo 1.03, MS XC Duo v1.00, MS XC-HG Duo v1.00, MS XC Micro
v1.00 and MS XC-HG Micro v1.00
Support Read/Write quad data access (512Bytex4) for MS PRO-HG to enhance the transmission rate
Support Serial Peripheral Interface (SPI) for firmware upgrade to SPI Flash Memory via USB interface
Support operation by either MASK ROM or external FW in SPI Flash Memory
On-Chip power MOSFETs for all flash media cards power source
On-chip 5V to 3.3V and 3.3V to 1.2V regulator
On board 25 MHz Crystal driver circuit
Support USB2.0 LPM (Link Power Management)
Support USB3.0 LTM (Latency Tolerance Messaging)
Support USB3.0 U1/U2/U3 low power link state
Pass the USB-IF Test Procedure for SuperSpeed product (TID: 340890039)
Pass WHCK (Windows Hardware Certification Kit) test for Windows 8.1 (Submission ID: 1620543)
Pass WHCK (Windows Hardware Certification Kit) test for Windows 8 (Submission ID: 1620537)
Pass WHQL (Windows Hardware Quality Lab) test for Windows 7 (Submission ID: 1620861)
Support two SD3.0 interfaces with UHS-I: SDR12/ SDR25/ SDR50/ DDR50/ SDR104 bus mode
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 7
GL3224 Datasheet
Support programmable disable MMC interface
Support programmable various LUN (Logic Unit Number): 2 LUNs and 1 LUN
Support programmable SSC (Spread Spectrum Clocking), clock rate in SD, MS memory card interface for
better EMI test effect.
Support programmable LED behavior, Read Only option for specific application
Support power-saving mode to disconnect USB bus by card remove for better power management
Support selective-suspend for entering suspend mode when data transfer pending after several seconds.
Support Over-Current protection mechanism
Available in QFN48 pin package (7x7mm) for 2 LUNs: SD3.0/MSPRO-HG and microSD3.0/M2; 1 LUN
for e•MMC v4.5/ 8bit data bus/ HS200 mode; with SPI I/F for FW upgrade.
Available in QFN32 pin package (5x5mm), 1 LUN: SD3.0; with SPI I/F for FW upgrade.
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 8
GL3224 Datasheet
CHAPTER 3 PIN ASSIGNMENT
3.1 QFN 48 Pinout
36 35 34 33 32 31 30 29 28 27 26 25
S1D1_M1BS
S1D0_M1D1
S1CK_M1D0
S1CM_M1D2
S1D3_M1D3
S1D2_M1CK
VUHS_1
37
38
39
40
41
42
43
44
45
46
47
48
24
S2M2_VCC
S1M1_VCC
VBUS
23
22
21
20
19
18
17
16
15
14
13
LED
SPI_CS
SPI_CK
SPI_MOSI
SPI_MISO
RTERM
AVDD33
X2
GL3224
DVDD33
QFN-48
S1D7_M1D4
S1D6_M1D5
S1D5_M1D6
S1D4_M1D7
(Die Pad must be connected to ground)
X1
1
2
3
4
5
6
7
8
9 10 11 12
Figure 3.1 – QFN48 Pinout Diagram
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 9
GL3224 Datasheet
3.2 QFN 32 Pinout
24 23 22 21 20 19 18 17
DVDD33
VBUS
DVDD33
SD_VCC
GND
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32
LED
SPI_CS
SPI_CK
SPI_MOSI
SPI_MISO
RTERM
SD_WP
SD_CDZ
AVDD33
DM
GL3224
QFN-32
(Die Pad must be connected to
ground)
DP
1
2
3
4
5
6
7
8
Figure 3.2 – QFN32 Pinout Diagram
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 10
GL3224 Datasheet
3.3 Pin Description
Table 3.1 - QFN48 Pin Description
Pin Name
QFN 48
Type
Description
Power/Ground
AVDD12
AVDD33
DVDD12
DVDD33
VBUS
9
6, 15
26
P
P
P
P
P
Analog 1.2V power source
Analog 3.3V power source
Digital 1.2V power source
Digital 3.3V power source
5V power source
25, 34, 44
22
SD 3.0 IO PAD Power, the power source of this pin comes
from the internal regulator of GL3224 and no need of
external power input
SD 3.0 IO PAD Power, the power source of this pin comes
from the internal regulator of GL3224 and no need of
external power input
VUHS_1
VUHS_2
43
33
P
P
S1M1_VCC
S2M2_VCC
GND
23
24
P
P
P
SD/MS card power
SD/MS card power
Ground
3, 12
USB PHY Interface
DP
5
4
A
A
A
A
A
A
USB 2.0 D+
DM
USB 2.0 D-
TXN
TXP
RXN
RXP
7
USB 3.0 TX-
USB 3.0 TX+
USB 3.0 RX-
USB 3.0 RX+
8
10
11
USB reference resistor. This pin is used to control the level of
USB signal. A 680ohm, 1% resistor is recommended to be
laid between RTERM and GND
RTERM
16
A
25MHz x’TAL input. It can be connected to external 25MHz
clock input
X1
X2
13
14
I
B
25MHz x’TAL output
Memory Card Interface
SD write protect
0: write enable
1: write protection
MS insertion detect
0: Card insert
MS1_INS/SD1_WP
2
I, pu
1: No card
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 11
GL3224 Datasheet
SD write protect
0: write enable
1: write protection
MS2_INS/SD2_WP
35
I, pu
MS insertion detect
0: Card insert
1: No card
SD card detect
0: Card insert
1: No card
SD1_CDZ
SD2_CDZ
1
I, pu
I, pu
SD card detect
0: Card insert
1: No card
36
SD data pin
B
O
B
S2D1_M2BS
S2D0_M2D1
S2CK_M2D0
27
28
29
30
31
32
MS/MSP bus state
SD data pin
MS/MSP data signal
SD clock
B
O
B
B,pu
B
MS/MSP data signal
SD command/response
MS/MSP data signal
SD data pin
S2CM_M2D2
S2D3_M2D3
B
B
B
MS/MSP data signal
SD data pin
S2D2_M2CK
S1D1_M1BS
O
MS clock
B
O
SD data pin
37
38
MS/MSP bus state
SD data pin
B
S1D0_M1D1
B
MS/MSP data signal
SD clock
O
39
40
S1CK_M1D0
S1CM_M1D2
B
MS/MSP data signal
SD command/response
B,pu
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 12
GL3224 Datasheet
B
B
B
B
O
B
B
B
B
B
B
B
B
MS/MSP data signal
SD data pin
41
42
45
46
47
48
S1D3_M1D3
S1D2_M1CK
S1D7_M1D4
S1D6_M1D5
S1D5_M1D6
S1D4_M1D7
MS/MSP data signal
SD data pin
MS clock
SD data pin
MS/MSP data signal
SD data pin
MS/MSP data signal
SD data pin
MS/MSP data signal
SD data pin
MS/MSP data signal
Others
LED
21
20
19
17
18
O
O
O
I
Memory card access LED
SPI interface: chip select
SPI interface: clock
SPI_CS
SPI_CK
SPI_MISO
SPI_MOSI
SPI interface: connect to SPI flash data output
SPI interface: connect to SPI flash data input
O
Notation:
Type
O
I
Output
Input
B
Bi-directional
pu
pd
P
internal pull-up when input
internal pull-down when input
Power / Ground
A
Analog
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 13
GL3224 Datasheet
Table 3.2 - QFN32 Pin Description
Pin Name
Pin NO.
Type
Description
Power/Ground
AVDD12
AVDD33
DVDD12
DVDD33
VBUS
3
8,30
17
P
P
P
P
P
Analog 1.2V power source
Analog 3.3V power source
Digital 1.2V power source
Digital 3.3V power source
5V power source
16,25
15
SD 3.0 IO PAD Power, the power source of this pin comes
from the internal regulator of GL3224 and no need of
external power input
VUHSI
24
P
SD_VCC
GND
26
27
P
P
SD card power
Ground
USB PHY Interface
DP
32
31
1
A
A
A
A
A
A
USB 2.0 D+
USB 2.0 D-
DM
TXN
TXP
RXN
RXP
USB 3.0 TX-
USB 3.0 TX+
USB 3.0 RX-
USB 3.0 RX+
2
4
5
USB reference resistor. This pin is used to control the level of
USB signal. A 680ohm, 1% resistor is recommended to be
laid between RREF and GND
RTERM
9
A
25MHz XTAL input. It can be connected to external 25MHz
clock input (Optional)
X1
X2
6
7
I
B
25MHz XTAL output (Optional)
Memory Card Interface
SD_WP
28
29
I, pu
SD write protect
0: write enable
1: write protection
SD card detect
0: Card insert
1: No card
SD_CDZ
I, pu
SD_D1
SD_D0
SD_CK
B
B
O
SD data pin
18
19
20
SD data pin
SD clock
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 14
GL3224 Datasheet
SD_CM
SD_D3
SD_D2
B,pu
B
SD command/response
21
22
23
SD data pin
SD data pin
B
Others
LED
14
13
12
10
11
O
O
O
I
Memory card access LED
SPI interface: chip select
SPI_CS
SPI_CK
SPI interface: clock
SPI_MISO
SPI_MOSI
SPI interface: Connect to SPI flash data output
SPI interface: Connect to SPI flash data input
O
Notation:
Type
O
I
Output
Input
B
Bi-directional
pu
pd
P
internal pull-up when input
internal pull-down when input
Power / Ground
A
Analog
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 15
GL3224 Datasheet
CHAPTER 4 BLOCK DIAGRAM
MHE
Regulator
EPFIFO
5V to 3.3V
EP0 FIFO
3.3V to 1.2V
BULK FIFO
SD3.0/MMC
8-bit I/F
PLL
xHCI
MS-PRO/HG
8-bit I/F
SuperSpeed
PHY
USB
HS/FS
PHY
Controller
EHCI
microSD3.0/M2
4-bit I/F
Control
Register
MCU
SPI
Flash
RAM
ROM
8051
CORE
Figure 4.1 – QFN48 Functional Block Diagram
MHE
Regulator
EPFIFO
5V to 3.3V
EP0 FIFO
3.3V to 1.2V
BULK FIFO
PLL
SD3.0/MMC
8-bit I/F
xHCI
EHCI
SuperSpeed
PHY
USB
HS/FS
PHY
Controller
Control
Register
MCU
SPI
Flash
RAM
ROM
8051
CORE
Figure 4.2 – QFN32 Functional Block Diagram
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 16
GL3224 Datasheet
4.1 Super Speed and HS/FS PHY
The transceiver macro cell is the analog circuitry that handles the low level USB protocol and signaling, and
shifts the clock domain of the data from the USB to one that is compatible with the general logic.
4.2 USB Controller
The USB Controller, which contains the USB PID and address recognition logic, and other sequencing and state
machine logic to handle USB packets and transactions.
4.3 EPFIFO
Endpoint FIFO includes Control FIFO (FIFO0), Bulk In/Out FIFO
EP0 FIFO
Bulk In/Out FIFO It can be in the TX mode or RX mode:
1. It can be transmit/receive 512-byte data of USB 2.0 and 1K-byte data of USB 3.0 continuously.
2. It can be directly accessed by micro-controller
FIFO of control endpoint 0. It is 512-byte FIFO and used for endpoint 0 data transfer.
4.4 MCU
8051 micro-controller inside.
8051 Core
ROM
Compliant with Intel 8051 high speed micro-controller
Firmware code on ROM
SRAM
Internal RAM area for MCU access
4.5 MHE (Media Hardware Engine)
Media Interface: SD/MMC/MS/MS PRO/MS PRO-HG
4.6 Regulator
5V to 3.3V
3.3V to 1.2V
3.3V Power source
1.2V Power source
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 17
GL3224 Datasheet
CHAPTER 5 ELECTRICAL CHARACTERISTICS
5.1 Temperature Conditions
Table 5.1 - Absolute Maximum Ratings
Parameter
Value
-65C to +150 C
Storage Temperature
Operating Temperature
0C to +70 C
5.2 Operating Conditions
Table 5.2 - Operating Conditions
Parameter
Supply Voltage
Value
+4.75V to +5.25V
0V
Ground Voltage
FOSC (Oscillator or Crystal Frequency)
25 MHz 0.03%
5.3 DC Characteristics
Table 5.3 - DC Characteristics
Symbol
VCC
VIH
VIL
Parameter
Supply Voltage
Condition
Min.
4.75
2.0
Typ.
Max.
Unit
V
5.0
5.25
Input High Voltage
Input Low Voltage
Input Leakage Current
Output High Voltage
Output Low Voltage
Output Current High
Output Current Low
Input Pin Capacitance
HS mode
V
0.4
10
V
II
0 < VIN < DVDD
DVDD = 3.3V
-10
2.8
A
V
VOH
VOL
IOH
0.4
V
8
8
mA
mA
pF
IOL
CIN
5
43
120
27
13
65
147
40
mA
mA
mA
mA
mA
mA
mA
U0 state
U1 state
U2 state
INORMAL
SS mode
HS mode
SS mode
IACTIVE
IRESET
U0 state
© 2015 Genesys Logic, Inc. - All rights reserved.
Page 18
GLI Confidential
GL3224 Datasheet
ISUS
Suspend current
1.5K pull-up included
U3 state
0.85
mA
SS Suspend current
Reset Pad pull-up
0.7
46
mA
KΩ
SD_CDZ, SD_WP, MS_INS,
GPIO Pad pull-up
KΩ
46
Rpu
KΩ
KΩ
KΩ
KΩ
SD_CMD pull-up
15
15
15
15
SD_CLK, D[3:0] Pad pull-up
SD_CMD pull-down
Rpd
SD_CLK, D[3:0] Pad pull-down
SD_CMD, SD_CLK, D[3:0]
impedances
Ω
RIMP
50
5.4 AC Characteristics of Reset Timing
5.4.1 Reset Timing
TRST
RSTZ
Figure 5.1 - Timing Diagram of Reset Width
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 19
GL3224 Datasheet
3V
AVDD
USB2.0
Command
SuperSpeed
Termination
Termination ON
2V
RSTZ
Clock
T3
T1
T2
Figure 5.2 - Timing Diagram of Power Good to USB Command Receive Ready
Table 5.4 - Reset Timing
Parameter
Description
Min.
2
Unit
us
TRST
T1
Chip reset sense timing width
AVDD power up to reset de-assert
Reset de-assert to respond USB command ready
Reset de-assert to SuperSpeed termination on
500
95
us
T2
ms
ms
T3
12
5.4.2 SD/MMC Card Clock Frequency
Table 5.5 - SD/MMC Card Clock Frequency
Parameter
FID
Description
Max.
400
25
Unit
KHz
MHz
MHz
MHz
MHz
Clock frequency Identification Mode
Clock frequency Default Speed Mode
FDS
FHS
SD Clock frequency High Speed Mode
MMC Clock frequency High Speed Mode
Clock frequency Ultra High Speed Mode: SDR25
50
FHS
52
FSDR25
50
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 20
GL3224 Datasheet
FDDR50
FSDR50
FSDR104
Clock frequency Ultra High Speed Mode: DDR50
Clock frequency Ultra High Speed Mode: SDR50
Clock frequency Ultra High Speed Mode: SDR104
50
MHz
MHz
MHz
100
208
5.4.3 e•MMC Clock Frequency
Table 5.6 - e•MMC Clock Frequency
Parameter
FID
Description
Max.
400
52
Unit
KHz
MHz
MHz
MHz
Clock frequency Identification Mode
FSDR
Clock frequency High Speed SDR
Clock frequency High Speed DDR
Clock frequency HS200
FDDR
52
FHS200
200
5.4.4 MS Card Clock Frequency
Table 5.7 - MS Card Clock Frequency
Parameter
FDS
Description
Max.
20
Unit
MHz
MHz
MHz
Clock frequency Default Speed Mode
FMSP
Clock frequency MS PRO 4bit Mode
40
FMSPHG
Clock frequency MS PRO HG 8bit Mode
60
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 21
GL3224 Datasheet
CHAPTER 6 SPI FLASH MEMORY SUPPORT LIST
Table 6.1 - SPI Flash Memory Support List
Vendor
Model
GD25Q512
GigaDevice
GD25Q010
GD25Q040
PM25LD512C
PM25LD010
PM25LD010C
PM25LD020
PM25LD020C
W25X05CL
W25X10CL
W25X10BV
W25X20CL
W25X20BV
EN25Q40
PMC
WINBON
EON
MXIC
MX25L1006E
F25L01PA-86PG
F25L01PA-100PG
GT25F512
ESMT
Giantec
Note :
- GL3224 support Page-Program SPI Flash Memory only, does not support Byte-program SPI Flash Memory
- The density of SPI Flash Memory shall be larger than or equal to 512Kbit.
- Firmware file (xxxx.bin) which Genesys Logic provided is only used for Genesys Logic’s Multi-Tool and MP
Tool ISP (In System Programming via USB interface) purpose. If you would like to provide FW to SPI Flash
vendor for pre-loading or Flash ROM writer usage, please contact to GL technical support team.
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 22
GL3224 Datasheet
CHAPTER 7 PACKAGE DIMENSION
Figure 7.1 - QFN 48 Pin Package
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 23
GL3224 Datasheet
Figure 7.2 - QFN 32 Pin Package
© 2015 Genesys Logic, Inc. - All rights reserved.
GLI Confidential
Page 24
GL3224 Datasheet
CHAPTER 8 ORDERING INFORMATION
Table 8.1 - Ordering Information
Part Number
GL3224-ONYXX
GL3224-OIYXX
Package
QFN 48
QFN 32
Green/Wire Material
Green Package + CU Wire
Green Package + CU Wire
Version
XX
Status
Available
Available
XX
© 2015 Genesys Logic, Inc. - All rights reserved.
Page 25
GLI Confidential
©2020 ICPDF网 联系我们和版权申明