概述
规格参数
数据手册GS9002ACPM 概述
GENLINX-TM GS9002A Serial Digital Encoder GENLINX -TM GS9002A串行数字编码器 其他商用集成电路
GS9002ACPM 规格参数
| 生命周期： | Transferred | 包装说明： | QCCJ, LDCC44,.7SQ |
| Reach Compliance Code： | unknown | 风险等级： | 5.64 |
| 商用集成电路类型： | CONSUMER CIRCUIT | JESD-30 代码： | S-PQCC-J44 |
| 端子数量： | 44 | 最高工作温度： | 70 °C |
| 最低工作温度： | 封装主体材料： | PLASTIC/EPOXY | |
| 封装代码： | QCCJ | 封装等效代码： | LDCC44,.7SQ |
| 封装形状： | SQUARE | 封装形式： | CHIP CARRIER |
| 电源： | 5 V | 认证状态： | Not Qualified |
| 子类别： | Other Consumer ICs | 最大压摆率： | 205 mA |
| 表面贴装： | YES | 技术： | BIPOLAR |
| 温度等级： | COMMERCIAL | 端子形式： | J BEND |
| 端子节距： | 1.27 mm | 端子位置： | QUAD |
| Base Number Matches： | 1 |
GS9002ACPM 数据手册
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GENLINX GS9002A
SerialDigitalEncoder
DATA SHEET
FEATURES
DEVICEDESCRIPTION
• fully compatible with SMPTE-259M serial digital
standard
The GS9002A is a monolithic bipolar integrated circuit
designed to serialize SMPTE 125M and SMPTE 244M bit
parallel digital signals as well as other 8 or 10 bit parallel
formats. This device performs the functions of sync detection,
• supports up to four serial bit rates to 400 Mb/s
9
• accepts 8 bit and 10 bit TTL and CMOS
compatible parallel data inputs
parallel to serial conversion, data scrambling (using the X +
4
X
+1 algorithm), 10x parallel clock multiplication and
9
4
conversion of NRZ to NRZI serial data. It supports any of four
selectable serial data rates from 100 Mb/s to over 360 Mb/s.
The data rates are set by resistors and are selected by an
on-board 2:4 decoder having two TTL level input address
lines.
• X + X + 1 scrambler, NRZI converter and sync
detector may be disabled for transparent data
transmission
• pseudo-ECL serial data and clock outputs
• single +5 or -5 volt supply
Otherfeaturessuchasasyncdetectoroutput, asyncdetector
disable input, and a lock detect output are also provided. The
• 713 mW typical power dissipation (including ECL
pull-down loads).
9
4
X + X + 1 scrambler and NRZ to NRZI converter may be
bypassed to allow the output of the parallel to serial converter
to be directly routed to the output drivers.
• 44 pin PLCC packaging
• Pb-free and Green
The GS9002A provides pseudo-ECL outputs for the serial
data and serial clock as well as a single-ended pseudo-ECL
output of the regenerated parallel clock.
APPLICATIONS
• 4ƒSC, 4:2:2 and 360 Mb/s serial digital interfaces for
Video cameras, VTRs, Signal generators
ORDERING INFORMATION
TheGS9002Adirectlyinterfaceswithcabledrivers GS9007A,
GS9008A and GS9009A. The device requires a single +5 volt
or -5 volt supply and typically consumes 713 mW of power
while driving 100 Ω loads. The 44 pin PLCC packaging
assures a small footprint for the complete encoder function.
GS9002ACPM
44 Pin PLCC o°C to 70°C
No
GS9002ACPME3 44 Pin PLCC o°C to 70°C
Yes
SCRAMBLER/
SERIALIZER
26
SELECT
3
SYNC DETECT
6
SYNC DETECT
2:1 MUX
38
DISABLE
SERIAL DATA
7-16
PARALLEL DATA
IN (10 BITS)
SYNC
DETECT
39
SERIAL DATA
INPUT
LATCH
P/S
CONVERTER
SCRAMBLER
NRZ
NRZI
42
43
20
29
SERIAL CLOCK
SERIAL CLOCK
PLD
SCLK
LOCK
DETECT
LOCK DETECT
PHASE
17
CHARGE
PUMP
PCLK IN
REGULATOR CAP
FREQUENCY
DETECT
VCO
22
19
36
35
LOOP FILTER
PCLK OUT
DRS0
DRS1
DATA RATE
SWITCH
DIV BY 10
34
33
32
31
GENERATOR
RVC00
RVC01
RVC02
RVC03
GS9002A
Patent No.5,357,220
FUNCTIONALBLOCKDIAGRAM
Document No. 24149 - 1
Revision Date: June 2004
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum Japan: Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo 160-0023 Japan
Tel: +81 (03) 3349-5501
Fax: +81 (03) 3349-5505
GS9002A -ENCODERDCELECTRICALCHARACTERISTICS
V
= 5V, V = 0V, T = 0°C to 70°C unless otherwise shown
EE A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Supply Voltage
V
P
Operating Range
4.75
5.0
5.25
V
S
Power Consumption
Supply Current
SDO/SDO connected to (VCC-2V)
thru 100ý resistors, PCK OUT
D
-
-
690
710
870
900
mW
mW
connected to V via 1kΩ
EE
Same as above with SCK/SCK
also connected to (V -2V)
thru 100Ω resistors.
CC
I
SDO/SDO connected to (VCC-2V)
thru100ý resistors, PCK OUT
-
155
190
mA
S
connected to V via 1kΩ
EE
Same as above with SCK/SCK
to (V -2V) V thru 100Ω resistors.
-
2.0
-
170
205
-
mA
V
see Figure 15
CC
TTL Inputs-HIGH
TTL Inputs-LOW
Logic Input Current
TTL Outputs-HIGH
TTL Outputs-LOW
V
V
I
T
T
= 25°C
= 25°C
-
IHmin
A
-
2.5
-
0.8
10
-
V
ILmax
INmax
OHmin
OLmax
A
-
µA
V
V
V
T
T
= 25°C
= 25°C
2.4
-
A
-
0.5
V
A
Sync Detect O/P
I
-
-
-
4.0
mA
V
SINK & SOURCE
with respect to V
OSYNC
Serial Outputs
(SDO & SCK)
High
Low
V
V
TA=25°C, RL=100Ω to VCC-2V -0.875
(V -2V) -1.8
-0.7
OH
OL
CC
-
-1.5
V
CC
GS9002A -ENCODERACELECTRICALCHARACTERISTICS
V
= 5V, V = 0V, T = 0°C to 70°C, VLOOP FILTER =2.6 V unless otherwise shown,
CC
EE A
PARAMETER
SYMBOL
BR
CONDITIONS
MIN
100
700
-
TYP
MAX
UNITS
Mb/s
mV p-p
ps
NOTES
Serial Data Outputs
(SDO and SDO)
bit rates
RL = 100Ω to
-
400
1000
-
SDO
(V -2 volts)
CC
signal swing
rise/fall times
jitter
V
850
500
SDO
T
= 25°C
A
t , t
20% - 80%
R
F
t
143 Mb/s
270 Mb/s
-
-
400
300
-
-
ps p-p
ps p-p
see Note 1
see Fig. 16
J(SDO)
Serial Clock Outputs
(SCK and SCK)
frequency
ƒ
R = 100Ω to
100
-
800
1.4
1
400
MHz
mV p-p
ns
see Fig. 12, 13
see Fig. 14
SCK
L
(V -2 volts)
CC
signal swing
V
-
-
-
-
-
SCK
Serial Data to Clock Timing
Lock Time
t
See Figure 9
Data lags Clock
D
t
C
R
= 0.1µF
= 3.9kΩ
1.2
ms
LOCK
LOOP FILT
LOOP FILT
Parallel Clock Output
(PCK OUT)
frequency
ƒ
R = 1kΩ to V
10
-
-
40
-
MHz
ƒ
= ƒSCK/10
PCKO
PCKO
L
EE
signal swing
rise/fall times
jitter
V
800
700
400
mV p-p
ps
PCKO
t , t
-
-
20% - 80%
R
F
t
t
-
-
ps p-p
JPCKO
Parallel Data & Clock Inputs
risetime
T
= 25°C
500
3
-
-
-
-
-
ps
ns
ns
R
A
setup
hold
t
SU
t
3
-
HOLD
NOTE 1: Measured using PCK-IN as trigger source on 1GHz analog oscilloscope.
2 of 11
24149 - 1
≤
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE/UNITS
Supply Voltage
5.5 V
Input Voltage Range (any input)
DC Input Current (any one input)
-V < V < V
EE
I
CC
10 mA
Power Dissipation (V = 5.25 V)
1 W
S
°
Operating Temperature Range
0°C ≤ T ≤ 70 C
A
Storage Temperature Range
-65°C ≤ TS ≤ 150°C
°
Lead Temperature (soldering 10 seconds)
260 C
SYNC
DET.
DIS.
SYNC
DET.
V
V
V
V
V
V
a
V
b
CC2
CC1
5
EE
4
CC3
2
EE
EE
44
SCK SCK
CC2
6
3
43
42
41
40
SDO
SDO
39
7
8
9
PD0
38
37
36
35
34
33
32
31
30
29
PD1
PD2
PD3
PD4
PD5
V
EE
DRS0
10
11
12
13
14
15
16
17
PARALLEL
DATA
INPUTS
DRS1
GS9002A
TOP VIEW
RVC00
RVC01
RVC02
VCO
FREQUENCY
SET
PD6
PD7
PD8
RESISTORS
RVC03
V
EE
PD9
C. REG
PCK IN
18
19
20
21
V
22
23
24
25
V
26
27
V
28
V
V
PCK LOCK
OUT DET.
LOOP
FILT.
NC
V
SSS
EE
CC3
CC3
EE
EE
EE
Fig. 1 GS9002A Encoder Pin Connections
24149 - 1
3 of 11
GS9002ASerialDigitalEncoder -DetailedDeviceDescription
The GS9002A Encoder is a bipolar integrated circuit used to
convert parallel data into a serial format according to the
SMPTE 259M standard. The device encodes both eight and
ten bit TTL-compatible parallel signals producing serial data
rates up to 400 Mb/s. It operates from a single five volt supply
and is packaged in a 44 pin PLCC.
VCO Centre Frequency Selection
The wide VCO pull range allows the PLL to compensate for
variations in device processing, temperature variations and
changesinpowersupplyvoltage,withoutexternaladjustment.
A single external resistor is used to set the VCO current for
each of four centre frequencies as selected by a two bit code
through a 2:4 decoder.
Functional blocks within the device include the input latches,
sync detector, parallel to serial converter, scrambler, NRZ to
NRZIconverter,ECLoutputbuffersfordataandclock,PLLfor
10x parallel clock multiplication and lock detect.
The current setting resistors are connected to the RVCO0
through RVCO3 inputs (34, 33, 32 and 31). The decoder
inputs DRS0 and DRS1 (36, 35) are TTL compatible inputs
and select the four resistors according to the following truth
table.
The parallel data (PD0-PD9) and parallel clock (PCK-IN) are
applied via pins 7 through 17 respectively.
Sync Detector
DRS1
DRS0
Resistor Selected
RVCO0 (34)
RVCO1 (33)
RVCO2 (32)
RVCO3 (31)
The Sync Detector looks for the reserved words 000-003 and
3FC-3FF, in ten bit Hex, or 00 and FF in eight bit Hex, used in
theTRS-IDsyncword. Whentheoccurrenceofeitherallzeros
or ones at inputs PD2-PD9 is detected, the lower two bits PD0
andPD1areforcedtozerosorones,respectively.This makes
the system compatible with eight or ten bit data. For non -
SMPTE standard parallel data, a logic input, Sync Disable (6)
is available to disable this feature.
0
0
1
1
0
1
0
1
Scrambler
A 2:1 multiplexer (MUX) selects either the direct data from the
P/SConverter(Serializer)ortheNRZIdatafromtheScrambler.
This MUX is controlled by the Scrambler/Serializer Select
(SSS) input pin 26. When this input is LOW the MUX selects
the Scrambler output. (This is the mode used for SMPTE
259M data). When this input is HIGH the MUX directly routes
the serialized data to the output buffer with no scrambling or
NRZ to NRZI conversion.
The Scrambler is a linear feedback shift register used to
pseudo-randomize the incoming serial data according to the
fixedpolynomial(X +X +1).ThisminimizestheDCcomponent
in the output serial data stream. The NRZ to NRZI converter
uses another polynomial (X+1) to convert a long sequence of
ones to a series of transitions, minimizing polarity effects.
9
4
Phase Locked Loop
Thelockdetectcircuitdisablestheserialdataoutputwhenthe
loop is not locked by turning off the 2:1 MUX. The Lock Detect
output is available from pin 20 and is HIGH when the loop is
locked.
The PLL performs parallel clock multiplication and provides
the timing signal for the serializer. It is composed of
a phase/frequency detector, charge pump, VCO and a
divide-by-ten counter.
The true and complement serial data, SDO and SDO are
available from pins 38 and 39 while the true and complement
serial clock, SCK and SCK are available from pins 43 and 42
respectively. If the serial clock is not used pins 43 and 42 can
The phase/frequency detector allows a wider capture range
and faster lock time than that which can be achieved with a
phase discriminator alone. The discrimination of frequency
alsoeliminatesharmoniclocking.Withthistypeofdiscriminator,
the PLL can be over-damped for good stability without
sacrificing lock time.
be connected to V
.
CC
The regenerated parallel clock (PCK OUT) is available at pin
19.Thisoutputisasingleendedpseudo-ECLoutputrequiring
a pull down resistor. If regenerated parallel clock is not used
The charge pump delivers a 'charge packet' to the loop filter
which is proportional to the system phase error. Internal
voltage clamps are used to constrain the loop filter voltage
between approximately 1.8 and 3.4 volts.
pin 19 can be connected to V
.
CC
The VCO, constructed from a current-controlled multivibrator,
features operation in excess of 400 Mb/s and a wide pull range
(≈ 40% of centre frequency).
4 of 11
24149 - 1
GS9002A PIN DESCRIPTIONS
PIN NO.
SYMBOL
TYPE
DESCRIPTION
Power Supply: Most negative power supply connection.
1
2
3
V
V
EE
Power Supply: Most positive power supply connection for the PLL and scrambler.
CC3
SYNC DET.
O
TTL output level that detects the occurrence of all zero’s or all one’s at inputs PD2-PD9
and pulses LOW for three PCK-IN durations. Used to detect SMPTE 259M reserved words
(000-003 and 3FC-3FF) in TRS sync word. Parallel data bits PD0 and PD1 are set Low or
High when PD2 - PD9 are Low or High respectively.
4
5
V
Power Supply: Most negative power supply connection.
EE
V
Power Supply: Most positive power supply connection for the input data latches and serializer.
CC1
6
SYNC DET.
DISABLE
I
TTL level input that disables the internal Sync Detector when HIGH. This allows the
GS9002 to serialize 8 or 10 bit non - SMPTE Standard parallel data.
7-16
17
PD0-PD9
PCK-IN
I
I
TTL level inputs of the parallel data words. PD0 is the LSB and PD9 is the MSB.
TTL level input of the Parallel Clock.
18
V
Power Supply: Most negative power supply connection.
EE
19
PCK OUT
O
O
Pseudo-ECL output representing the re-clocked Parallel Clock and is derived from the
internal VCO. The VCO is divided by 10 in order to produce this output.
20
21
22
LOCK DET.
TTL level output which goes HIGH when the internal PLL is locked.
V
Power Supply: Most positive power supply connection for the PLL and scrambler.
CC3
LOOP FILT.
I
Connection for the R-C loop filter components. The loop filter sets the PLL loop
parameters.
23
24
25
26
V
Power Supply: Most negative power supply connection.
EE
NC
V
Power Supply: Most negative power supply connection.
EE
SSS
I
I
Scrambler/Serializer Select. TTL level input that selects scrambled NZRI output when
logic LOW or direct serializer output when logic HIGH.
27
28
29
V
V
Power Supply: Most negative power supply connection.
EE
Power Supply: Most positive power supply connection for the PLL and scrambler.
CC3
C
Compensation RC network for internal voltage regulator that requires decoupling with a series
REG
0.1µF capacitor and 820Ω resistor. Components should be located as close as possible to the pin.
30
31
V
Power Supply: Most negative power supply connection.
EE
R
I
I
I
I
I
VCO Resistor 3: Analog current input used to set the centre frequency of the VCO when
the two Data Rate Select bits (pins 35 and 36) are both set to logic 1. A resistor is
VCO3
connected from this pin to V
.
EE
32
R
VCO Resistor 2: Analog current input used to set the centre frequency of the VCO when
the Data Rate Select Bit 0 (pin 36) is set to logic 0 and the Data Rate Select Bit 1 (pin 35)
is set to logic 1. A resistor is connected from this pin to V
VCO2
VCO1
.
EE
33
R
VCO Resistor 1: Analog current input used to set the centre frequency of the VCO when
the Data Rate Select Bit 0 (pin 36) is set to logic 1 and the Data Rate Select Bit 1 (pin 35)
is set to logic 0. A resistor is connected from this pin to V
.
EE
34
R
VCO Resistor 0: Analog current input used to set the centre frequency of the VCO when
the two Data Rate Select bits (pins 35 and 36) are both set to logic 0. A resistor is
VCO0
connected from this pin to V
.
EE
35,36
DRS0, 1
TTL level inputs to the internal 2:4 demultiplexer used to select one of four VCO frequency
setting resistors (R - R ). (See above)
VCO0
VCO3
24149 - 1
5 of 11
GS9002A PIN DESCRIPTIONS (Continued)
PIN NO
SYMBOL
TYPE
DESCRIPTION
Power Supply: Most negative power supply connection.
37
V
EE
38,39
SDO/SDO
O
Serial Data Outputs (true and inverse). Pseudo-ECL differential outputs representing the serialized
data. These outputs require 390Ω pull down resistors.
40
V
Power Supply: Most positive power supply connection for the Serial Data ECL output buffers.
Power Supply: Most positive power supply connection for the Serial Clock ECL output buffers.
CC2b
41
V
CC2a
42,43
SCK/SCK
O
Serial Clock Outputs (inverse and true). Pseudo-ECL differential outputs of the Serial Clock (10x
Parallel Clock). These outputs require 390Ω pull-down resistors.
44
V
Power Supply: Most negative power supply connection.
EE
INPUT / OUTPUT CIRCUITS
V
CC
V
CC
5k
1k
1k
INPUT
SYNC DET
V
R1
V
EE
V
EE
Fig. 2 Pin No. 3
Fig. 3 Pins No. 6, 7 - 16, 17,26
Sync Detect
Sync Disable, Parallel Data, Parallel Clock,
Scrambler/Serializer Select
V
V
CC
CC
V
CC
1k
1k
10k
PCK OUT
LOCK
DETECT
V
EE
V
EE
Fig. 5 Pin No. 20
Lock Detect
Fig. 4 Pin No. 19
Parallel Clock Out
6 of 11
24149 - 1
I
V
V
VCO
CC
CC
V
=2.15V
R2
V
SELECT
DRS0
DRS1
800
R
VCOX
V
R1
V
EE
Fig. 7 Pins No. 31 - 34
Frequency Setting Registors R
-R
V
VCO0 VCO3
EE
Fig. 6 Pins No. 35, 36
Data Rate Select
V
CC
200
200
SDO
SDO
V
EE
Fig. 8 Pins No. 38, 39, 42, 43
Serial Outputs (Data & Clock)
t
t
CLKL = CLKH
t
t
D
D
SERIAL
DATA OUT
(SD0)
50%
PARALLEL
CLOCK
PLCK
PARALLEL
DATA
PDn
50%
SERIAL
CLOCK OUT
(SCK)
50%
t
t
HOLD
SU
Fig. 9 Waveforms
24149 - 1
7 of 11
4ƒ
sc
DATA
STREAM
T
R
S
T
R
S
T
R
S
ACTIVE VIDEO
& H BLANKING
ACTIVE VIDEO
& H BLANKING
SYNC
DETECT
4:2:2
E
A
V
H
BLNK
E
A
V
H
BLNK
S
A
V
S
A
V
ACTIVE
VIDEO
DATA
STREAM
SYNC
DETECT
PCLK IN
PDN
XXX 3FF 000 000 XXX ••• ••• XXX 3FF 000 000 XXX •••
SYNC
DETECT
Fig. 10 Timing Diagram
+5V
LOOP
+10
LOCKED
L.E.D.
2N4400
0.1
330
82
10k
6x100n
5k
+5V
20
26
6
2,5,21,28,40,41
LOCK SSS SYNC (6x VCC)
7
100
100
100
100
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
PD0
PDI
DET.
DIS.
8
9
38
39
43
42
DATA
SDO
SDO
PD2
PD3
DATA
10
11
12
13
14
15
PD4
PD5
PD6
PD7
PD8
PD9
CLOCK
CLOCK
SCK
SCK
GS9002A
+5V
DATA 8
DATA 9
CLOCK
16
17
36
35
29
1M
PCK IN
DRS0
DRS1
19
22
*150
*10p
PCK-OUT
PARALLEL
CLOCK OUT
LOOP FILT
CREG
RVCO1 RVCO2 RVCO3 RVCO4 VEE
34
33
32
31
1,4
0.1
18,23
25,27
30,37
44
0.1
10k
10k
1
2
3
4
3.9k
1k
820
4x0.1
COMMON
DATA RATE
SELECT DIP
SWITCH
(SEE TRUTH TABLE,
FIG. 2)
+5V
NOTES: Resistors 1, 2, 3 and 4 are used to set the VCO centre frequency. For 143/177 Mb/s ≈ 6kΩ, 270 Mb/s ≈ 2.7kΩ, 360 Mb/s ≈ 1.8kΩ
All resistors in ohms, all capacitors in microfarads unless otherwise stated. represent test points.
*
This RC network is used to slow down fast PCLK risetimes ( ≤ 500ps). It is not required if risetimes exceed 500ps.
Fig. 11 GS9002A Test Circuit
8 of 11
24149 - 1
TYPICAL PERFORMANCE CURVES (V = 5V, T = 25° C unless otherwise shown)
S
A
600
550
500
450
400
350
300
250
200
150
100
50
600
550
500
450
400
350
300
250
200
150
100
50
OPTIMAL
LOOP FILTER
VOLTAGE
RVCO = 1.8k
RVCO = 2.7k
RVCO = 6.3k
V
=2.6V
LOOP
0
0
1
2
3
4
5
6
7
8
9
10
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2 3.4
FREQUENCY SETTING RESISTANCE (ký)
LOOP FILTER VOLTAGE (V)
Fig. 12 VCO Frequency
Fig. 13 VCO Frequency vs Loop Filter Voltage
1000
950
900
850
800
750
700
200
190
180
170
160
150
V = 5.25V
S
V = 5.25V
S
V = 5.0V
S
V = 5.0V
S
V = 4.75V
S
V = 4.75V
S
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Fig. 15 Supply Current
Fig. 14 Serial Output Level (Data & Clock)
800
700
600
500
400
300
200
100
143 Mb/s
270 Mb/s
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2 3.4
LOOP FILTER VOLTAGE (V)
Fig. 16 Output Jitter
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APPLICATIONCIRCUIT
Figure 17 shows a typical application circuit of the GS9002A
driving a GS9007A cable driver.
DOCUMENT
IDENTIFICATION
PRODUCT PROPOSAL
This data has been compiled for market investigation purposes
only, and does not constitute an offer for sale.
ADVANCE INFORMATION NOTE
REVISION NOTES
This product is in development phase and specifications are
subject to change without notice. Gennum reserves the right to
remove the product at any time. Listing the product does not
constitute an offer for sale.
Added lead-free and green information.
For latest product information, visit www.gennum.com
PRELIMINARY
The product is in a preproduction phase and specifications are
subject to change without notice.
CAUTION
ELECTROSTATIC
DATA SHEET
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
The product is in production. Gennum reserves the right to
make changes at any time to improve reliability, function or
design, in order to provide the best product possible.
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright March 1991 Gennum Corporation. All rights reserved. Printed in Canada.
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GS9002ACPM 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| GS9002ACPME3 | GENNUM | GENLINX-TM GS9002A Serial Digital Encoder | 获取价格 |
|
| GS9004 | ETC | 获取价格 |
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| GS9004BCKB | SEMTECH | Consumer Circuit, PDSO14 | 获取价格 |
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| GS9004BCTB | GENNUM | Consumer Circuit, Bipolar, PDSO14, SOIC-14 | 获取价格 |
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| GS9004C | GENNUM | Serial Digital Cable Equalizer | 获取价格 |
|
| GS9004CCKB | GENNUM | Serial Digital Cable Equalizer | 获取价格 |
|
| GS9004CCTB | GENNUM | Serial Digital Cable Equalizer | 获取价格 |
|
| GS9004D | GENNUM | GENLINX-TM GS9004D Serial Digital Cable Equalizer | 获取价格 |
|
| GS9004DCKB | GENNUM | GENLINX-TM GS9004D Serial Digital Cable Equalizer | 获取价格 |
|
| GS9004DCKBE3 | GENNUM | GENLINX-TM GS9004D Serial Digital Cable Equalizer | 获取价格 |
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