NJ8821 [GE]
FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE) WITH RESETTABLE COUNTERS; 频率合成器（微处理器接口）与复位系列计数器
| 型号： | NJ8821 |
| 厂家： | 
GENERAL ELECTRIC COMPANY |
| 描述： | FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE) WITH RESETTABLE COUNTERS |
| 文件： | 总5页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS3278-1.3
NJ8821
FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE)
WITH RESETTABLE COUNTERS
T
he NJ8821 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-holdcomparators,10-bitprogrammable‘M’counter,
7-bit programmable ‘A’ counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented as eight 4-bit words under external control
from a suitable microprocessor..
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
PDA
PDB
LD
CH
RB
MC
DS2
DS1
DS0
PE
F
IN
V
SS
NJ8821
It is intended to be used in conjunction with a two-modulus
prescaler such as the SP8710 series to produce a universal
binary coded synthesiser.
V
DD
OSC IN
OSC OUT
D0
The NJ8821 is available in Plastic DIL (DP) and Miniature
Plastic DIL (MP) packages, both with operating temperature
NC
D3
range of 230
Ceramic DIL package with operating temperature range of
240 C to 185 C.
°C to 170°C. The NJ8821MA is available only in
DP20, MP20
DG20
D1
D2
°
°
FEATURES
Low Power Consumption
■ Microprocessor Compatible
Fig.1 Pin connections - top view
■
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD2VSS
Input voltage
20·5V to 7V
■
■
High Performance Sample and Hold Phase Detector
>10MHz Input Frequency
7V
Open drain output, pin 3
V
SS20·3V to VDD10·3V
All other pins
ORDERING INFORMATION
Storage temperature
265°C to 1150°C
NJ8821 BA DP Plastic DIL Package
NJ8821 BA MP Miniature Plastic DIL Package
NJ8821 MA DG Ceramic DIL Package
(DG package, NJ8821MA)
255°C to 1125°C
(DP and MP packages, NJ8821)
Storage temperature
DATA SELECT INPUTS
DS0 DS1 DS2
RB
19
CH
20
15 16 17
TO
INTERNAL
LATCHES
14
LATCH SELECT
LOGIC
PROGRAM
ENABLE (PE)
f
REFERENCE COUNTER
(11BITS)
r
7
8
SAMPLE/HOLD
PHASE
DETECTOR
42
OSC IN
1
PDA
OSC OUT
LATCH 6 LATCH 7 LATCH 8
FREQUENCY/
PHASE
DETECTOR
2
3
PDB
9
D0
10
11
12
DATA
INPUTS
D1
D2
D3
LOCK DETECT (LD)
V
SS
LATCH 4 LATCH 5
LATCH 1 LATCH 2 LATCH 3
f
4
v
‘A’ COUNTER
(7 BITS)
‘M’ COUNTER
(10 BITS)
F
IN
6
V
DD
MODULUS
CONTROL
18
CONTROL LOGIC
5
OUTPUT (MC)
V
SS
Fig.2 Block diagram
NJ8821
ELECTRICAL CHARACTERISTICS AT VDD = 5V
Test conditions unless otherwise stated:
V
DD–VSS=5V ±0·5V. Temperature range NJ8821 BA: –30°C to +70°C; NJ8821MA: –40°C to +85°C
DC Characteristics
Value
Typ.
Characteristic
Units
Conditions
Max.
Min.
0 to 5V
square
wave
Supply current
3·5
0·7
5·5
1·5
mA
mA
f
f
, fFIN = 10MHz
, fFIN = 1·0MHz
osc
osc
OUTPUT LEVELS
Modulus Control Output (MC)
High level
4·6
V
V
I
SOURCE = 1mA
Low level
0·4
ISINK = 1mA
Lock Detect Output (LD)
Low level
Open drain pull-up voltage
PDB Output
0·4
7
V
V
ISINK = 4mA
High level
Low level
4·6
V
V
I
SOURCE = 5mA
0·4
ISINK = 5mA
3-state leakage current
±0·1
µA
INPUT LEVELS
Data Inputs (D0-D3)
High level
Low level
Program Enable Input (PE)
High level
Low level
Data Select Inputs (DS0-DS2)
High level
4·25
4·25
4·25
V
V
TTL compatible
See note 1
0·4
V
V
0·75
0·75
V
V
Low level
AC Characteristics
Characteristic
Value
Typ.
Units
Conditions
Max.
Min.
FIN and OSC IN input level
200
mVRMS 10MHz AC-coupled sinewave
Max. operating frequency, fFIN and f
10·6
MHz
Input squarewave VDD to VSS
See note 4.
,
osc
Propagation delay, clock to MC
Strobe pulse width, tW(ST)
Data set-up time, tDS
Data hold time, tDH
Latch address set-up time, tSE
Latch address hold time, tHE
30
50
ns
µs
µs
µs
µs
See note 2.
2
1
1
1
1
See Fig. 6
µs
Digital phase detector propagation delay
Gain programming resistor, RB
Hold capacitor, CH
Output resistance, PDA
Digital phase detector gain
500
0·4
ns
kΩ
nF
kΩ
V/Rad
5
See note 3.
1
5
NOTES
1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant
to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs, typically.
4. Operation at up to 15MHz is possible with a full logic swing but is not guaranteed.
2
NJ8821
PIN DESCRIPTIONS
Pin no.
Description
Name
PDA
1
Analog output from the sample and hold phase comparator for use as a ‘fine’ error signal. Output at
(VDD2VSS)/2 when the system is in lock. Voltage increases as f phase lead increases; voltage
v
decreases as f phase lead increases. Output is linear over only a narrow phase window, determined
r
by gain (programmed by RB).
PDB
2
Three-state output from the phase/frequency detector for use as a ‘coarse’ error signal.
f . f or f leading: positive pulses with respect to the bias point VBIAS
v
r
v
f , f or f leading: negative pulses with respect to the bias point VBIAS
v
r
r
f = f and phase error within PDA window: high impedance.
v
r
LD
FIN
3
4
An open-drain lock detect output at low level when phase error is within PDA window (in lock); high
impedance at all other times.
The input to the main counters, normally driven from a prescaler, which may be AC-coupled or, when
a full logic swing is available, may be DC-coupled.
VSS
VDD
5
6
Negative supply (ground).
Positive supply.
OSC IN/
OSC OUT
7, 8
These pins form an on-chip reference oscillator when a series resonant crystal is connected across
them. Capacitors of appropriate value are also required between each end of the crystal and ground
to provide the necessary additional phase shift. An external reference signal may, alternatively, be
applied to OSC IN. This may be a low-level signal, AC-coupled, or if a full logic swing is available it may
be DC-coupled. The program range of the reference counter is 3 to 2047, with the division ratio being
twice the programmed number.
9,10, 11, 12
Data on these inputs is transferred to the internal data latches during the appropriate data read time
slot. D3 is MSB, D0 is LSB.
D0-D3
NC
PE
13
14
No connection
This pin is used as a strobe for the data. A logic ‘1’ on this pin transfers data from the D0-D3 pins to
the internal latch addressed by the data select (DS0-DS2) pins . A logic ‘0’ disables the data inputs.
15, 16, 17 DS0-DS2 Data select inputs for addressing the internal data latches
18
Moduluscontroloutputforcontrollinganexternaldual-modulusprescaler.MCwillbelowatthebeginning
of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes high and
remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters are reset.
This gives a total division ratio of MP1A, where P and P11 represent the dual-modulus prescaler
values. The program range of the ‘A’ counter is 0-127 and therefore can control prescalers with a
division ratio up to and including 4128/129. The programming range of the ‘M’ counter is 8-1023
and, for correct operation, M>A. Where every possible channel is required, the minimum total division
ratio should be P 22P.
MC
19
20
RB
CH
An external sample and hold phase comparator gain programming resistor should be connected
between this pin and VSS
.
An external hold capacitor should be connected between this pin and VSS
.
8
2·0
V
= 5V
DD
V
= 5V
DD
F
= LOW FREQUENCY
7
6
5
4
3
2
1
IN
OSC IN, F = 0V TO 5V SQUARE WAVE
IN
0V TO 5V SQUARE WAVE
1·5
1·0
0·5
OSC IN
10MHz
1MHz
F
IN
TOTAL SUPPLY CURRENT IS
THE SUM OF THAT DUE TO F
AND OSC IN
IN
0·2 0·4
0·6
0·8
1·0
1·2
1·4
1·6
1
2
3
4
5
6
7
8
9
10
INPUT LEVEL (V RMS)
INPUT FREQUENCY (MHz)
Fig. 3 Typical supply current v. input frequency
Fig. 4 Typical supply current v. input level, OSC IN
3
NJ8821
PROGRAMMING
Timing is generated externally, normally from a
microprocessor, and allows the user to change the data in
selected latches as defined by the data map Fig.5. The PE pin
is used as a strobe for the data: taking PE high causes data to
be transferred from the data pins (D0-D3) into the addressed
latch. Following the falling edge of PE, the data is retained in
the addressed latch and the data inputs are disabled. Data
transfer from all internal latches into the counters occurs
simultaneously with the transfer of data into latch 1, which
would therefore normally be the last latch addressed during
each channel change. Timing information for this mode of
operation is given in Fig. 6.
10ms. If shorter lock-up times are are required when making
only small changes in frequency, the GPS NJ8823 (with non-
resettable counters) should be considered.
DS2 DS1 DS0
D3
D2
D1
D0
WORD
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
M1
M5
M9
A3
-
R3
R7
-
M0
M4
M8
A2
-
-
1
2
3
4
5
6
7
8
M3
M7
A1
A5
R1
R5
R9
M2
M6
A0
A4
R0
R4
R8
A6
R2
R6
R10
When re-programming, a reset to zero state is followed by
reloading with the new counter values. This means that the
synthesiser loop lock-up time is well defined and less than
Fig. 5 Data map
DS0-DS2
PE
D0 - D3
t
t
DS
DH
t
t
t
HE
SE
W(ST)
Fig. 6 Timing diagram
PHASE COMPARATORS
The digital phase/frequency detector drives a three-state
output, PDB, which provides a ‘coarse’ error signal to enable
fast switching between channels. The PDB output is active
until the phase error is within the sample and hold phase
detector, PDA, window, whenPDB becomeshighimpedance.
Phase-lock is indicated at this point by a low level on LD. The
sample and hold phase detector provides a ‘fine’ error signal
to give further phase adjustment and to hold the loop in lock.
An internally generated ramp, controlled by the digital
output from both the reference and main divider chains, is
sampled at the reference frequency to give the ‘fine’ error
signal, PDA. When in phase lock, this output would be typically
at (VDD2VSS)/2 and any offset from this would be proportional
to phase error. The relationship between this offset and the
phase error is the phase comparator gain, which is
programmable with an external resistor, RB. An internal 50pF
capacitor is used in the sample and hold comparator.
CRYSTAL OSCILLATOR
When using the internal oscillator, the stability may be
enhanced at high frequencies by the inclusion of a resistor
between pin 8 (OSC OUT) and the other components. A value
of 150-270Ω is advised.
PROGRAMMING/POWER UP
Data and signal input pins should not have input applied to
them prior to the application of VDD, as otherwise latch-up may
occur.
4
NJ8821
HEADQUARTERS OPERATIONS
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire SN2 2QW, United Kingdom.
Tel: (0793) 518000
CUSTOMER SERVICE CENTRES
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax : (1) 64 46 06 07
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• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
Fax: (0793) 518411
• NORTH AMERICA Scotts Valley, USA Tel (408) 438 2900 Fax: (408) 438 7023.
• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
• SWEDEN Stockholm, Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
• TAIWAN, ROC Taipei Tel: 886 2 5461260. Fax: 886 2 71900260
• UK, EIRE, DENMARK, FINLAND & NORWAY
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.
Tel: (408) 438 2900
Swindon Tel: (0793) 518510 Fax : (0793) 518582
These are supported by Agents and Distributors in major countries world-wide.
Fax: (408) 438 5576
GEC Plessey Semiconductors 1992
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