GD25B127DFJS [GIGADEVICE]
3.3V Uniform Sector Dual and Quad Serial Flash;![GD25B127DFJS](http://pdffile.icpdf.com/pdf2/p00322/img/icpdf/GD25B127D_1979818_icpdf.jpg)
型号: | GD25B127DFJS |
厂家: | ![]() |
描述: | 3.3V Uniform Sector Dual and Quad Serial Flash |
文件: | 总65页 (文件大小:1227K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
GD25B127D
DATASHEET
1
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
Contents
1. FEATURES ..................................................................................................................................................4
2. GENERAL DESCRIPTION ..........................................................................................................................5
3. MEMORY ORGANIZATION.........................................................................................................................7
4. DEVICE OPERATION..................................................................................................................................8
5. DATA PROTECTION ...................................................................................................................................9
6. STATUS REGISTER ..................................................................................................................................11
7. COMMANDS DESCRIPTION ....................................................................................................................13
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
WRITE ENABLE (WREN) (06H).............................................................................................................16
WRITE DISABLE (WRDI) (04H)..............................................................................................................16
WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ........................................................................17
READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H)......................................................................17
WRITE STATUS REGISTER (WRSR) (01H OR 31H OR 11H)....................................................................18
READ DATA BYTES (READ) (03H) ........................................................................................................18
READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH).....................................................................19
DUAL OUTPUT FAST READ (3BH) ..........................................................................................................19
QUAD OUTPUT FAST READ (6BH) .........................................................................................................20
7.10. DUAL I/O FAST READ (BBH) .................................................................................................................20
7.11. QUAD I/O FAST READ (EBH).................................................................................................................22
7.12. QUAD I/O WORD FAST READ (E7H) ......................................................................................................23
7.13. SET BURST WITH WRAP (77H) ..............................................................................................................25
7.14. PAGE PROGRAM (PP) (02H) .................................................................................................................26
7.15. QUAD PAGE PROGRAM (32H)................................................................................................................27
7.16. SECTOR ERASE (SE) (20H) ..................................................................................................................28
7.17. 32KB BLOCK ERASE (BE) (52H)...........................................................................................................28
7.18. 64KB BLOCK ERASE (BE) (D8H) ..........................................................................................................29
7.19. CHIP ERASE (CE) (60/C7H)..................................................................................................................29
7.20. DEEP POWER-DOWN (DP) (B9H)..........................................................................................................30
7.21. RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) ...............................................31
7.22. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ..............................................................................32
7.23. READ MANUFACTURE ID/ DEVICE ID DUAL I/O (92H) .............................................................................33
7.24. READ MANUFACTURE ID/ DEVICE ID QUAD I/O (94H).............................................................................34
7.25. READ IDENTIFICATION (RDID) (9FH) .....................................................................................................35
7.26. PROGRAM/ERASE SUSPEND (PES) (75H)..............................................................................................36
7.27. PROGRAM/ERASE RESUME (PER) (7AH)...............................................................................................36
7.28. READ UNIQUE ID (4BH) ........................................................................................................................37
7.29. ERASE SECURITY REGISTERS (44H)......................................................................................................37
7.30. PROGRAM SECURITY REGISTERS (42H).................................................................................................38
7.31. READ SECURITY REGISTERS (48H)........................................................................................................39
7.32. ENABLE RESET (66H) AND RESET (99H) ...............................................................................................40
2
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.33. READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH)........................................................................40
8. ELECTRICAL CHARACTERISTICS .........................................................................................................45
8.1. POWER-ON TIMING ..........................................................................................................................45
8.2. INITIAL DELIVERY STATE.................................................................................................................45
8.3. ABSOLUTE MAXIMUM RATINGS .....................................................................................................45
8.4. CAPACITANCE MEASUREMENT CONDITIONS..............................................................................46
8.5. DC CHARACTERISTICS....................................................................................................................47
8.6. AC CHARACTERISTICS....................................................................................................................50
9. ORDERING INFORMATION......................................................................................................................54
9.1.
10.
VALID PART NUMBERS ..........................................................................................................................55
PACKAGE INFORMATION....................................................................................................................57
10.1. PACKAGE SOP8 208MIL ......................................................................................................................57
10.2. PACKAGE VSOP8 208MIL....................................................................................................................58
10.3. PACKAGE DIP8 300MIL........................................................................................................................59
10.4. PACKAGE SOP16 300MIL ....................................................................................................................60
10.5. PACKAGE WSON8 (6*5MM)..................................................................................................................61
10.6. PACKAGE WSON8 (8*6MM)..................................................................................................................62
10.7. PACKAGE TFBGA-24BALL (6*4 BALL ARRAY) .......................................................................................63
11.
REVISION HISTORY..............................................................................................................................64
3
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
1. FEATURES
◆
128M-bit Serial Flash
◆
Fast Program/Erase Speed
- 16384K-byte
- Page Program time: 0.5ms typical
- Sector Erase time: 50ms typical
- Block Erase time: 0.16/0.3s typical
- Chip Erase time: 50s typical
- 256 bytes per programmable page
◆
Standard, Dual, Quad SPI
- Standard SPI: SCLK, CS#, SI, SO
- Dual SPI: SCLK, CS#, IO0, IO1
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆
◆
◆
Flexible Architecture
- Uniform Sector of 4K-byte
- Uniform Block of 32/64K-byte
◆
High Speed Clock Frequency
- 104MHz for Standard and Dual SPI fast read with 30PF load
- Dual I/O Data transfer up to 208Mbits/s
- Quad I/O Data transfer up to 416Mbits/s
Low Power Consumption
- 20uA typical stand-by current
- 1uA typical deep-power-down current
◆ Software Protection
Advanced Security Features
- Write protect all/portion of memory via software
- 128-bit Unique ID for each device
- 3*1024-Byte Security Registers With OTP Locks
- Discoverable parameters (SFDP) register
◆ Allows XIP (execute in place) Operation
- Continuous Read With 8/16/32/64-byte Wrap
◆
Package Information
- SOP8 (208mil)
◆ Minimum 100,000 Program/Erase Cycles
- VSOP8 (208mil)
- SOP16 (300mil)
- DIP8 (300mil)
◆
Data Retention
- 20-year data retention typical
- WSON8 (8*6mm)
- WSON8 (6*5mm)
- TFBGA-24 (6*4 ball array)
◆
Single Power Supply Voltage
- Full voltage range: 2.7~3.6V
4
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
2. GENERAL DESCRIPTION
The GD25B127D (128M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2, and I/O3. The Dual I/O data is transferred
with speed of 208Mbits/s and the Quad I/O & Quad output data is transferred with speed of 416Mbits/s.
CONNECTION DIAGRAM
CS#
1
2
3
4
8
7
6
5
VCC
CS#
1
2
3
8
7
VCC
IO3
SO
(IO1)
SO
(IO1)
IO3
Top View
Top View
IO2
SCLK
IO2
6 SCLK
SI
(IO0)
SI
5
VSS
VSS 4
(IO0)
8–LEAD SOP/DIP
8–LEAD WSON
1
2
3
4
5
6
7
8
IO3
16
15
14
13
12
11
10
9
SCLK
Top View
SI
VCC
NC(1)
NC
(IO0)
4
3
2
1
NC VCC
NC
NC
IO2
NC
IO3
NC
NC
NC
NC
VSS
IO2
SI
VSS
NC
NC
NC
NC
NC
NC
Top View
(IO0)
NC
SO
SCLK CS#
(IO1)
NC
CS#
NC
A
NC
B
NC
NC
NC
E
NC
F
SO
(IO1)
C
D
16-LEAD SOP
24-BALL TFBGA
Note:
1. Only for special order, Pin 3 of SOP16 package is RESET# pin. Please contact GigaDevice for detail.
PIN DESCRIPTION
Pin Name
I/O
I
Description
CS#
Chip Select Input
SO (IO1)
IO2
I/O
I/O
Data Output (Data Input Output 1)
Data Input Output 2
Ground
VSS
SI (IO0)
SCLK
IO3
I/O
I
Data Input (Data Input Output 0)
Serial Clock Input
Data Input Output 3
Power Supply
I/O
VCC
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
5
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
BLOCK DIAGRAM
Status
Register
IO2
IO3
Flash
Memory
High Voltage
Generators
SPI
Command &
Control Logic
SCLK
CS#
Page Address
Latch/Counter
SI(IO0)
SO(IO1)
Column Decode And
256-Byte Page Buffer
Byte Address
Latch/Counter
6
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
3. MEMORY ORGANIZATION
GD25B127D
Each device has
Each block has
Each sector has
Each page has
16M
64K
64/32K
256/128
16/8
4K
16
-
256
bytes
pages
sectors
blocks
-
-
-
4096
256/512
-
-
UNIFORM BLOCK SECTOR ARCHITECTURE
GD25B127D 64K Bytes Block Sector Architecture
Block
Sector
Address range
4095
……
4080
4079
……
4064
……
……
……
……
……
……
47
FFF000H
……
FFFFFFH
……
255
FF0000H
FEF000H
……
FF0FFFH
FEFFFFH
……
254
……
……
2
FE0000H
……
FE0FFFH
……
……
……
……
……
……
……
……
……
……
……
02F000H
……
02FFFFH
……
……
32
020000H
01F000H
……
020FFFH
01FFFFH
……
31
1
……
16
010000H
00F000H
……
010FFFH
00FFFFH
……
15
0
……
0
000000H
000FFFH
7
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
4. DEVICE OPERATION
SPI Mode
Standard SPI
The GD25B127D features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the
rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25B127D supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read”
(3BH and BBH) commands. These commands allow data to be transferred to or from the device at twice the rate of the
standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25B127D supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”,
“Quad I/O Word Fast Read” (6BH,EBH,E7H)commands. These commands allow data to be transferred to or from the device
at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O
pins: IO0 and IO1.
8
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
5. DATA PROTECTION
The GD25B127D provide the following data protection methods:
◆
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
-Software reset (66H+99H)
◆
◆
Software Protection Mode:
-The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory array that can be read
but not change.
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command and reset command (66H+99H).
Table 5.1. GD25B127D Protected area size (CMP=0)
Status Register Content
Memory Content
Addresses
BP4
X
BP3
X
BP2
0
BP1
0
BP0
0
Blocks
NONE
Density
NONE
256KB
512KB
1MB
Portion
NONE
NONE
0
0
0
0
1
252 to 255
248 to 255
240 to 255
224 to 255
192 to 255
128 to 255
FC0000H-FFFFFFH
F80000H-FFFFFFH
F00000H-FFFFFFH
E00000H-FFFFFFH
C00000H-FFFFFFH
800000H-FFFFFFH
000000H-03FFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-1FFFFFH
000000H-3FFFFFH
000000H-7FFFFFH
000000H-FFFFFFH
FFF000H-FFFFFFH
FFE000H-FFFFFFH
FFC000H-FFFFFFH
FF8000H-FFFFFFH
FF8000H-FFFFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
2MB
0
0
1
0
1
4MB
0
0
1
1
0
8MB
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
X
0
1
0
1
X
0 to 3
0 to 7
0 to 15
0 to 31
0 to 63
0 to 127
0 to 255
255
256KB
512KB
1MB
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
2MB
4MB
8MB
16MB
4KB
Top Block
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
255
8KB
255
16KB
32KB
32KB
4KB
255
255
0
0
8KB
0
16KB
32KB
0
9
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
1
1
1
1
0
0
000000H-007FFFH
32KB
Bottom Block
Table 5.2. GD25B127D Protected area size (CMP=1)
Memory Content
Status Register Content
BP4
X
BP3
X
BP2
0
BP1
0
BP0
0
Blocks
0 to 255
0 to 251
0 to 247
0 to 239
0 to 223
0 to 191
0 to 127
Addresses
Density
Portion
000000H-FFFFFFH
000000H-FBFFFFH
000000H-F7FFFFH
000000H-EFFFFFH
000000H-DFFFFFH
000000H-BFFFFFH
000000H-7FFFFFH
ALL
ALL
0
0
0
0
1
16128KB
15872KB
15MB
Lower 63/64
Lower 31/32
Lower 15/16
Lower 7/8
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
14MB
0
0
1
0
1
12MB
Lower 3/4
0
0
1
1
0
8MB
Lower 1/2
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
X
0
1
0
1
X
0
4 to 255
8 to 255
16 to 255
32 to 255
64 to 255
128 to 255
NONE
040000H-FFFFFFH
080000H-FFFFFFH
100000H-FFFFFFH
200000H-FFFFFFH
400000H-FFFFFFH
800000H-FFFFFFH
NONE
16128KB
15872KB
15MB
Upper 63/64
Upper 31/32
Upper 15/16
Upper 7/8
14MB
12MB
Upper 3/4
8MB
Upper 1/2
NONE
NONE
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
000000H-FFEFFFH
000000H-FFDFFFH
000000H-FFBFFFH
000000H-FF7FFFH
000000H-FF7FFFH
001000H-FFFFFFH
002000H-FFFFFFH
004000H-FFFFFFH
008000H-FFFFFFH
008000H-FFFFFFH
16380KB
16376KB
16368KB
16352KB
16352KB
16380KB
16376KB
16368KB
16352KB
16352KB
L-4095/4096
L-2047/2048
L-1023/1024
L-511/512
L-511/512
U-4095/4096
U-2047/2048
U-1023/1024
U-511/512
U-511/512
10
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
6. STATUS REGISTER
S23
S22
S21
S20
S19
S18
S17
S16
Reserved
DRV1
DRV0
Reserved
Reserved
Reserved
Reserved
Reserved
S15
S14
S13
LB3
S12
LB2
S11
LB1
S10
S9
S8
SUS1
CMP
SUS2
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Chip
Erase (CE) command is executed, if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block Protect
(BP2, BP1, and BP0) bits are 1 and CMP=1.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, power supply lock-down or one time programmable
protection.
SRP1 SRP0
Status Register
Description
The Status Register can be written to after a Write Enable
command, WEL=1. (Default)
0
1
0
0
1
Software Protected
Status Register is protected and cannot be written to again
until the next Power-Down, Power-Up cycle.
Status Register is permanently protected and cannot be
written to.
Power Supply Lock-Down(1)(2)
One Time Program(2)
1
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact GigaDevice for details.
QE bit.
The Quad Enable (QE) bit is a non-volatile bit in the Status Register that allows Quad operation. The default value of
QE bit is 1 and it cannot be changed, so that the Quad IO2 and IO3 pins are enabled all the time.
11
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
LB3, LB2, LB1 bits.
The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the
write protect control and status to the Security Registers. The default state of LB3-LB1are 0, the security registers are
unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time
Programmable, once they are set to 1, the Security Registers will become read-only permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the BP4-BP0
bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details.
The default setting is CMP=0.
SUS1, SUS2 bits
The SUS1 and SUS2 bits are read only bits in the status register (S15 and S10) that are set to 1 after executing an
Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the
SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command, software reset
(66H+99H) command as well as a power-down, power-up cycle.
DRV1, DRV0 bits
The DRV1&DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0
Driver Strength
100%
00
01
10
11
75%
50% (default)
25%
12
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, with
most significant bit first on SI, and each bit is latched on the rising edges of SCLK.
See Table 7.1., every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the
command sequence has been completed. For the command of Read, Fast Read, Read Status Register or Release from
Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read
instruction can be completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high
to return to deselected status.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command
is rejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS# being driven
low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and
WEL will not be reset.
Table 7.1. Commands (Standard/Dual/Quad SPI)
Command Name
Byte 1
06H
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
Write Enable
Write Disable
04H
Volatile SR
50H
Write Enable
Read Status Register-1
Read Status Register-2
Read Status Register-3
Write Status Register-1
Write Status Register-2
Write Status Register-3
Read Data
05H
35H
15H
01H
31H
11H
03H
0BH
3BH
(S7-S0)
(S15-S8)
(S23-S16)
S7-S0
(continuous)
(continuous)
S15-S8
S23-S16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
(D7-D0)
dummy
dummy
(Next byte) (continuous)
Fast Read
(D7-D0)
(D7-D0)(1)
(continuous)
(continuous)
Dual Output
Fast Read
Dual I/O
Fast Read
BBH
6BH
EBH
E7H
A23-A8(2)
A23-A16
A7-A0
(D7-D0)(1)
A7-A0
(continuous)
(continuous)
(continuous)
(continuous)
M7-M0(2)
Quad Output
Fast Read
A15-A8
dummy
(D7-D0)(3)
Quad I/O
Fast Read
A23-A0
M7-M0(4)
dummy(5)
dummy(6)
(D7-D0)(3)
(D7-D0)(3)
Quad I/O Word
Fast Read(7)
A23-A0
M7-M0(4)
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
Page Program
Quad Page Program
Sector Erase
02H
32H
20H
52H
D8H
C7/60
H
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0
D7-D0
Next byte
Block Erase(32K)
Block Erase(64K)
Chip Erase
Enable Reset
Reset
66H
99H
13
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
Set Burst with Wrap
77H
dummy(9)
W7-W0
Program/Erase
Suspend
75H
Program/Erase Resume 7AH
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
ABH
dummy
dummy
dummy
dummy
(DID7-
DID0)
(continuous)
ABH
Deep Power-Down
Manufacturer/
Device ID
B9H
90H
dummy
A23-A8
00H
(MID7-
MID0)
(DID7-
DID0)
(continuous)
(continuous)
Manufacturer/
Device ID by Dual I/O
(MID7-
MID0)
(DID7-
DID0)
A7-A0,
M7-M0
92H
Manufacturer/
Device ID by Quad I/O
dummy
(10)(MID7-
MID0)
(DID7-
DID0)
A23-A0,
M7-M0
94H
9FH
(continuous)
Read Identification
Read Unique ID
(MID7-
MID0)
(JDID15-
JDID8)
(JDID7-
JDID0)
(continuous)
(continuous)
(UID7-
UID0)
00H
00H
00H
dummy
dummy
4BH
5AH
Read Serial Flash
Discoverable Parameter
Erase Security
Registers(8)
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
(D7-D0)
(continuous)
44H
42H
48H
Program Security
Registers(8)
D7-D0
D7-D0
Read Security
Registers(8)
dummy
(D7-D0)
NOTE:
1. Dual Output data
IO0=(D6,D4,D2,D0)
IO1=(D7,D5,D3,D1)
2. Dual Input Address
IO0=A22,A20,A18,A16,A14,A12,A10,A8
IO1=A23,A21,A19,A17,A15,A13,A11,A9
A6,A4,A2,A0,M6,M4,M2,M0
A7,A5,A3,A1,M7,M5,M3,M1
3. Quad Output Data
IO0=(D4,D0,…..)
IO1=(D5,D1,…..)
IO2=(D6,D2,…..)
IO3=(D7,D3,…..)
4. Quad Input Address
IO0=A20,A16,A12,A8, A4,A0,M4,M0
IO1=A21,A17,A13,A9, A5,A1,M5,M1
IO2=A22,A18,A14,A10,A6,A2,M6,M2
IO3=A23,A19,A15,A11,A7,A3,M7,M3
14
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
5. Fast Read Quad I/O Data
IO0=(x,x,x,x, D4, D0,…)
IO1=(x,x,x,x, D5, D1,…)
IO2=(x,x,x,x, D6, D2,…)
IO3=(x,x,x,x, D7, D3,…)
6. Fast Word Read Quad I/O Data
IO0=(x,x, D4, D0,…)
IO1=(x,x, D5, D1,…)
IO2=(x,x, D6, D2,…)
IO3=(x,x, D7, D3,…)
7. Fast Word Read Quad I/O Data: the lowest address bit must be 0.
8. Security Registers Address:
Security Register1: A23-A16=00H, A15-A10=000100b, A9-A0=Byte Address;
Security Register2: A23-A16=00H, A15-A10=001000b, A9-A0=Byte Address;
Security Register3: A23-A16=00H, A15-A10=001100b, A9-A0=Byte Address.
9. Dummy bits and Wrap Bits
IO0=(x,x, x,x, x,x, W4, x)
IO1=(x,x, x,x, x,x, W5, x)
IO2=(x,x, x,x, x,x, W6, x)
IO3=(x,x, x,x, x,x, x, x)
10.Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID
IO0=(A20, A16, A12, A8, A4, A0, M4, M0, x,x, x,x, MID4, MID0, DID4, DID0, …)
IO1=(A21, A17, A13, A9, A5, A1, M5, M1, x,x, x,x, MID5, MID1, DID5, DID1, …)
IO2=(A22, A18, A14, A10, A6, A2, M6, M2,x,x, x,x, MID6, MID2, DID6, DID2, …)
IO3=(A23, A19, A15, A11, A7, A3, M7, M3, x,x, x,x, MID7, MID3, DID7, DID3, …)
Table 7.2. Table of ID Definitions for GD25B127D
Operation Code
9FH
MID7-MID0
ID15-ID8
ID7-ID0
18
C8
C8
40
90H/92H/94H
ABH
17
17
15
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL)
bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status
Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS#
goes low sending the Write Enable command CS# goes high.
Figure3. Write Enable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
06H
High-Z
SO
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence:
CS# goes lowSending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-
up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase,
Erase/Program Security Registers and Reset commands.
Figure4. Write Disable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
04H
High-Z
SO
16
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.3. Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the
system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or
affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command
must be issued prior to a Write Status Register command, and any other commands can't be inserted between them.
Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command
will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status
Register bit values.
Figure5. Write Enable for Volatile Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command(50H)
High-Z
SI
SO
7.4. Read Status Register (RDSR) (05H or 35H or 15H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress,
it is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible
to read the Status Register continuously. For command code “05H”/ “35H” / “15H”, the SO will output Status Register bits
S7~S0/ S15-S8 / S23-S16.
Figure6. Read Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
Command
05H or 35H or 15H
Register0/1/2
Register0/1/2
SO
High-Z
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
17
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.5. Write Status Register (WRSR) (01H or 31H or 11H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S20, S19, S17, S16, S15, S10, S1 and S0 of the Status
Register. CS# must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status Register
(WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose
duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check
the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register
cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3,
BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register (WRSR)
command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits.
Figure7. Write Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Status Register in
SCLK
Command
01H/31H/11H
SI
7
6
5
4
3
2 1 0
MSB
High-Z
SO
7.6. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit is latched-in on the
rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit is shifted out, at a Max
frequency fR, on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure8. Read Data Bytes Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
Command
03H
24-bit address
23 22 21
MSB
3
2
1
0
Data Out1
Data Out2
High-Z
SO
7
6
5
4
3
2
1
0
MSB
18
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at
that address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first
byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte
of data is shifted out.
Figure9. Read Data Bytes at Higher Speed Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
0BH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
7.8. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is
latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure 10. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure10. Dual Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
3BH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
SI
6
4
2
0
6
4
2
0
6
7
Data Out1
Data Out2
SO
7
5
3
1
7
5
3
1
MSB
MSB
19
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.9. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is
latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1
and IO0. The command sequence is shown in followed Figure11. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
Figure11. Quad Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
6BH
24-bit address
23 22 21
SI(IO0)
3
2
1
0
SO(IO1)
IO2
High-Z
High-Z
High-Z
IO3
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI(IO0)
SO(IO1)
IO2
IO3
Byte1 Byte2 Byte3 Byte4
7.10. Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input
the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, and each bit is latched in on
the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command
sequence is shown in followed Figure12. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-4) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4)= (1, 0), then the next Dual
I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command
sequence is shown in followed Figure12a. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command
requires the command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used
to reset (M5-4) before issuing normal command.
20
3.3V Uniform Sector
Dual and Quad Serial Flash
Figure12. Dual I/O Fast Read Sequence Diagram (M5-4≠(1, 0))
GD25B127D
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
BBH
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
SO(IO1)
7
Dummy
M7-4
A23-16
A15-8
A7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
Figure12a. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
6
4
2
0
6
4
2
0
6
4
5
2
3
0
1
6
7
4
5
7
5
3
1
7
5
3
1
7
A23-16
A15-8
A7-0
M7-4
Dummy
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
21
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.11. Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the
3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock4-bit per clock by IO0, IO1, IO2, IO3, and
each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,
IO1, IO2, IO3. The command sequence is shown in followed Figure13. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next
Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The
command sequence is shown in followed Figure13a. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the
next command requires the command code, thus returning to normal operation. A “Continuous Read Mode” Reset command
can be used to reset (M5-4) before issuing normal command.
Figure13. Quad I/O Fast Read Sequence Diagram (M5-4≠(1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
EBH
SI(IO0)
SO(IO1)
IO2
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
5
6
7
IO3
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Figure13a. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI(IO0)
SO(IO1)
IO2
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
IO3
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
22
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI Mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with
Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap
Around” feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited
to either an8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command,
once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary
automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache
afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap”
command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation
while W6-W5 is used to specify the length of the wrap around section within a page.
7.12. Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest
address bit (A0) must be equal 0 and only 2-dummy clocks. The command sequence is shown in followed Figure14. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) =(1, 0), then
the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command
code. The command sequence is shown in followed Figure14a.If the “Continuous Read Mode” bits (M5-4) do not equal to
(1, 0), the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read
Mode” Reset command can be used to reset (M5-4) before issuing normal command.
Figure14. Quad I/O Word Fast Read Sequence Diagram (M5-4≠ (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
E7H
SI(IO0)
SO(IO1)
IO2
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
5
6
7
IO3
Dummy
A23-16 A15-8 A7-0 M7-0
Byte1 Byte2 Byte3
23
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
Figure14a. Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI(IO0)
SO(IO1)
IO2
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
IO3
Dummy
A23-16 A15-8 A7-0 M7-0
Byte1 Byte2 Byte3
Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI Mode
The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst
with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap
Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be limited
to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command,
once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary
automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache
afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap”
command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation
while W6-W5 is used to specify the length of the wrap around section within a page.
24
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.13. Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word Fast Read”
command to access a fixed length of 8/16/32/64-byte section within a 256-byte page.
The Set Burst with Wrap command sequence: CS# goes low Send Set Burst with Wrap command Send 24
dummy bits Send 8 bits “Wrap bits” CS# goes high.
W4=0
W4=1 (default)
W6,W5
Wrap Around
Wrap Length
8-byte
Wrap Around
Wrap Length
0, 0
0, 1
1, 0
1, 1
Yes
Yes
Yes
Yes
No
No
No
No
N/A
N/A
N/A
N/A
16-byte
32-byte
64-byte
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and “Quad I/O
Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the
“Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set
W4=1.
Figure15. Set Burst with Wrap Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
77H
SI(IO0)
SO(IO1)
IO2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
5
6
x
x
x
x
x
x
x
x
IO3
W6-W4
25
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.14. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address
bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data
that goes beyond the end of the current page are programmed from the start address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The
Page Program command sequence: CS# goes low sending Page Program command 3-byte address on SI at least
1 byte data on SI CS# goes high. The command sequence is shown in Figure16. If more than 256 bytes are sent to the
device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within
the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses
without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data
byte has been latched in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and
BP0) is not executed.
Figure16. Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
Command
02H
24-bit address
23 22 21
MSB
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
26
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.15. Quad Page Program (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. A Write
Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the
Page Program command. The quad Page Program command is entered by driving CS# Low, followed by the command
code (32H), three address bytes and at least one data byte on IO pins.
The command sequence is shown in Figure17. If more than 256 bytes are sent to the device, previously latched data
are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than
256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on
the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in;
otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the
Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) is not executed.
Figure17.Quad Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
32H
24-bit address
23 22 21
MSB
Byte1 Byte2
SI(IO0)
SO(IO1)
IO2
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO3
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Byte11Byte12
SCLK
Byte253
Byte256
SI(IO0)
SO(IO1)
IO2
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO3
27
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.16. Sector Erase (SE) (20H)
The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by
driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address
for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low sending Sector Erase command 3-byte address on SI
CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven
high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the
Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected
by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit is not executed.
Figure18. Sector Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
20H
24 Bits Address
23 22
MSB
2
1
0
7.17. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is
entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block
is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low sending 32KB Block Erase command 3-byte address
on SI CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of the
last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits is not executed.
Figure19. 32KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
52H
24 Bits Address
23 22
2
1
0
MSB
28
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.18. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is
entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block
is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low sending 64KB Block Erase command 3-byte address
on SI CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the
last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits is not executed.
Figure20. 64KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
D8H
24 Bits Address
23 22
MSB
2
1
0
7.19. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low,
followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low sending Chip Erase command CS# goes high. The
command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has been
latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase
cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check
the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and
is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) command is executed only if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the
Block Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. The Chip Erase (CE) command is ignored if one or more sectors
are protected.
Figure21. Chip Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
60H or C7H
29
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.20. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode
(the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in
active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the
device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the
Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP)
command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down and Read Device ID (RDI) command or software reset command. The Release from Deep Power-Down
and Read Device ID (RDI) command releases the device from Deep Power-Down mode, also allows the Device ID of the
device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device is in the Standby Mode after Power-
Up.
The Deep Power-Down command sequence: CS# goes low sending Deep Power-Down command CS# goes
high. The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the command code has
been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires
a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-
Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
Figure22. Deep Power-Down Sequence Diagram
CS#
tDP
0
1 2 3 4 5 6 7
SCLK
SI
Command
B9H
Stand-by mode Deep Power-down mode
30
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.21. Release from Deep Power-Down and Read Device ID (RDI) (ABH)
The Release from Power-Down and Read Device ID command is a multi-purpose command. It can be used to release
the device from the Power-Down state or obtain the devices electronic identification (ID) number.
To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the
instruction code “ABH” and driving CS# high as shown below. Release from Power-Down will take the time duration of
tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The
CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the
CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown below. The Device ID value for the GD25B127D
is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is
completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the same
as previously described, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC
Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If
the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (when
WIP equal 1) the command is ignored and will not have any effects on the current cycle.
Figure23. Release Power-Down Sequence Diagram
CS#
tRES1
0
1
2
3
4
5
6
7
SCLK
SI
Command
ABH
Deep Power-down mode
Stand-by mode
Figure24. Release Power-Down/Read Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
SCLK
tRES2
Command
ABH
3 Dummy Bytes
23 22
MSB
SI
2
1
0
Device ID
SO
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode Stand-by Mode
31
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.22. Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command
that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure25. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure25. Read Manufacture ID/ Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
24-bit address
23 22 21
SI
90H
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
Device ID
Manufacturer ID
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
32
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.23. Read Manufacture ID/ Device ID Dual I/O (92H)
The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O.
The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure26. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure26. Read Manufacture ID/ Device ID Dual I/O Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
92H
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
7
A23-16
A15-8
A7-0
M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
MFR ID
(Repeat)
MFR ID
Device ID
Device ID
(Repeat)
MFR ID
(Repeat)
Device ID
(Repeat)
33
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.24. Read Manufacture ID/ Device ID Quad I/O (94H)
The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O.
The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure27. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure27. Read Manufacture ID/ Device ID Quad I/O Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
94H
SI(IO0)
SO(IO1)
IO2
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
IO3
MFR ID DID
A23-16 A15-8 A7-0 M7-0
Dummy
CS#
24 25 26 27 28 29 30 31
SCLK
SI(IO0)
SO(IO1)
IO2
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO3
MFR ID DID
MFR ID DID
(Repeat()Repeat)
(Repeat()Repeat)
34
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.25. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes
of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the
device in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is
followed by the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock.
The command sequence is shown in Figure28. The Read Identification (RDID) command is terminated by driving CS# high
at any time during data output. When CS# is driven high, the device is in the Standby Mode. Once in the Standby Mode,
the device waits to be selected, so that it can receive, decode and execute commands.
Figure28. Read Identification ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
9FH
Command
Manufacturer ID
7
6
5
4
3
2
1
0
SO
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Memory Type
JDID15-JDID8
Capacity
JDID7-JDID0
MSB
MSB
35
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.26. Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase
operation and then read data from any other sector or block. The Write Status Register command (01H/31H/11H) and
Erase/Program Security Registers command (44H,42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page
Program command (02H / 32H) are not allowed during Program suspend. The Write Status Register command
(01H/31H/11H) and Erase Security Registers command (44H) and Erase commands (20H, 52H, D8H, C7H, 60H) are not
allowed during Erase suspend. Program/Erase Suspend is valid only during the page program or sector/block erase
operation. A maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status Register
equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS2/SUS1
bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared from 1
to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off
during the suspend period will reset the device and release the suspend state. The command sequence is show in Figure29.
Figure29. Program/Erase Suspend Sequence Diagram
CS#
0
1
2
3
4
5
6
7
tSUS
SCLK
SI
Command
75H
High-Z
SO
Accept read command
7.27. Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation after
a Program/Erase Suspend command. The Program/Erase command will be accepted by the device only if the SUS2/SUS1
bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared from 1 to 0
immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or
the page will complete the program operation. The Program/Erase Resume command will be ignored unless a
Program/Erase Suspend is active. The command sequence is show in Figure30.
Figure30. Program/Erase Resume Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
7AH
SO
Resume Erase/Program
36
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.28. Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The
Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low sending Read Unique ID command 3-Byte Address
(000000H) Dummy Byte128bit Unique ID Out CS# goes high.
Figure31. Read Unique ID Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
24-bit address
Command
4BH
(000000H)
3
23 22 21
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
7.29. Erase Security Registers (44H)
The GD25B127D provides three 1024-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information separately from
the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low sending Erase Security Registers command
3-byte address on SI CS# goes high. The command sequence is shown in Figure32. CS# must be driven high after the
eighth bit of the last address byte has been latched in; otherwise the Erase Security Registers command is not executed.
As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the
Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress
(WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security
Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set
to 1, the Security Registers will be permanently locked; the Erase Security Register command will be ignored.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
Don’t care
Don’t care
Don’t care
00H
0 0
00H
0 0
37
3.3V Uniform Sector
Dual and Quad Serial Flash
Figure32. Erase Security Registers command Sequence Diagram
GD25B127D
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
44H
24 Bits Address
23 22
MSB
2
1
0
7.30. Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. Each security register contains
four pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch
(WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered
by driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon
as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program
Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Register will be permanently locked. Program Security
Registers command will be ignored.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00H
0 0
00H
0 0
Figure33. Program Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
42H
24-bit address
23 22 21
MSB
Data Byte 1
SI
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
SI
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
38
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.31. Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte
address (A23-A0) and a dummy byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at
that address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first
byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte
of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the
command is completed by driving CS# high.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00H
0 0
00H
0 0
Figure34. Read Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
48H
24-bit address
23 22 21
SI
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
39
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
7.32. Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its
default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch
status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read Mode bit setting (M7-
M0) and Wrap Bit Setting (W6-W4).
The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI mode. The “Reset (99H)”
command sequence as follow: CS# goes low Sending Enable Reset command CS# goes high CS# goes low
Sending Reset command CS# goes high. Once the Reset command is accepted by the device, the device will take
approximately tRST_R to reset. During this period, no command will be accepted. Data corruption may happen if there is an
on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It
is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence.
Figure35. Enable Reset and Reset command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6 7
SCLK
SI
Command
66H
Command
99H
High-Z
SO
7.33. Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can
be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple
vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard
of JEDEC Standard No.216.
Figure36. Read Serial Flash Discoverable Parameter command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
5AH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
40
3.3V Uniform Sector
Dual and Quad Serial Flash
Table 7.3. Signature and Parameter Identification Data Values
GD25B127D
Description
Comment
Add(H)
(Byte)
DW Add
(Bit)
Data
Data
SFDP Signature
Fixed:50444653H
00H
01H
02H
03H
04H
05H
06H
07H
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
53H
46H
44H
50H
00H
01H
01H
FFH
53H
46H
44H
50H
00H
01H
01H
FFH
SFDP Minor Revision Number
SFDP Major Revision Number
Number of Parameters Headers
Unused
Start from 00H
Start from 01H
Start from 00H
Contains 0xFFH and can never be
changed
ID number (JEDEC)
00H: It indicates a JEDEC specified
header
08H
09H
0AH
0BH
07:00
15:08
23:16
31:24
00H
00H
01H
09H
00H
00H
01H
09H
Parameter Table Minor Revision
Number
Start from 0x00H
Parameter Table Major Revision
Number
Start from 0x01H
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
0CH
0DH
0EH
0FH
07:00
15:08
23:16
31:24
30H
00H
00H
FFH
30H
00H
00H
FFH
Unused
Contains 0xFFH and can never be
changed
ID Number
It is indicates GigaDevice
manufacturer ID
10H
11H
12H
13H
07:00
15:08
23:16
31:24
C8H
00H
01H
03H
C8H
00H
01H
03H
(GigaDevice Manufacturer ID)
Parameter Table Minor Revision
Number
Start from 0x00H
Parameter Table Major Revision
Number
Start from 0x01H
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
Parameter Table Pointer (PTP)
First address of GigaDevice Flash
Parameter table
14H
15H
16H
17H
07:00
15:08
23:16
31:24
60H
00H
00H
FFH
60H
00H
00H
FFH
Unused
Contains 0xFFH and can never be
changed
41
3.3V Uniform Sector
Dual and Quad Serial Flash
Table 7.4. Parameter Table (0): JEDEC Flash Parameter Tables
GD25B127D
Description
Comment
Add(H)
(Byte)
DW Add
(Bit)
Data
Data
00: Reserved; 01: 4KB erase;
10: Reserved;
Block/Sector Erase Size
01:00
02
01b
1b
11: not support 4KB erase
0: 1Byte, 1: 64Byte or larger
0: Nonvolatile status bit
1: Volatile status bit
Write Granularity
Write Enable Instruction
Requested for Writing to Volatile
Status Registers
03
0b
(BP status register bit)
0: Use 50H Opcode,
30H
E5H
Write Enable Opcode Select for
Writing to Volatile Status
Registers
1: Use 06H Opcode,
Note: If target flash status register is
Nonvolatile, then bits 3 and 4 must
be set to 00b.
04
0b
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Opcode
31H
32H
15:08
16
20H
1b
20H
F1H
FFH
(1-1-2) Fast Read
0=Not support, 1=Support
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
Address Bytes Number used in
addressing flash array
Double Transfer Rate (DTR)
clocking
18:17
19
00b
0b
0=Not support, 1=Support
(1-2-2) Fast Read
0=Not support, 1=Support
0=Not support, 1=Support
0=Not support, 1=Support
20
21
1b
1b
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
22
1b
23
1b
Unused
33H
31:24
31:00
FFH
Flash Memory Density
37H:34H
07FFFFFFH
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
00100b
states
Clocks) not support
38H
39H
3AH
3BH
44H
EBH
08H
6BH
(1-4-4) Fast Read Number of
Mode Bits
000b:Mode Bits not support
07:05
15:08
20:16
010b
EBH
(1-4-4) Fast Read Opcode
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
01000b
states
Clocks) not support
(1-1-4) Fast Read Number of
Mode Bits
000b:Mode Bits not support
23:21
31:24
000b
6BH
(1-1-4) Fast Read Opcode
42
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
Add(H)
(Byte)
DW Add
(Bit)
Description
Comment
Data
Data
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
01000b
states
Clocks) not support
3CH
3DH
3EH
3FH
08H
3BH
42H
BBH
(1-1-2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
07:05
15:08
20:16
000b
3BH
(1-1-2) Fast Read Opcode
(1-2-2) Fast Read Number
of Wait states
0 0000b: Wait states (Dummy
Clocks) not support
00010b
(1-2-2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
23:21
010b
(1-2-2) Fast Read Opcode
31:24
00
BBH
0b
(2-2-2) Fast Read
Unused
0=not support 1=support
0=not support 1=support
03:01
04
111b
0b
40H
EEH
(4-4-4) Fast Read
Unused
07:05
31:08
15:00
111b
0xFFH
0xFFH
Unused
43H:41H
45H:44H
0xFFH
0xFFH
Unused
(2-2-2) Fast Read Number
of Wait states
0 0000b: Wait states (Dummy
Clocks) not support
20:16
23:21
00000b
000b
46H
00H
(2-2-2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
(2-2-2) Fast Read Opcode
47H
31:24
15:00
FFH
FFH
Unused
49H:48H
0xFFH
0xFFH
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
00000b
states
Clocks) not support
4AH
00H
(4-4-4) Fast Read Number
of Mode Bits
000b: Mode Bits not support
23:21
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
000b
EBH
0CH
20H
0FH
52H
10H
D8H
00H
FFH
(4-4-4) Fast Read Opcode
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
EBH
0CH
20H
0FH
52H
10H
D8H
00H
FFH
Sector/block size=2^N bytes
Sector Type 1 Size
0x00b: this sector type don’t exist
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 4 erase Opcode
43
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
Data
Table 7.5. Parameter Table (1): GigaDevice Flash Parameter Tables
Add(H)
(Byte)
DW Add
Description
Comment
2000H=2.000V
Data
(Bit)
Vcc Supply Maximum Voltage
2700H=2.700V
61H:60H
15:00
3600H
3600H
3600H=3.600V
1650H=1.650V
2250H=2.250V
Vcc Supply Minimum Voltage
63H:62H
31:16
2700H
2700H
2350H=2.350V
2700H=2.700V
HW Reset# pin
HW Hold# pin
0=not support 1=support
00
01
02
03
0b
0b
1b
0=not support 1=support
0=not support 1=support
Deep Power Down Mode
SW Reset
0=not support 1=support
Should be issue Reset Enable(66H)
before Reset cmd.
1b
1001 1001b
(99H)
SW Reset Opcode
65H:64H
11:04
F99CH
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
12
13
1b
0=not support 1=support
0=not support 1=support
1b
1b
14
Wrap-Around Read mode
Wrap-Around Read mode Opcode
15
1b
66H
67H
23:16
77H
77H
64H
08H:support 8B wrap-around read
16H:8B&16B
Wrap-Around Read data length
31:24
64H
32H:8B&16B&32B
64H:8B&16B&32B&64B
0=not support 1=support
Individual block lock
00
01
0b
0b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
Individual block lock Opcode
Individual block lock Volatile
protect bit default protect status
Secured OTP
09:02
10
FFH
CBFC/
EBFCH
(1)
0=protect 1=unprotect
0b
6BH:68H
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
Read Lock
Permanent Lock
Unused
13
0b/1b(1)
11b
15:14
31:16
Unused
FFFFH
FFFFH
NOTE:
1. GD25B127DxxSx supports Permanent Lock. Please contact GigaDevice for details.
44
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
8. ELECTRICAL CHARACTERISTICS
8.1. POWER-ON TIMING
Figure 37. Power-on Timing Sequence Diagram
Vcc(max)
Vcc(min)
VWI
Chip Selection is not allowed
Device is fully
accessible
tVSL
Time
Table 8.1. Power-Up Timing and Write Inhibit Threshold
Parameter
Symbol
Min
2.5
1.5
Max
Unit
ms
tVSL
VWI
VCC (min) To CS# Low
Write Inhibit Voltage
2.5
V
8.2. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH). The Status
Register bits are set to 0, except DRV1 bit (S22) and QE bit (S9) are set to 1.
8.3. ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
Ambient Operating Temperature
-40 to 85
-40 to 105
℃
-40 to 125
Storage Temperature
-65 to 150
℃
V
Applied Input/Output Voltage
Transient Input/Output Voltage (note: overshoot)
VCC
-0.6 to VCC+0.4
-2.0 to VCC+2.0
-0.6 to 4.2
V
V
45
3.3V Uniform Sector
Dual and Quad Serial Flash
Figure 38. Maximum Negative/positive Overshoot Diagram
GD25B127D
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
8.4. CAPACITANCE MEASUREMENT CONDITIONS
Symbol
CIN
Parameter
Min
Typ.
Max
6
Unit
Conditions
VIN=0V
Input Capacitance
pF
pF
pF
ns
V
COUT
CL
Output Capacitance
8
VOUT=0V
Load Capacitance
30
Input Rise And Fall time
Input Pulse Voltage
5
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
V
V
Figure39. Input Test Waveform and Measurement Level
Input timing reference level
0.7VCC
Output timing reference level
0.5VCC
0.8VCC
0.1VCC
AC Measurement Level
0.2VCC
Note: Input pulse rise and fall time are <5ns
46
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
8.5. DC CHARACTERISTICS
(T= -40℃~85℃, VCC=2.7~3.6V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ.
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
VIN=VCC or VSS
Deep Power-Down Current CS#=VCC,
VIN=VCC or VSS
20
1
50
μA
ICC2
5
μA
CLK=0.1VCC /
0.9VCC
15
13
20
mA
at 104MHz,
Q=Open(*1 I/O)
CLK=0.1VCC /
0.9VCC
ICC3
Operating Current (Read)
Operating Current (PP)
18
mA
at 80MHz,
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
27
27
mA
mA
mA
mA
mA
V
Operating Current (WRSR) CS#=VCC
Operating Current (SE)
Operating Current (BE)
Operating Current (CE)
Input Low Voltage
CS#=VCC
CS#=VCC
CS#=VCC
27
27
27
0.2VCC
VCC+0.4
0.2
VIH
Input High Voltage
0.7VCC
VCC-0.2
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =100μA
IOH =-100μA
V
V
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
47
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
(T= -40℃~105℃, VCC=2.7~3.6V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ.
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
VIN=VCC or VSS
Deep Power-Down Current CS#=VCC,
VIN=VCC or VSS
20
1
100
μA
ICC2
20
20
μA
CLK=0.1VCC /
0.9VCC
15
13
mA
at 80MHz,
Q=Open(*1 I/O)
CLK=0.1VCC /
0.9VCC
ICC3
Operating Current (Read)
Operating Current (PP)
18
mA
at 60MHz,
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
30
30
mA
mA
mA
mA
mA
V
Operating Current (WRSR) CS#=VCC
Operating Current (SE)
Operating Current (BE)
Operating Current (CE)
Input Low Voltage
CS#=VCC
CS#=VCC
CS#=VCC
30
30
30
0.2VCC
VCC+0.4
0.2
VIH
Input High Voltage
0.7VCC
VCC-0.2
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =100μA
IOH =-100μA
V
V
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
48
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
(T= -40℃~125℃, VCC=2.7~3.6V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ.
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
VIN=VCC or VSS
Deep Power-Down Current CS#=VCC,
VIN=VCC or VSS
20
1
120
μA
ICC2
25
20
μA
CLK=0.1VCC /
0.9VCC
15
13
mA
at 80MHz,
Q=Open(*1 I/O)
CLK=0.1VCC /
0.9VCC
ICC3
Operating Current (Read)
Operating Current (PP)
18
mA
at 60MHz,
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
30
30
mA
mA
mA
mA
mA
V
Operating Current (WRSR) CS#=VCC
Operating Current (SE)
Operating Current (BE)
Operating Current (CE)
Input Low Voltage
CS#=VCC
CS#=VCC
CS#=VCC
30
30
30
0.2VCC
VCC+0.4
0.2
VIH
Input High Voltage
0.7VCC
VCC-0.2
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =100μA
IOH =-100μA
V
V
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
49
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
8.6. AC CHARACTERISTICS
(T= -40℃~85℃, VCC=2.7~3.6V, CL=30pf)
Symbol
Parameter
Min.
Typ.
Max.
Unit.
Serial Clock Frequency For: Fast Read (0BH), on 2.7V-3.6V
power supply
FC
104
MHz
Serial Clock Frequency For: Dual Output (3BH), Quad Output
(6BH), Dual I/O (BBH), Quad I/O (EBH), Quad I/O Word Fast
Read (E7H), on 2.7V-3.0V power supply
fC1
80
MHz
Serial Clock Frequency For: Dual Output (3BH), Quad Output
(6BH), Dual I/O (BBH), Quad I/O (EBH), Quad I/O Word Fast
Read (E7H), on 3.0V-3.6V power supply
fC2
104
80
MHz
MHz
Serial Clock Frequency For: Read (03H), Read Manufacturer
ID/device ID (90H), Read Identification (9FH)
fR
tCLH
tCLL
Serial Clock High Time
4.5
4.5
0.1
0.1
5
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
ms
ms
μs
μs
ms
ms
s
Serial Clock Low Time
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tCLQV
tDP
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
CS# Active Hold Time
5
CS# Not Active Setup Time
5
CS# Not Active Hold Time
5
CS# High Time (read/write)
20
Output Disable Time
6
Output Hold Time
1.0
2
Data In Setup Time
Data In Hold Time
2
Clock Low To Output Valid
6.5
20
30
30
20
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic Signature Read
CS# High To Standby Mode With Electronic Signature Read
CS# High To Next Command After Suspend
Latency Between Resume And Next Suspend
CS# High To Next Command After Reset (Except From Erase)
CS# High To Next Command After Reset (From Erase)
Write Status Register Cycle Time
Byte Program Time (First Byte)
Additional Byte Program Time (After First Byte)
Page Programming Time
tRES1
tRES2
tSUS
tRS
100
tRST
30
12
tRST_E
tW
5
30
30
tBP1
50
tBP2
2.5
0.5
50
12
tPP
2.4
400
0.8
1.2
120
tSE
Sector Erase Time
tBE1
Block Erase Time (32K Bytes)
0.16
0.3
50
tBE2
Block Erase Time (64K Bytes)
s
tCE
Chip Erase Time (GD25B127D)
s
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
50
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
(T= -40℃~105℃, VCC=2.7~3.6V, CL=30pf)
Symbol
Parameter
Min.
Typ.
Max.
Unit.
Serial Clock Frequency For: Fast Read (0BH), on 2.7V-3.6V
FC
80
MHz
power supply
Serial Clock Frequency For: Dual Output (3BH), Quad Output
(6BH), Dual I/O (BBH), Quad I/O (EBH), Quad I/O Word Fast
fC1
60
MHz
Read (E7H), on 2.7V-3.0V power supply
Serial Clock Frequency For: Dual Output (3BH), Quad Output
fC2
80
60
MHz
MHz
(6BH), Dual I/O (BBH), Quad I/O (EBH), Quad I/O Word Fast
Read (E7H), on 3.0V-3.6V power supply
Serial Clock Frequency For: Read (03H), Read Manufacturer
fR
ID/device ID (90H), Read Identification (9FH)
Serial Clock High Time
tCLH
tCLL
4.5
4.5
0.1
0.1
5
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
ms
ms
μs
μs
ms
ms
s
Serial Clock Low Time
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tCLQV
tDP
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
CS# Active Hold Time
5
CS# Not Active Setup Time
5
CS# Not Active Hold Time
5
CS# High Time (read/write)
20
Output Disable Time
6
Output Hold Time
1.0
2
Data In Setup Time
Data In Hold Time
2
Clock Low To Output Valid
7
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic Signature Read
CS# High To Standby Mode With Electronic Signature Read
CS# High To Next Command After Suspend
Latency Between Resume And Next Suspend
CS# High To Next Command After Reset (Except From Erase)
CS# High To Next Command After Reset (From Erase)
Write Status Register Cycle Time
Byte Program Time (First Byte)
Additional Byte Program Time (After First Byte)
Page Programming Time
20
30
30
20
tRES1
tRES2
tSUS
tRS
100
tRST
30
12
30
60
15
4
tRST_E
tW
5
30
tBP1
tBP2
2.5
0.5
50
tPP
tSE
Sector Erase Time
400
2
tBE1
Block Erase Time (32K Bytes)
0.16
0.3
50
tBE2
Block Erase Time (64K Bytes)
3
s
tCE
Chip Erase Time (GD25B127D)
150
s
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
51
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
(T= -40℃~125℃, VCC=2.7~3.6V, CL=30pf)
Symbol
Parameter
Min.
Typ.
Max.
Unit.
Serial Clock Frequency For: Fast Read (0BH), on 2.7V-3.6V
FC
80
MHz
power supply
Serial Clock Frequency For: Dual Output (3BH), Quad Output
(6BH), Dual I/O (BBH), Quad I/O (EBH), Quad I/O Word Fast
fC1
60
MHz
Read (E7H), on 2.7V-3.0V power supply
Serial Clock Frequency For: Dual Output (3BH), Quad Output
fC2
80
60
MHz
MHz
(6BH), Dual I/O (BBH), Quad I/O (EBH), Quad I/O Word Fast
Read (E7H), on 3.0V-3.6V power supply
Serial Clock Frequency For: Read (03H), Read Manufacturer
fR
ID/device ID (90H), Read Identification (9FH)
Serial Clock High Time
tCLH
tCLL
4.5
4.5
0.1
0.1
5
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
ms
ms
μs
μs
ms
ms
s
Serial Clock Low Time
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tCLQV
tDP
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
CS# Active Hold Time
5
CS# Not Active Setup Time
5
CS# Not Active Hold Time
5
CS# High Time (read/write)
20
Output Disable Time
6
Output Hold Time
1.0
2
Data In Setup Time
Data In Hold Time
2
Clock Low To Output Valid
7
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic Signature Read
CS# High To Standby Mode With Electronic Signature Read
CS# High To Next Command After Suspend
Latency Between Resume And Next Suspend
CS# High To Next Command After Reset (Except From Erase)
CS# High To Next Command After Reset (From Erase)
Write Status Register Cycle Time
Byte Program Time (First Byte)
Additional Byte Program Time (After First Byte)
Page Programming Time
20
30
30
20
tRES1
tRES2
tSUS
tRS
100
tRST
30
12
30
60
15
4
tRST_E
tW
5
30
tBP1
tBP2
2.5
0.5
50
tPP
tSE
Sector Erase Time
500
2.5
4
tBE1
Block Erase Time (32K Bytes)
0.16
0.3
50
tBE2
Block Erase Time (64K Bytes)
s
tCE
Chip Erase Time (GD25B127D)
180
s
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
52
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
Figure40. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tCLCH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
SI
MSB
High-Z
LSB
SO
Figure41. Output Timing
CS#
tCLH
tSHQZ
SCLK
tCLQV
tCLQV
tCLQX
tCLL
tCLQX
SO
SI
LSB
Least significant address bit (LIB) in
Figure42. Resume to Suspend Timing Diagram
tRS
Resume
Command
Suspend
Command
CS#
53
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
9. ORDERING INFORMATION
GD XX XX XX X X X X X
Packing
T or no mark: Tube
Y: Tray
R: Tape and Reel
Green Code
G: Pb Free + Halogen Free Green Package
S: Pb Free + Halogen Free Green Package + SRP1
Function
Temperature Range
I: Industrial (-40℃ to +85℃)
J: Industrial (-40℃ to +105℃)
E: Industrial (-40℃ to +125℃)
F: Industrial+ (-40℃ to +85℃)
3: Automotive (-40℃ to +85℃)*
2: Automotive (-40℃ to +105℃)*
A: Automotive (-40℃ to +125℃)*
Package Type
S: SOP8 208mil
V: VSOP8 208mil
P: DIP8 300mil
F: SOP16 300mil
W: WSON8 (6x5mm)
Y: WSON8 (8x6mm)
Z: TFBGA-24ball (6x4 Ball Array)
Generation
D: D Version
Density
127: 128M bit
Series
B: 3V, 4KB Uniform Sector, QE=1 Permenently
Product Family
25: SPI Interface Flash
*Please contact GigaDevice sales for automotive products.
54
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
9.1. Valid Part Numbers
Please contact GigaDevice regional sales for the latest product selection and available form factors.
Temperature Range I: Industrial (-40℃ to +85℃)
Product Number
Density
128Mbit
128Mbit
128Mbit
128Mbit
128Mbit
128Mbit
128Mbit
Package Type
SOP8 208mil
GD25B127DSIG
GD25B127DSIS
GD25B127DVIG
GD25B127DVIS
GD25B127DPIG
GD25B127DPIS
GD25B127DFIG
GD25B127DFIS
GD25B127DWIG
GD25B127DWIS
GD25B127DYIG
GD25B127DYIS
GD25B127DZIG
GD25B127DZIS
VSOP8 208mil
DIP8 300mil
SOP16 300mil
WSON8 (6x5mm)
WSON8 (8x6mm)
TFBGA-24ball (6x4 Ball Array)
Temperature Range J: Industrial (-40℃ to +105℃)
Product Number
Density
128Mbit
128Mbit
128Mbit
128Mbit
128Mbit
128Mbit
128Mbit
Package Type
SOP8 208mil
GD25B127DSJG
GD25B127DSJS
GD25B127DVJG
GD25B127DVJS
GD25B127DPJG
GD25B127DPJS
GD25B127DFJG
GD25B127DFJS
GD25B127DWJG
GD25B127DWJS
GD25B127DYJG
GD25B127DYJS
GD25B127DZJG
GD25B127DZJS
VSOP8 208mil
DIP8 300mil
SOP16 300mil
WSON8 (6x5mm)
WSON8 (8x6mm)
TFBGA-24ball (6x4 Ball Array)
Temperature Range E: Industrial (-40℃ to +125℃)
55
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
Product Number
Density
128Mbit
128Mbit
128Mbit
128Mbit
128Mbit
128Mbit
128Mbit
Package Type
GD25B127DSEG
GD25B127DSES
GD25B127DVEG
GD25B127DVES
GD25B127DPEG
GD25B127DPES
GD25B127DFEG
GD25B127DFES
GD25B127DWEG
GD25B127DWES
GD25B127DYEG
GD25B127DYES
GD25B127DZEG
GD25B127DZES
SOP8 208mil
VSOP8 208mil
DIP8 300mil
SOP16 300mil
WSON8 (6x5mm)
WSON8 (8x6mm)
TFBGA-24ball (6x4 Ball Array)
Temperature Range F: Industrial+ (-40℃ to +85℃)
Product Number
Density
128Mbit
128Mbit
128Mbit
128Mbit
128Mbit
128Mbit
128Mbit
Package Type
SOP8 208mil
GD25B127DSFG
GD25B127DSFS
GD25B127DVFG
GD25B127DVFS
GD25B127DPFG
GD25B127DPFS
GD25B127DFFG
GD25B127DFFS
GD25B127DWFG
GD25B127DWFS
GD25B127DYFG
GD25B127DYFS
GD25B127DZFG
GD25B127DZFS
VSOP8 208mil
DIP8 300mil
SOP16 300mil
WSON8 (6x5mm)
WSON8 (8x6mm)
TFBGA-24ball (6x4 Ball Array)
56
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
10.PACKAGE INFORMATION
10.1. Package SOP8 208MIL
D
8
5
E
E1
L1
L
1
4
“A”
θ
b
Base Metal
A
A2
c
Detail “A”
A1
b
e
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
Min
-
-
0.05
0.15
0.25
1.70
1.80
1.90
0.31
0.41
0.51
0.15
0.20
0.25
5.13
5.23
5.33
7.70
7.90
8.10
5.18
5.28
5.38
0.50
-
0°
-
mm Nom
Max
1.27
1.31
2.16
0.85
8°
Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.
57
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
10.2. Package VSOP8 208MIL
D
8
5
E
E1
L1
L
1
4
“A”
θ
b
Base Metal
A2
A1
A
c
b
e
Detail “A”
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
Min
-
-
0.05
0.10
0.15
0.75
0.80
0.85
0.35
0.42
0.50
0.09
0.15
0.20
5.18
5.28
5.38
7.70
7.90
8.10
5.18
5.28
5.38
0.50
-
0°
-
mm Nom
Max
1.27
1.31
1.00
0.80
10°
Note:
1. Both the package length and width include the mold flash.
2. Seating plane: Max. 0.1mm.
58
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
10.3. Package DIP8 300MIL
4
1
E
E1
c
θ
5
8
eA
D
A2
A
A1
L
e
b1
b
Dimensions
Symbol
Unit
A
A1
A2
b
b1
C
D
E
E1
e
L
eA
θ
Min
-
-
0.38
3.00
3.30
3.50
1.14
1.52
1.78
0.36
0.46
0.56
0.20
0.25
0.35
9.02
9.27
9.59
7.62
7.87
8.26
6.10
6.35
6.60
2.92
3.30
3.81
8.45
8.90
9.35
0°
-
mm Nom
Max
-
-
2.54
3.88
11°
Note: Both the package length and width do not include the mold flash.
59
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
10.4. Package SOP16 300MIL
D
16
9
E1
E
h
L1
L
1
8
h
θ
“A”
b
c
Base Metal
A
A2
A1
Detail “A”
b
e
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
h
θ
Min
-
-
0.10
0.20
0.30
2.05
-
0.31
0.41
0.51
0.10 10.20 10.10 7.40
0.25 10.30 10.30 7.50
0.33 10.40 10.50 7.60
0.40
-
0.25
-
0
-
mm Nom
Max
1.27
1.40
2.65
2.55
1.27
0.75
8
Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.
60
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
10.5. Package WSON8 (6*5mm)
c
D
PIN 1#
E
A1
A
Top View
Side View
L
8
1
b
e
E2
5
4
D2
Bottom View
Dimensions
Symbol
A
A1
c
b
D
D2
E
E2
e
L
Unit
Min
0.70
0.75
0.80
0.00
0.02
0.05
0.180
0.203
0.250
0.35
0.40
0.50
5.90
6.00
6.10
3.30
3.40
3.50
4.90
5.00
5.10
3.90
4.00
4.10
0.50
0.60
0.75
mm
Nom
Max
1.27
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package lead frames. These lead
shapes are compatible with each other.
61
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
10.6. Package WSON8 (8*6mm)
c
D
PIN 1#
E
A1
A
Top View
Side View
L
8
1
4
b
e
E2
5
D2
Bottom View
Dimensions
Symbol
Unit
A
A1
c
b
D
D2
E
E2
e
L
Min
0.70
0.75
0.80
0.00
0.02
0.05
0.180
0.203
0.250
0.35
0.40
0.45
7.90
8.00
8.10
3.30
3.40
3.50
5.90
6.00
6.10
4.20
4.30
4.40
0.45
0.50
0.55
mm Nom
Max
1.27
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package lead frames. These lead
shapes are compatible with each other.
62
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
10.7. Package TFBGA-24BALL (6*4 ball array)
1
2
3
4
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
b
e
D
D1
e
E
E1
A2
A
A1
Dimensions
Symbol
Unit
A
A1
A2
b
E
E1
D
D1
e
Min
-
-
0.25
0.30
0.35
0.75
0.80
0.85
0.35
5.90
6.00
6.10
7.90
8.00
8.10
mm
Nom
Max
0.40
0.45
3.00
5.00
1.00
1.20
Note: Both the package length and width do not include the mold flash.
63
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
11.REVISION HISTORY
Version No
Description
Page
---
Date
1.0
Initial Release
2016-8-23
Update Table7.5. Parameter Table (1): GigaDevice Flash
Parameter Tables
---
1.1
1.2
2016-8-26
Add “Page” Column in the Revision History
Modify the note in the description of WSON packages
Delete tRST_R and tRST_P
P59
P56-57
P48
2017-11-13
Add tRST, of which the max value is 30us
Delete figure 34, which is excrescent
P48
P39
Modify tVSL from 5ms to 2.5ms
P45
Add tRS, of which the min value is 100us
Update Ordering Information
P48
1.3
1.4
2018-5-18
2018-7-25
P50
Update the description of all packages
P52-58
P37
Add 4BH command
Modify Icc4~8 max. value @-40~85℃ from 25mA to 27mA
Modify tpp typ. value @-40~85℃ from 0.6ms to 0.5ms
Modify tBE1 typ. value @-40~85℃ from 0.2~1.0s to 0.16~0.8s
Modify tCE typ. value @-40~85℃ from 60s to 50s
Add DC/AC parameters @-40~105℃ and @-40~125℃
P47
P50
P50
P50
P48, 49, 51, 52
64
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B127D
Important Notice
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65
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