GD25LQ128DVJS [GIGADEVICE]
1.8V Uniform Sector Dual and Quad Serial Flash;
| 型号： | GD25LQ128DVJS |
| 厂家： | 
GigaDevice |
| 描述： | 1.8V Uniform Sector Dual and Quad Serial Flash |
| 文件： | 总79页 (文件大小：1512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
GD25LQ128D
DATASHEET
1
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
Contents
1. FEATURES .........................................................................................................................................................4
2. GENERAL DESCRIPTION................................................................................................................................5
3. MEMORY ORGANIZATION...............................................................................................................................7
4. DEVICE OPERATION ........................................................................................................................................8
5. DATA PROTECTION..........................................................................................................................................9
6. STATUS REGISTER.........................................................................................................................................11
7. COMMANDS DESCRIPTION..........................................................................................................................13
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
WRITE ENABLE (WREN) (06H)................................................................................................................................ 17
WRITE DISABLE (WRDI) (04H) ................................................................................................................................ 18
WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ................................................................................................. 19
READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H) .............................................................................................. 20
WRITE STATUS REGISTER (WRSR) (01H)................................................................................................................... 21
READ DATA BYTES (READ) (03H)............................................................................................................................. 22
READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH).............................................................................................. 23
DUAL OUTPUT FAST READ (3BH).............................................................................................................................. 24
QUAD OUTPUT FAST READ (6BH)............................................................................................................................. 25
7.10. DUAL I/O FAST READ (BBH).................................................................................................................................... 26
7.11. QUAD I/O FAST READ (EBH) ................................................................................................................................... 27
7.12. QUAD I/O WORD FAST READ (E7H) ......................................................................................................................... 30
7.13. SET BURST WITH WRAP (77H) ................................................................................................................................. 31
7.14. PAGE PROGRAM (PP) (02H).................................................................................................................................... 32
7.15. QUAD PAGE PROGRAM (32H).................................................................................................................................. 34
7.16. SECTOR ERASE (SE) (20H)....................................................................................................................................... 35
7.17. 32KB BLOCK ERASE (BE) (52H)............................................................................................................................... 36
7.18. 64KB BLOCK ERASE (BE) (D8H)............................................................................................................................... 37
7.19. CHIP ERASE (CE) (60/C7H)..................................................................................................................................... 38
7.20. DEEP POWER-DOWN (DP) (B9H)............................................................................................................................. 39
7.21. RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) ......................................................................... 40
7.22. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ................................................................................................... 42
7.23. READ MANUFACTURE ID/ DEVICE ID DUAL I/O (92H) ................................................................................................. 43
7.24. READ MANUFACTURE ID/ DEVICE ID QUAD I/O (94H)................................................................................................. 44
7.25. READ IDENTIFICATION (RDID) (9FH)......................................................................................................................... 45
7.26. PROGRAM/ERASE SUSPEND (PES) (75H)................................................................................................................... 46
7.27. PROGRAM/ERASE RESUME (PER) (7AH) ................................................................................................................... 47
7.28. READ UNIQUE ID (4BH).......................................................................................................................................... 48
7.29. ERASE SECURITY REGISTERS (44H) ............................................................................................................................ 49
7.30. PROGRAM SECURITY REGISTERS (42H)....................................................................................................................... 50
7.31. READ SECURITY REGISTERS (48H) ............................................................................................................................. 51
7.32. SET READ PARAMETERS (C0H) ................................................................................................................................. 52
2
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.33. BURST READ WITH WRAP (0CH)............................................................................................................................... 53
7.34. ENABLE QPI (38H)................................................................................................................................................. 54
7.35. DISABLE QPI (FFH) ................................................................................................................................................ 54
7.36. ENABLE RESET (66H) AND RESET (99H)..................................................................................................................... 55
7.37. READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH)................................................................................................. 56
8. ELECTRICAL CHARACTERISTICS ..............................................................................................................61
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
POWER-ON TIMING ........................................................................................................................................... 61
INITIAL DELIVERY STATE..................................................................................................................................... 61
ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 61
CAPACITANCE MEASUREMENT CONDITIONS .................................................................................................... 62
DC CHARACTERISTICS......................................................................................................................................... 63
AC CHARACTERISTICS......................................................................................................................................... 66
9. ORDERING INFORMATION............................................................................................................................71
9.1.
10.
VALID PART NUMBERS ............................................................................................................................................ 72
PACKAGE INFORMATION .........................................................................................................................74
10.1. PACKAGE SOP8 208MIL ........................................................................................................................................ 74
10.2. PACKAGE VSOP8 208MIL ...................................................................................................................................... 75
10.3. PACKAGE WSON8 (6*5MM)................................................................................................................................... 76
10.4. PACKAGE WSON8 (8*6MM)................................................................................................................................... 77
11.
REVISION HISTORY....................................................................................................................................78
3
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
1. FEATURES
◆ 128M-bit Serial Flash
-16384K-byte
◆ Fast Program/Erase Speed
-Page Program time: 0.5ms typical
-Sector Erase time: 70ms typical
-256 bytes per programmable page
-Block Erase time: 0.16/0.3s typical
-Chip Erase time: 50s typical
◆ Standard, Dual, Quad SPI, QPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
-QPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆ Flexible Architecture
-Uniform Sector of 4K-byte
-Uniform Block of 32/64K-byte
-Erase/Program Suspend/Resume
◆ High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 240Mbits/s
-Quad I/O Data transfer up to 480Mbits/s
-QPI Mode Data transfer up to 480Mbits/s
◆ Low Power Consumption
-35μA typical stand-by current
-1μA typical power down current
◆ Advanced security Features
◆ Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top/Bottom Block protection
-128-bit Unique ID for each device
-3x1024-Byte Security Registers With OTP Lock
◆ Single Power Supply Voltage
-Full voltage range: 1.65~2.0V
◆ Allows XIP (execute in place) Operation
-Continuous Read With 8/16/32/64-byte Wrap
◆ Data Retention
-20-year data retention typical
◆ Minimum 100,000 Program/Erase Cycles
4
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
2. GENERAL DESCRIPTION
The GD25LQ128D (128M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI and QPI mode: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#).
The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed
of 480Mbits/s.
CONNECTION DIAGRAM
CS#
1
2
3
4
8
7
6
5
VCC
CS#
1
2
3
8
7
VCC
SO
(IO0)
HOLD#
(IO3)
SO
(IO0)
HOLD#
(IO3)
Top View
Top View
WP#
(IO2)
WP#
(IO2)
SCLK
6 SCLK
SI
(IO0)
SI
5
VSS
VSS 4
(IO0)
8–LEAD VSOP/SOP
8–LEAD WSON
PIN DESCRIPTION
Pin Name
CS#
I/O
Description
Chip Select Input
I
SO (IO1)
WP# (IO2)
VSS
I/O
I/O
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
SI (IO0)
SCLK
I/O
I
Data Input (Data Input Output 0)
Serial Clock Input
HOLD# (IO3)
VCC
I/O
Hold Input (Data Input Output 3)
Power Supply
Note:
1. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
2. The NC pin/ball is not connected to any internal signal. It is OK to connect it to the system ground (GND) or leave it
floating.
5
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
BLOCK DIAGRAM
Write Control
Logic
WP#(IO2)
Status
Register
Flash
Memory
High Voltage
Generators
HOLD#(IO3)
SCLK
SPI
Command &
Control Logic
Page Address
Latch/Counter
CS#
Column Decode And
256-Byte Page Buffer
SI(IO0)
SO(IO1)
Byte Address
Latch/Counter
6
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
3. MEMORY ORGANIZATION
GD25LQ128D
Each device has
Each block has
Each sector has
Each page has
16M
64K
64/32K
256/128
16/8
4K
16
-
256
bytes
pages
sectors
blocks
-
-
-
4096
256/512
-
-
UNIFORM BLOCK SECTOR ARCHITECTURE
GD25LQ128D 64K Bytes Block Sector Architecture
Block
Sector
Address range
4095
……
4080
4079
……
4064
……
……
……
……
……
……
47
FFF000H
……
FFFFFFH
……
255
FF0000H
FEF000H
……
FF0FFFH
FEFFFFH
……
254
……
……
2
FE0000H
……
FE0FFFH
……
……
……
……
……
……
……
……
……
……
……
02F000H
……
02FFFFH
……
……
32
020000H
01F000H
……
020FFFH
01FFFFH
……
31
1
……
16
010000H
00F000H
……
010FFFH
00FFFFH
……
15
0
……
0
000000H
000FFFH
7
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
4. DEVICE OPERATION
SPI Mode
Standard SPI
The GD25LQ128D features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the
rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25LQ128D supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read”
(3BH and BBH) commands. These commands allow data to be transferred to or from the device at twice the rate of the
standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25LQ128D supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”,
“Quad I/O Word Fast Read”, “Quad Page Program” (6BH, EBH, E7H, 32H) commands. These commands allow data to be
transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and
SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands
require the non-volatile Quad Enable bit (QE) in Status Register to be set.
QPI
The GD25LQ128D supports Quad Peripheral Interface (QPI) operations only when the device is switched from
Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command. The QPI mode utilizes all four IO
pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active
at any given times. “Enable the QPI (38H)” and “Disable the QPI (FFH)” commands are used to switch between these two
modes. Upon power-up and after software reset using “”Reset (99H)” command, the default state of the device is
Standard/Dual/Quad SPI mode. The QPI mode requires the non-volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
8
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
5. DATA PROTECTION
The GD25LQ128D provide the following data protection methods:
◆
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
-Erase Security Registers / Program Security Registers
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory
array that can be read but not change.
◆
◆
◆
Hardware Protection Mode: WP# goes low to protect the BP0~BP4 bits and SRP0~1 bits.
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command and reset command (66H+99H).
Table1. GD25LQ128D Protected area size (CMP=0)
Status Register Content
Memory Content
Addresses
BP4
X
BP3
X
BP2
0
BP1
0
BP0
0
Blocks
NONE
Density
NONE
256KB
512KB
1MB
Portion
NONE
NONE
0
0
0
0
1
252 to 255
248 to 255
240 to 255
224 to 255
192 to 255
128 to 255
FC0000H-FFFFFFH
F80000H-FFFFFFH
F00000H-FFFFFFH
E00000H-FFFFFFH
C00000H-FFFFFFH
800000H-FFFFFFH
000000H-03FFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-1FFFFFH
000000H-3FFFFFH
000000H-7FFFFFH
000000H-FFFFFFH
FFF000H-FFFFFFH
FFE000H-FFFFFFH
FFC000H-FFFFFFH
FF8000H-FFFFFFH
FF8000H-FFFFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
2MB
0
0
1
0
1
4MB
0
0
1
1
0
8MB
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
1
X
0
1
0
1
X
0 to 3
0 to 7
0 to 15
0 to 31
0 to 63
0 to 127
0 to 255
255
256KB
512KB
1MB
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
2MB
4MB
8MB
16MB
4KB
Top Block
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
255
8KB
255
16KB
32KB
32KB
4KB
255
255
0
0
8KB
0
16KB
32KB
0
9
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
1
1
1
1
0
0
000000H-007FFFH
32KB
Bottom Block
Table1a. GD25LQ128D Protected area size (CMP=1)
Memory Content
Status Register Content
BP4
X
BP3
X
BP2
0
BP1
0
BP0
0
Blocks
0 to 255
0 to 251
0 to 247
0 to 239
0 to 223
0 to 191
0 to 127
Addresses
Density
ALL
Portion
ALL
000000H-FFFFFFH
000000H-FBFFFFH
000000H-F7FFFFH
000000H-EFFFFFH
000000H-DFFFFFH
000000H-BFFFFFH
000000H-7FFFFFH
0
0
0
0
1
16128KB
15872KB
15MB
Lower 63/64
Lower 31/32
Lower 15/16
Lower 7/8
Lower 3/4
Lower 1/2
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
14MB
0
0
1
0
1
12MB
0
0
1
1
0
8MB
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
X
0
1
0
1
X
0
4 to 255
8 to 255
16 to 255
32 to 255
64 to 255
128 to 255
NONE
040000H-FFFFFFH
080000H-FFFFFFH
100000H-FFFFFFH
200000H-FFFFFFH
400000H-FFFFFFH
800000H-FFFFFFH
NONE
16128KB
15872KB
15MB
Upper 63/64
Upper 31/32
Upper 15/16
Upper 7/8
14MB
12MB
Upper 3/4
8MB
Upper 1/2
NONE
NONE
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
000000H-FFEFFFH
000000H-FFDFFFH
000000H-FFBFFFH
000000H-FF7FFFH
000000H-FF7FFFH
001000H-FFFFFFH
002000H-FFFFFFH
004000H-FFFFFFH
008000H-FFFFFFH
008000H-FFFFFFH
16380KB
16376KB
16368KB
16352KB
16352KB
16380KB
16376KB
16368KB
16352KB
16352KB
L-4095/4096
L-2047/2048
L-1023/1024
L-511/512
L-511/512
U-4095/4096
U-2047/2048
U-1023/1024
U-511/512
U-511/512
10
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
6. STATUS REGISTER
S15
S14
S13
LB3
S12
LB2
S11
LB1
S10
S9
S8
SUS1
CMP
SUS2
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block
Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set.
The Chip Erase (CE) command is executed, if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block
Protect (BP2, BP1, and BP0) bits are 1 and CMP=1.
SRP1, SRP0 bits
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1 SRP0 #WP
Status Register
Description
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
0
0
0
1
0
1
1
0
1
X
0
Software Protected
WP#=0, the Status Register locked and cannot be written
to.
Hardware Protected
Hardware Unprotected
Power Supply Lock-Down(1)(2)
One Time Program(2)
WP#=1, the Status Register is unlocked and can be written
to after a Write Enable command, WEL=1.
Status Register is protected and cannot be written to again
until the next Power-Down, Power-Up cycle.
Status Register is permanently protected and cannot be
written to.
1
X
X
1
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact GigaDevice for details.
11
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
QE bit
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3
pins are enabled. (It is best to set the QE bit to 0 to avoid short issue if the WP# or HOLD# pin is tied directly to the power
supply or ground.)
LB3, LB2, LB1 bits
The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the
write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are
unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time
Programmable, once they are set to 1, the Security Registers will become read-only permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the BP4-BP0
bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details.
The default setting is CMP=0.
SUS1, SUS2 bits
The SUS1 and SUS2 bits are read only bit in the status register (S15 and S10) that are set to 1 after executing an
Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the
SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command, software reset
(66H+99H) command as well as a power-down, power-up cycle.
12
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, with
most significant bit first on SI, and each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might
be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command
sequence has been completed. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-
Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can
be completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return to
deselected status.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command
is rejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS# being driven
low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and
WEL will not be reset.
Table2. Commands (Standard/Dual/Quad SPI)
Command Name
Byte 1
06H
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
Write Enable
Write Disable
Volatile SR
04H
50H
Write Enable
Read Status Register
05H
(S7-S0)
(S15-S8)
S7-S0
(continuous)
(continuous)
Read Status Register-1 35H
Write Status Register
Read Data
01H
03H
0BH
3BH
S15-S8
A15-A8
A15-A8
A15-A8
A23-A16
A23-A16
A23-A16
A7-A0
A7-A0
A7-A0
(D7-D0)
dummy
dummy
(Next byte) (continuous)
Fast Read
(D7-D0)
(D7-D0)(1)
(continuous)
(continuous)
Dual Output
Fast Read
Dual I/O
Fast Read
BBH
6BH
EBH
E7H
A23-A8(2)
A23-A16
A7-A0
(D7-D0)(1)
A7-A0
(continuous)
(continuous)
(continuous)
(continuous)
M7-M0(2)
Quad Output
Fast Read
A15-A8
dummy
(D7-D0)(3)
Quad I/O
Fast Read
A23-A0
M7-M0(4)
dummy(5)
dummy(6)
(D7-D0)(3)
(D7-D0)(3)
Quad I/O Word
Fast Read(7)
Page Program
Quad Page Program
Sector Erase
Block Erase(32K)
Block Erase(64K)
Chip Erase
A23-A0
M7-M0(4)
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
02H
32H
20H
52H
D8H
C7/60H
38H
66H
99H
77H
75H
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0
D7-D0
Next byte
Enable QPI
Enable Reset
Reset
Set Burst with Wrap
Program/Erase
Suspend
W6-W4
Program/Erase
7AH
13
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
Resume
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
ABH
ABH
dummy
dummy
dummy
(ID7-ID0)
(M7-M0)
(continuous)
Deep Power-Down
Manufacturer/
Device ID
B9H
90H
dummy
A23-A8
dummy
00H
(ID7-ID0)
(continuous)
Manufacturer/
Device ID by Dual I/O
Manufacturer/
Device ID by Quad I/O
Read Identification
Read Unique ID
A7-A0,
M[7:0]
dummy
(M7-M0)
(ID7-ID0)
(M7-M0)
(ID7-ID0)
92H
(continuous)
(continuous)
A23-A0,
M[7:0]
94H
9FH
(M7-M0)
(ID15-ID8) (ID7-ID0)
(continuous)
(continuous)
(UID7-
UID0)
00H
00H
00H
dummy
dummy
4BH
5AH
Read Serial Flash
Discoverable
Parameter(10)
Erase Security
Registers(8)
A23-A16
A15-A8
A7-A0
(D7-D0)
(continuous)
44H
42H
48H
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
Program Security
Registers(8)
D7-D0
D7-D0
Read Security
Registers(8)
dummy
(D7-D0)
Table2a. Commands (QPI)
Command Name
Clock Number
Write Enable
Byte 1
(0,1)
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
(2,3)
(4,5)
(6,7)
(8,9)
(10,11)
(12,13)
06H
Volatile
Enable
SR
Write 50H
Write Disable
04H
05H
35H
15H
01H
02H
20H
52H
D8H
C7/60H
75H
Read Status Register
Read Status Register-1
Read Status Register-2
Write Status Register
Page Program
(S7-S0)
(S15-S8)
(S1-S0)
S7-S0
S15-S8
A15-A8
A15-A8
A15-A8
A15-A8
A23-A16
A23-A16
A23-A16
A23-A16
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0
Next byte
Sector Erase
Block Erase(32K)
Block Erase(64K)
Chip Erase
Program/Erase
Suspend
Program/Erase Resume 7AH
Deep Power-Down
Set Read Parameters
Fast Read
B9H
C0H
0BH
0CH
EBH
ABH
P7-P0
A23-A16
A23-A16
A23-A16
dummy
A15-A8
A15-A8
A15-A8
dummy
A7-A0
A7-A0
A7-A0
dummy
dummy
dummy
M7-M0
(D7-D0)
(D7-D0)
dummy
Burst Read with Wrap
Quad I/O Fast Read
Release From Deep
Power-Down, And
Read Device ID
(D7-D0)
(ID7-ID0)
Manufacturer/
90H
dummy
dummy
00H
(M7-M0)
(ID7-ID0)
14
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
Device ID
Read Identification
Read Serial Flash
Discoverable
Parameter(10)
Disable QPI
9FH
5AH
(M7-M0)
A23-A16
(ID15-ID8) (ID7-ID0)
A15-A8 A7-A0
dummy
(D7-D0)
FFH
66H
99H
Enable Reset
Reset
NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8
IO1 = A23, A21, A19, A17, A15, A13, A11, A9
A6, A4, A2, A0, M6, M4, M2, M0
A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
7. Fast Word Read Quad I/O Data: the lowest address bit must be 0.
8. Security Registers Address:
Security Register1: A23-A16=00H, A15-A10=000100b, A9-A0=Byte Address;
Security Register2: A23-A16=00H, A15-A10=001000b, A9-A0=Byte Address;
Security Register3: A23-A16=00H, A15-A10=001100b, A9-A0=Byte Address.
9. QPI Command, Address, Data input/output format:
CLK #0
1
2
3
4
5
6
7
8
9
10 11
IO0= C4, C0, A20, A16, A12, A8,
IO1= C5, C1, A21, A17, A13, A9,
A4, A0, D4, D0, D4, D0,
A5, A1, D5, D1, D5, D1
IO2= C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2
IO3= C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3
15
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
Table of ID Definitions:
GD25LQ128D
Operation Code
M7-M0
C8
ID15-ID8
ID7-ID0
18
9FH
90H
ABH
60
C8
17
17
16
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL)
bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status
Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS#
goes low sending the Write Enable command CS# goes high.
Figure2. Write Enable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
06H
High-Z
SO
Figure2a. Write Enable Sequence Diagram (QPI)
CS#
0
1
SCLK
Command
06H
IO0
IO1
IO2
IO3
17
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence:
CS# goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-
up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase,
Erase/Program Security Registers and Reset commands.
Figure3. Write Disable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
04H
High-Z
SO
Figure3a. Write Disable Sequence Diagram (QPI)
CS#
0
1
SCLK
Command
04H
IO0
IO1
IO2
IO3
18
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.3. Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the
system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or
affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command
must be issued prior to a Write Status Register command, and any other commands cannot be inserted between them.
Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command
will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status
Register bit values.
Figure4. Write Enable for Volatile Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command(50H)
High-Z
SI
SO
Figure4a. Write Enable for Volatile Status Register Sequence Diagram (QPI)
CS#
0
1
SCLK
Command
50H
IO0
IO1
IO2
IO3
19
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.4. Read Status Register (RDSR) (05H or 35H or 15H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress,
it is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible
to read the Status Register continuously. For command code “05H” / “35H”, the SO will output Status Register bits S7~S0
/ S15-S8. The command code “15H” only supports the QPI mode, the I/O0 will output Status Register S1-S0. (For 120MHz
Frequency, the 15H will better than 05H to check the WIP bit)
Figure5. Read Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
Command
05H or 35H
S7~S0 or S15~S8 out
S7~S0 or S15~S8 out
SO
High-Z
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure5a. Read Status Register Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
SCLK
Command
05H or 35H
4
5
0
1
2
3
4
5
6
7
0
1
4
5
6
7
IO0
IO1
IO2
IO3
6
2
7
3
S7-S0 or S15-S8 out
20
1.8V Uniform Sector
Dual and Quad Serial Flash
Figure5b. Read Status Register Sequence Diagram (QPI) (15H)
GD25LQ128D
CS#
0
1
2
3
4
5
SCLK
Command
15H
S1
S0
S1
S0
IO0
S1-S0 out
IO1
IO2
IO3
7.5. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register. CS# must
be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register (WRSR)
command is not executed. If CS# is driven high after eighth bit of the data byte, the CMP and QE bits will be cleared to 0 in
SPI mode, while only CMP will be cleared to 0 in QPI mode. As soon as CS# is driven high, the self-timed Write Status
Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register
may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-
timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL)
is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3,
BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write
Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits
in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect
(WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is
not executed once the Hardware Protected Mode is entered.
Figure6. Write Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Status Register in
SCLK
Command
01H
SI
7
6
5
4
3
2
1
0
11 10 9
8
15 14 13 12
MSB
High-Z
SO
21
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
Figure6a. Write Status Register Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
SCLK
Command
01H
4
5
6
7
0
1
2
3
12
8
9
IO0
13
IO1
IO2
IO3
14 10
15 11
Status Register in
7.6. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit is latched-in on the
rising edge of SCLK. Then the memory content at that address is shifted out on SO, each bit being shifted out, at a Max
frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure7. Read Data Bytes Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
Command
03H
24-bit address
23 22 21
MSB
3
2
1
0
Data Out1
Data Out2
High-Z
SO
7
6
5
4
3
2
1
0
MSB
22
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,
at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out.
Figure8. Read Data Bytes at Higher Speed Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
0BH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
Fast Read (0BH) in QPI mode
The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is configured by
the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either
maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the
number of dummy clocks can be configured as either 4/6/8/8.
Figure8a. Read Data Bytes at Higher Speed Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13
SCLK
Command
0BH
IOs switch from
Input to output
Dummy*
A23-16 A15-8 A7-0
IO0
IO1
IO2
IO3
20 16 12
8
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
21 17 13
9
22 18 14 10
23 19 15 11
Byte1 Byte2
*"Set Read Parameters" Command (C0H)
can set the number of dummy clocks
23
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.8. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure9. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure9. Dual Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
3BH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
SI
6
4
2
0
6
4
2
0
6
7
Data Out1
Data Out2
SO
7
5
3
1
7
5
3
1
MSB
MSB
24
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.9. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1
and IO0. The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
Figure10. Quad Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
6BH
24-bit address
23 22 21
SI(IO0)
3
2
1
0
SO(IO1)
High-Z
High-Z
High-Z
WP#(IO2)
HOLD#(IO3)
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Byte1 Byte2 Byte3 Byte4
25
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.10. Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input
the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in
during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command
sequence is shown in followed Figure11. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Dual
I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command
sequence is shown in followed Figure11. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command
requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can
be used to reset (M5-4) before issuing normal command.
Figure11. Dual I/O Fast Read Sequence Diagram (M5-4≠ (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
BBH
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
7
A23-16
A15-8
A7-0
M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
26
1.8V Uniform Sector
Dual and Quad Serial Flash
Figure11a. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0))
GD25LQ128D
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
6
4
2
0
6
4
2
0
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
7
5
3
1
7
5
3
1
7
A23-16
A15-8
A7-0
M7-0
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
7.11. Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the
3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each
bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,
IO1, IO2, IO3. The command sequence is shown in followed Figure12. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit
(QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next
Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The
command sequence is shown in followed Figure12a. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the
next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset
command can be used to reset (M5-4) before issuing normal command.
27
1.8V Uniform Sector
Dual and Quad Serial Flash
Figure12. Quad I/O Fast Read Sequence Diagram (M5-4≠ (1, 0))
GD25LQ128D
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
EBH
SI(IO0)
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
WP#(IO2)
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Figure12a. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
WP#(IO2)
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI Mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with
Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap
Around” feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited
to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command,
once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary
automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache
afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap”
command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation
while W6-W5 is used to specify the length of the wrap around section within a page.
Quad I/O Fast Read (EBH) in QPI Mode
The Quad I/O Fast Read command is also supported in QPI mode. See Figure12b. In QPI mode, the number of dummy
clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with different
needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits
28
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8/8. In QPI mode, the “Continuous Read Mode”
bits M7-M0 are also considered as dummy clocks. “Continuous Read Mode” feature is also available in QPI mode for Quad
I/O Fast Read command. “Wrap Around” feature is not available in QPI mode for Quad I/O Fast Read command. To perform
a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0CH) command
must be used.
Figure12b. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0) QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCLK
IO0
Command
EBH
IOs switch from
Input to output
20 16 12
21 17 13
8
9
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
IO1
IO2
IO3
5
22 18 14 10
6
7
*"Set Read Parameters"
Command (C0H) can
set the number of
dummy clocks
23 19 15 11
A23-16 A15-8 A7-0
M7-0* dummy* Byte1 Byte2
29
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.12. Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest
address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure13. The first
byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte
of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast
read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then
the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command
code. The command sequence is shown in followed Figure13. If the “Continuous Read Mode” bits (M5-4) do not equal to
(1, 0), the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read
Mode” Reset command can be used to reset (M5-4) before issuing normal command.
Figure13. Quad I/O Word Fast Read Sequence Diagram (M5-4≠ (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
E7H
SI(IO0)
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
WP#(IO2)
HOLD#(IO3)
Dummy
A23-16 A15-8 A7-0 M7-0
Byte1 Byte2 Byte3
Figure13a. Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
WP#(IO2)
HOLD#(IO3)
Dummy
A23-16 A15-8 A7-0 M7-0
Byte1 Byte2 Byte3
Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI Mode
The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst
with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap
Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be limited
30
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command,
once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary
automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache
afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap”
command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation
while W6-W5 is used to specify the length of the wrap around section within a page.
7.13. Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word Fast Read”
command to access a fixed length of 8/16/32/64-byte section within a 256-byte page.
The Set Burst with Wrap command sequence: CS# goes low Send Set Burst with Wrap command Send 24
dummy bits Send 8 bits “Wrap bits” CS# goes high.
W4=0
W4=1 (default)
W6,W5
Wrap Around
Wrap Length
8-byte
Wrap Around
Wrap Length
0, 0
0, 1
1, 0
1, 1
Yes
Yes
Yes
Yes
No
No
No
No
N/A
N/A
N/A
N/A
16-byte
32-byte
64-byte
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and “Quad I/O
Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the
“Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set
W4=1. In QPI mode, the “Burst Read with Wrap (0CH)” command should be used to perform the Read Operation with “Wrap
Around” feature. The Wrap Length set by W5-W6 in Standard SPI mode is still valid in QPI mode and can also be re-
configured by “Set Read Parameters (C0H) command.
Figure14. Set Burst with Wrap Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
77H
SI(IO0)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
5
6
x
x
x
x
x
SO(IO1)
x
x
x
WP#(IO2)
HOLD#(IO3)
W6-W4
31
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.14. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address
bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data
that goes beyond the end of the current page are programmed from the start address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The
Page Program command sequence: CS# goes low sending Page Program command 3-byte address on SI at least
1 byte data on SI CS# goes high. The command sequence is shown in Figure15. If more than 256 bytes are sent to the
device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within
the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses
without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data
byte has been latched in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and
BP0) is not executed.
Figure15. Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
Command
02H
24-bit address
23 22 21
MSB
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
32
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
Figure15a. Page Program Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13
SCLK
Command
02H
Byte1 Byte2
Byte3
Byte255 Byte256
A23-16 A15-8 A7-0
IO0
20 16 12
8
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO1
IO2
IO3
21 17 13
9
5
6
7
22 18 14 10
23 19 15 11
33
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.15. Quad Page Program (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use
Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The
quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address bytes
and at least one data byte on IO pins.
The command sequence is shown in Figure16. If more than 256 bytes are sent to the device, previously latched data
are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than
256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on
the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in;
otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the
Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) is not executed.
Figure16.Quad Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
32H
24-bit address
23 22 21
MSB
Byte1 Byte2
SI(IO0)
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Byte11Byte12
SCLK
Byte253
Byte256
SI(IO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
34
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.16. Sector Erase (SE) (20H)
The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by
driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address
for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low sending Sector Erase command 3-byte address on SI
CS# goes high. The command sequence is shown in Figure17. CS# must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven
high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the
Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected
by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit (see Table1&1a) is not executed.
Figure17. Sector Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
20H
24 Bits Address
23 22
MSB
2
1
0
Figure17a. Sector Erase Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
20H
A23-16 A12-8 A7-0
20 16 12
8
4
0
1
2
3
IO0
21 17 13
9
5
IO1
IO2
IO3
22 18 14 10
23 19 15 11
6
7
35
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.17. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is
entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block
is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low sending 32KB Block Erase command 3-byte address
on SI CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the
last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tSE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure18. 32KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
52H
24 Bits Address
23 22
MSB
2
1
0
Figure18a. 32KB Block Erase Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
52H
A23-16 A12-8 A7-0
20 16 12
8
4
0
1
2
3
IO0
21 17 13
9
5
IO1
IO2
IO3
22 18 14 10
23 19 15 11
6
7
36
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.18. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is
entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block
is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low sending 64KB Block Erase command 3-byte address
on SI CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of the
last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tSE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure19. 64KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
D8H
24 Bits Address
23 22
MSB
2
1
0
Figure19a. 64KB Block Erase Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
D8H
A23-16 A15-8
A7-0
IO0
20 16 12
8
4
0
1
2
3
21 17 13
9
IO1
IO2
IO3
5
6
7
22
14 10
18
23 19 15 11
37
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.19. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low,
followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low sending Chip Erase command CS# goes high. The
command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the command code has been
latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase
cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check
the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and
is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block
Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. The Chip Erase (CE) command is ignored if one or more sectors are
protected.
Figure20. Chip Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
60H or C7H
Figure20a. Chip Erase Sequence Diagram (QPI)
CS#
0
1
SCLK
Instruction
C7H/60H
IO0
IO1
IO2
IO3
38
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.20. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode
(the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in
active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the
device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the
Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP)
command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down and Read Device ID (RDI (ABH) or Enable Reset (66H) and Reset (99H) commands. These commands
can release the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI) command releases
the device from deep power down mode , also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device is in the Standby Mode after Power-
Up. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS# must
be driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low sending Deep Power-Down command CS# goes
high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has
been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires
a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-
Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
Figure21. Deep Power-Down Sequence Diagram
CS#
tDP
0
1
2
3
4
5
6
7
SCLK
SI
Command
B9H
Stand-by mode Deep Power-down mode
Figure21a. Deep Power-Down Sequence Diagram (QPI)
CS#
tDP
0
1
SCLK
Command
B9H
IO0
IO1
IO2
IO3
Stand-by mode
Deep Power-down mode
39
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.21. Release from Deep Power-Down and Read Device ID (RDI) (ABH)
The Release from Power-Down and Read Device ID command is a multi-purpose command. It can be used to release
the device from the Power-Down state or obtain the devices electronic identification (ID) number.
To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the
instruction code “ABH” and driving CS# high as shown in Figure22. Release from Power-Down will take the time duration
of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The
CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the
CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure23. The Device ID value for the
GD25LQ128D is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The
command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the same
as previously described, and shown in Figure23, except that after CS# is driven high it must remain high for a time
duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other
command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or
Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle.
Figure22. Release Power-Down Sequence Diagram
CS#
tRES1
0
1
2
3
4
5
6
7
SCLK
SI
Command
ABH
Deep Power-down mode
Stand-by mode
Figure22a. Release Power-Down Sequence Diagram (QPI)
CS#
tRES1
0
1
SCLK
Command
ABH
IO0
IO1
IO2
IO3
Deep Power-down mode
Stand-by mode
40
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
Figure23. Release Power-Down/Read Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
SCLK
tRES2
Command
ABH
3 Dummy Bytes
23 22
MSB
SI
2
1
0
Device ID
SO
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode Stand-by Mode
Figure23a. Release Power-Down/Read Device ID Sequence Diagram (QPI)
CS#
tRES2
0
1
2
3
4
5
6
7
8
SCLK
Command
ABH
IOs switch from
Input to Output
3 Dummy Bytes
IO0
4
5
0
1
2
3
IO1
IO2
IO3
6
7
Device
ID
Deep Power-down mode
Stand-by mode
41
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.22. Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command
that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure24. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure24. Read Manufacture ID/ Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
24-bit address
23 22 21
SI
90H
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
Device ID
Manufacturer ID
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
Figure24a. Read Manufacture ID/ Device ID Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10
IOs switch from
SCLK
Command
90H
A7-0
(00H)
Input to Output
A23-16 A15-8
IO0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
12
8
4
5
6
7
20 16
IO1
IO2
IO3
1
2
3
9
1
2
3
21 17 13
18
14 10
15 11
22
23 19
Device
ID
MID
42
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.23. Read Manufacture ID/ Device ID Dual I/O (92H)
The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O.
The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure25. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure25. Read Manufacture ID/ Device ID Dual I/O Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
92H
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
7
A23-16
A15-8
A7-0
M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
MFR ID
(Repeat)
MFR ID
Device ID
Device ID
(Repeat)
MFR ID
(Repeat)
Device ID
(Repeat)
43
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.24. Read Manufacture ID/ Device ID Quad I/O (94H)
The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O.
The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure26. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure26. Read Manufacture ID/ Device ID Quad I/O Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
94H
SI(IO0)
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
5
6
7
WP#(IO2)
HOLD#(IO3)
MFR ID DID
A23-16 A15-8 A7-0 M7-0
Dummy
CS#
24 25 26 27 28 29 30 31
SCLK
SI(IO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
MFR ID DID
MFR ID DID
(Repeat()Repeat)
(Repeat()Repeat)
44
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.25. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes
of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the
device in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is
followed by the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock.
The command sequence is shown in Figure27. The Read Identification (RDID) command is terminated by driving CS# high
at any time during data output. When CS# is driven high, the device is in the Standby Mode. Once in the Standby Mode,
the device waits to be selected, so that it can receive, decode and execute commands.
Figure27. Read Identification ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
9FH
Manufacturer ID
7
6
5
4
3
2
1
0
SO
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
Memory Type ID15-ID8
Capacity ID7-ID0
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
Figure27a. Read Identification ID Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
SCLK
IOs switch from
Input to Output
Command
9FH
4
0
12
8
4
0
1
2
3
IO0
IO1
IO2
IO3
5
1
2
3
13
9
5
6
14 10
15 11
6
7
7
MID ID15-8 ID7-0
45
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.26. Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase
operation and then read data from any other sector or block. The Write Status Register command (01H/31H/11H) and
Erase/Program Security Registers command (44H, 42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page
Program command (02H, 32H) are not allowed during Program suspend. The Write Status Register command
(01H/31H/11H) and Erase Security Registers command (44H) and Erase commands (20H, 52H, D8H, C7H, 60H) are not
allowed during Erase suspend. Program/Erase Suspend is valid only during the page program or sector/block erase
operation. A maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation
The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status
Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the
SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be
cleared from 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend.
A power-off during the suspend period will reset the device and release the suspend state. The command sequence is show
in Figure28.
Figure28. Program/Erase Suspend Sequence Diagram
CS#
0
1
2
3
4
5
6
7
tSUS
SCLK
SI
Command
75H
High-Z
SO
Accept read command
Figure28a. Program/Erase Suspend Sequence Diagram (QPI)
CS#
tSUS
0
1
SCLK
Command
75H
IO0
IO1
IO2
IO3
Accept Read
46
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.27. Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation after
a Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the
SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared
from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase
operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a
Program/Erase Suspend is active. The command sequence is show in Figure29.
Figure29. Program/Erase Resume Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
7AH
SO
Resume Erase/Program
Figure29a. Program/Erase Resume Sequence Diagram (QPI)
CS#
0
1
SCLK
Command
7AH
IO0
IO1
IO2
IO3
Resume previously suspended
program or Erase
47
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.28. Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The
Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low sending Read Unique ID command 3-Byte Address
(000000H) Dummy Byte128bit Unique ID Out CS# goes high.
Figure30. Read Unique ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
24-bit address
Command
4BH
(000000H)
3
23 22 21
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
48
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.29. Erase Security Registers (44H)
The GD25LQ128D provides three 1024-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information separately from
the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low sending Erase Security Registers command
3-byte address on SI CS# goes high. The command sequence is shown in Figure30. CS# must be driven high after the
eighth bit of the last address byte has been latched in; otherwise the Erase Security Registers command is not executed.
As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the
Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress
(WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security
Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set
to 1, the Security Registers will be permanently locked; the Erase Security Registers command will be ignored.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
Don’t Care
Don’t Care
Don’t Care
00H
0 0
00H
0 0
Figure31. Erase Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
44H
24 Bits Address
23 22
SI
2
1
0
MSB
49
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.30. Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. Each security register contains
four pages of contents. It allows from 1 to 1024 bytes Security Registers data to be programmed. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security
Registers command. The Program Security Registers command is entered by driving CS# Low, followed by the command
code (42H), three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program
Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the
Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program
Security Registers command will be ignored.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00H
0 0
00H
0 0
Figure32. Program Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
42H
24-bit address
23 22 21
MSB
Data Byte 1
SI
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
SI
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
50
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.31. Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,
at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H,
the command is completed by driving CS# high.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00H
0 0
00H
0 0
Figure33. Read Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
48H
24-bit address
23 22 21
SI
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
51
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.32. Set Read Parameters (C0H)
In QPI mode the “Set Read Parameters (C0H)” command can be used to configure the number of dummy clocks for
“Fast Read (0BH)”, “Quad I/O Fast Read (EBH)” and “Burst Read with Wrap (0CH)” command, and to configure the number
of bytes of “Wrap Length” for the “Burst Read with Wrap (0CH)” command. The “Wrap Length” is set by W5-6 bit in the “Set
Burst with Wrap (77H)” command. This setting will remain unchanged when the device is switched from Standard SPI mode
to QPI mode.
Maximum Read Freq.
Dummy
Clocks
P5-P4
P1-P0
Wrap Length
-40~85℃
80MHz
-40~105℃
-40~125℃
60MHz
0 0
0 1
1 0
1 1
4
6
8
8
60MHz
80MHz
0 0
0 1
1 0
1 1
8-byte
16-byte
32-byte
64-byte
108MHz
120MHz
120MHz
80MHz
104MHz
104MHz
104MHz
104MHz
Figure34. Set Read Parameters command Sequence Diagram
CS#
0
1
2
3
SCLK
Command
C0H
Read
Parameters
P4 P0
IO0
P5 P1
P6 P2
P7 P3
IO1
IO2
IO3
52
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.33. Burst Read with Wrap (0CH)
The “Burst Read with Wrap (0CH)” command provides an alternative way to perform the read operation with “Wrap
Around” in QPI mode. This command is similar to the “Fast Read (0BH)” command in QPI mode, except the addressing of
the read operation will “Wrap Around” to the beginning boundary of the “Wrap Around” once the ending boundary is reached.
The “Wrap Length” and the number of dummy clocks can be configured by the “Set Read Parameters (C0H)” command.
Figure35. Burst Read with Wrap command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCLK
IO0
Command
0CH
IOs switch from
Input to output
20 16 12
21 17 13
8
9
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO1
IO2
IO3
22 18 14 10
23 19 15 11
A23-16 A15-8
A7-0
Byte1 Byte2 Byte3
Dummy*
*"Set Read Parameters" Command (C0H)
can set the number of dummy clocks
53
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.34. Enable QPI (38H)
The device support both Standard/Dual/Quad SPI and QPI mode. The “Enable QPI (38H)” command can switch the
device from SPI mode to QPI mode. See the command Table 2a for all support QPI commands. In order to switch the device
to QPI mode, the Quad Enable (QE) bit in Status Register-1 must be set to 1 first, and “Enable QPI (38H)” command must
be issued. If the QE bit is 0, the “Enable QPI (38H)” command will be ignored and the device will remain in SPI mode. When
the device is switched from SPI mode to QPI mode, the existing Write Enable Latch and Program/Erase Suspend status,
and the Wrap Length setting will remain unchanged.
Figure36. Enable QPI mode command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
38H
7.35. Disable QPI (FFH)
To exit the QPI mode and return to Standard/Dual/Quad SPI mode, the “Disable QPI (FFH)” command must be
issued. When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch and Program/Erase
Suspend status, and the Wrap Length setting will remain unchanged.
Figure37. Disable QPI mode command Sequence Diagram
CS#
0
1
SCLK
Command
FFH
IO0
IO1
IO2
IO3
54
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.36. Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its
default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch
status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read Mode bit setting (M7-
M0) and Wrap Bit Setting (W6-W4).
The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI or QPI mode. The “Reset
(99H)” command sequence as follow: CS# goes low Sending Enable Reset command CS# goes high CS# goes
low Sending Reset command CS# goes high. Once the Reset command is accepted by the device, the device will
take approximately tRST / tRST_E to reset. During this period, no command will be accepted. Data corruption may happen if
there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the
device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command
sequence.
Figure38. Enable Reset and Reset command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCLK
SI
Command
66H
Command
99H
High-Z
SO
Figure39. Enable Reset and Reset command Sequence Diagram (QPI)
CS#
0
0
1
1
SCLK
Command
66H
Command
99H
IO0
IO1
IO2
IO3
55
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
7.37. Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can
be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple
vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard
of JEDEC Standard No.216.
Figure40. Read Serial Flash Discoverable Parameter command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
5AH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
Figure39a. Read Serial Flash Discoverable Parameter command Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13
SCLK
IO0
Command
5AH
IOs switch from
Input to output
Dummy*
A23-16 A15-8 A7-0
20 16 12
8
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO1
IO2
IO3
21 17 13
9
22 18 14 10
23 19 15 11
Byte1 Byte2
56
1.8V Uniform Sector
Dual and Quad Serial Flash
Table3. Signature and Parameter Identification Data Values
GD25LQ128D
Description
Comment
Add(H)
(Byte)
DW Add
Data
Data
(Bit)
SFDP Signature
Fixed:50444653H
00H
01H
02H
03H
04H
05H
06H
07H
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
53H
46H
44H
50H
00H
01H
01H
FFH
53H
46H
44H
50H
00H
01H
01H
FFH
SFDP Minor Revision Number
SFDP Major Revision Number
Number of Parameters Headers
Unused
Start from 00H
Start from 01H
Start from 00H
Contains 0xFFH and can never be
changed
ID number (JEDEC)
00H: It indicates a JEDEC specified
header
08H
09H
0AH
0BH
07:00
15:08
23:16
31:24
00H
00H
01H
09H
00H
00H
01H
09H
Parameter Table Minor Revision
Number
Start from 0x00H
Parameter Table Major Revision
Number
Start from 0x01H
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
0CH
0DH
0EH
0FH
07:00
15:08
23:16
31:24
30H
00H
00H
FFH
30H
00H
00H
FFH
Unused
Contains 0xFFH and can never be
changed
ID Number LSB
It is indicates GigaDevice
manufacturer ID
10H
11H
12H
13H
07:00
15:08
23:16
31:24
C8H
00H
01H
03H
C8H
00H
01H
03H
(GigaDevice Manufacturer ID)
Parameter Table Minor Revision
Number
Start from 0x00H
Parameter Table Major Revision
Number
Start from 0x01H
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
Parameter Table Pointer (PTP)
First address of GigaDevice Flash
Parameter table
14H
15H
16H
17H
07:00
15:08
23:16
31:24
60H
00H
00H
FFH
60H
00H
00H
FFH
Unused
Contains 0xFFH and can never be
changed
57
1.8V Uniform Sector
Dual and Quad Serial Flash
Table4. Parameter Table (0): JEDEC Flash Parameter Tables
GD25LQ128D
Description
Comment
Add(H)
(Byte)
DW Add
Data
Data
(Bit)
01:00
02
00: Reserved; 01: 4KB erase;
10: Reserved;
Block/Sector Erase Size
01b
1b
11: not support 4KB erase
0: 1Byte, 1: 64Byte or larger
0: Nonvolatile status bit
1: Volatile status bit
Write Granularity
Write Enable Instruction
Requested for Writing to Volatile
Status Registers
03
0b
(BP status register bit)
0: Use 50H Opcode,
30H
E5H
Write Enable Opcode Select for
Writing to Volatile Status
Registers
1: Use 06H Opcode,
Note: If target flash status register is
Nonvolatile, then bits 3 and 4 must
be set to 00b.
04
0b
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Opcode
31H
32H
15:08
16
20H
1b
20H
F1H
FFH
(1-1-2) Fast Read
0=Not support, 1=Support
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
Address Bytes Number used in
addressing flash array
Double Transfer Rate (DTR)
clocking
18:17
19
00b
0b
0=Not support, 1=Support
(1-2-2) Fast Read
0=Not support, 1=Support
0=Not support, 1=Support
0=Not support, 1=Support
20
21
1b
1b
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
22
1b
23
1b
Unused
33H
31:24
31:00
FFH
Flash Memory Density
37H:34H
07FFFFFFH
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
00100b
states
Clocks) not support
38H
39H
3AH
44H
EBH
08H
(1-4-4) Fast Read Number of
Mode Bits
000b:Mode Bits not support
07:05
15:08
20:16
010b
EBH
(1-4-4) Fast Read Opcode
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
01000b
states
Clocks) not support
(1-1-4) Fast Read Number of
Mode Bits
000b:Mode Bits not support
23:21
31:24
04:00
07:05
000b
6BH
(1-1-4) Fast Read Opcode
3BH
3CH
6BH
08H
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
01000b
000b
states
Clocks) not support
(1-1-2) Fast Read Number
000b: Mode Bits not support
58
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
of Mode Bits
(1-1-2) Fast Read Opcode
(1-2-2) Fast Read Number
of Wait states
3DH
3EH
3FH
15:08
20:16
3BH
3BH
0 0000b: Wait states (Dummy
Clocks) not support
00010b
42H
(1-2-2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
23:21
010b
(1-2-2) Fast Read Opcode
31:24
00
BBH
0b
BBH
(2-2-2) Fast Read
Unused
0=not support
1=support
03:01
04
111b
1b
40H
FEH
(4-4-4) Fast Read
Unused
0=not support 1=support
07:05
31:08
15:00
111b
0xFFH
0xFFH
Unused
43H:41H
45H:44H
0xFFH
0xFFH
Unused
(2-2-2) Fast Read Number
of Wait states
0 0000b: Wait states (Dummy
Clocks) not support
20:16
23:21
00000b
000b
46H
00H
(2-2-2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
(2-2-2) Fast Read Opcode
47H
31:24
15:00
FFH
FFH
Unused
49H:48H
0xFFH
0xFFH
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
00100b
states
Clocks) not support
4AH
44H (1)
(4-4-4) Fast Read Number
of Mode Bits
000b: Mode Bits not support
23:21
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
010b
EBH
0CH
20H
0FH
52H
10H
D8H
00H
FFH
(4-4-4) Fast Read Opcode
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
EBH
0CH
20H
0FH
52H
10H
D8H
00H
FFH
Sector/block size=2^N bytes
Sector Type 1 Size
0x00b: this sector type don’t exist
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 4 erase Opcode
59
1.8V Uniform Sector
Dual and Quad Serial Flash
Table5. Parameter Table (1): GigaDevice Flash Parameter Tables
GD25LQ128D
Add(H)
(Byte)
DW Add
Description
Comment
Data
Data
(Bit)
2000H=2.000V
Vcc Supply Maximum Voltage
2700H=2.700V
61H:60H
15:00
2000H
1650H
2000H
1650H
3600H=3.600V
1650H=1.650V
2250H=2.250V
Vcc Supply Minimum Voltage
63H:62H
31:16
2350H=2.350V
2700H=2.700V
HW Reset# pin
HW Hold# pin
0=not support 1=support
00
01
02
03
0b
1b
1b
1b
0=not support 1=support
0=not support 1=support
Deep Power Down Mode
SW Reset
0=not support 1=support
Should be issue Reset Enable(66H)
before Reset cmd.
SW Reset Opcode
65H:64H
11:04
99H
F99EH
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
12
13
1b
1b
0=not support 1=support
0=not support 1=support
14
1b
Wrap-Around Read mode
Wrap-Around Read mode Opcode
15
1b
66H
67H
23:16
77H
77H
64H
08H:support 8B wrap-around read
16H:8B&16B
Wrap-Around Read data length
Individual block lock
31:24
64H
32H:8B&16B&32B
64H:8B&16B&32B&64B
0=not support 1=support
00
01
0b
0b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
Individual block lock Opcode
09:02
10
FFH
0b
Individual block lock Volatile
0=protect 1=unprotect
EBFCH
protect bit default protect status
6BH:68H
Secured OTP
Read Lock
Permanent Lock
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
13
1b
15:14
31:16
11b
Unused
FFFFH
FFFFH
60
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
8. ELECTRICAL CHARACTERISTICS
8.1. POWER-ON TIMING
Figure41. Power-on Timing
Vcc(max)
Vcc(min)
VWI
Chip Selection is not allowed
Device is fully
accessible
tVSL
Time
Table6. Power-Up Timing And Write Inhibit Threshold
Parameter
Symbol
Min
2.5
Max
Unit
ms
tVSL
VWI
VCC (min) To CS# Low
Write Inhibit Voltage VCC (min)
1
1.5
V
8.2. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register
contains 00H (all Status Register bits are 0).
8.3. ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
Ambient Operating Temperature
-40 to 85
-40 to 105
℃
-40 to 125
Storage Temperature
-65 to 150
℃
V
Applied Input/Output Voltage
Transient Input/Output Voltage (note: overshoot)
VCC
-0.6 to VCC+0.4
-2.0 to VCC+2.0
-0.6 to 2.5
V
V
61
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
Figure42. Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
8.4. CAPACITANCE MEASUREMENT CONDITIONS
Symbol
CIN
Parameter
Min
Typ.
Max
6
Unit
Conditions
Input Capacitance
pF
pF
pF
ns
V
VIN=0V
COUT
CL
Output Capacitance
8
VOUT=0V
Load Capacitance
30
Input Rise And Fall time
Input Pause Voltage
5
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
V
V
Figure43. Input Test Waveform and Measurement Level
Input timing reference level
0.7VCC
Output timing reference level
0.5VCC
0.8VCC
0.1VCC
AC Measurement Level
0.2VCC
Note: Input pulse rise and fall time are<5ns
62
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
8.5. DC CHARACTERISTICS
(T= -40℃~85℃, VCC=1.65~2.0V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ.
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
VIN=VCC or VSS
Deep Power-Down Current CS#=VCC,
VIN=VCC or VSS
35
1
50
μA
ICC2
8
μA
CLK=0.1VCC /
0.9VCC
15
13
20
mA
at 120MHz,
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC /
0.9VCC
ICC3
Operating Current (Read)
Operating Current (PP)
18
mA
at 80MHz,
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
20
20
mA
mA
mA
mA
mA
V
Operating Current (WRSR) CS#=VCC
Operating Current (SE)
Operating Current (BE)
Operating Current (CE)
Input Low Voltage
CS#=VCC
CS#=VCC
CS#=VCC
20
20
20
-0.5
0.2VCC
VCC+0.4
0.2
VIH
Input High Voltage
0.7VCC
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =100μA
IOH =-100μA
V
VCC-0.2
V
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
63
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
(T= -40℃~105℃, VCC=1.65~2.0V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ.
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
VIN=VCC or VSS
Deep Power-Down Current CS#=VCC,
VIN=VCC or VSS
35
1
100
μA
ICC2
30
20
μA
CLK=0.1VCC /
0.9VCC
15
13
mA
at 104MHz,
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC /
0.9VCC
ICC3
Operating Current (Read)
Operating Current (PP)
18
mA
at 80MHz,
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
25
25
mA
mA
mA
mA
mA
V
Operating Current (WRSR) CS#=VCC
Operating Current (SE)
Operating Current (BE)
Operating Current (CE)
Input Low Voltage
CS#=VCC
CS#=VCC
CS#=VCC
25
25
25
-0.5
0.2VCC
VCC+0.4
0.2
VIH
Input High Voltage
0.7VCC
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =100μA
IOH =-100μA
V
VCC-0.2
V
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
64
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
(T= -40℃~125℃, VCC=1.65~2.0V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ.
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
VIN=VCC or VSS
Deep Power-Down Current CS#=VCC,
VIN=VCC or VSS
35
1
120
μA
ICC2
40
20
μA
CLK=0.1VCC /
0.9VCC
15
13
mA
at 104MHz,
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC /
0.9VCC
ICC3
Operating Current (Read)
Operating Current (PP)
18
mA
at 80MHz,
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
25
25
mA
mA
mA
mA
mA
V
Operating Current (WRSR) CS#=VCC
Operating Current (SE)
Operating Current (BE)
Operating Current (CE)
Input Low Voltage
CS#=VCC
CS#=VCC
CS#=VCC
25
25
25
-0.5
0.2VCC
VCC+0.4
0.2
VIH
Input High Voltage
0.7VCC
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =100μA
IOH =-100μA
V
VCC-0.2
V
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
65
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
8.6. AC CHARACTERISTICS
(T= -40℃~85℃, VCC=1.65~2.0V, CL=30pf)
Symbol
fC
Parameter
Min.
Typ.
Max.
120
80
Unit.
MHz
MHz
ns
Serial Clock Frequency For: all command except for 03H
Serial Clock Frequency For: Read (03H)
Serial Clock High Time
fR
tCLH
3.5
3.5
0.1
0.1
5
Serial Clock Low Time
tCLL
ns
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
V/ns
V/ns
ns
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
5
ns
CS# Not Active Hold Time
5
ns
CS# High Time (Read/Write)
20
ns
Output Disable Time
6
ns
Output Hold Time
1.2
2
ns
Data In Setup Time
ns
Data In Hold Time
2
ns
Hold# Low Setup Time (Relative To Clock)
Hold# High Setup Time (Relative To Clock)
Hold# High Hold Time (Relative To Clock)
Hold# Low Hold Time (Relative To Clock)
Hold# Low To High-Z Output
5
ns
5
ns
5
ns
5
ns
6
6
7
6
ns
Hold# Low To Low-Z Output
ns
Clock Low To Output Valid (CL = 30pF)
Clock Low To Output Valid (CL = 15pF)
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
CS# High To Next Command After Reset (Except From Erase)
CS# High To Next Command After Reset (From Erase)
CS# High To Standby Mode Without Electronic Signature Read
CS# High To Standby Mode With Electronic Signature Read
CS# High To Next Command After Suspend
Latency Between Resume And Next Suspend
Write Status Register Cycle Time
Page Programming Time
ns
tCLQV
ns
tWHSL
tSHWL
tDP
20
ns
100
ns
20
30
12
20
20
20
μs
tRST
tRST_E
tRES1
tRES2
tSUS
tRS
μs
ms
μs
μs
μs
100
μs
tW
5
30
2.4
400
0.8
1.2
ms
ms
ms
s
tPP
0.5
70
Sector Erase Time
tSE
Block Erase Time (32K Bytes)
tBE1
tBE2
0.16
0.3
Block Erase Time (64K Bytes)
s
66
1.8V Uniform Sector
Dual and Quad Serial Flash
Chip Erase Time (GD25LQ128D)
GD25LQ128D
tCE
50
120
s
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
67
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
(T= -40℃~105℃, VCC=1.65~2.0V, CL=30pf)
Symbol
fC
Parameter
Serial Clock Frequency For: all command except for 03H
Serial Clock Frequency For: Read (03H)
Serial Clock High Time
Min.
Typ.
Max.
104
80
Unit.
MHz
MHz
ns
fR
tCLH
4.0
4.0
0.2
0.2
5
tCLL
Serial Clock Low Time
ns
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
V/ns
V/ns
ns
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
5
ns
CS# Not Active Hold Time
5
ns
CS# High Time (Read/Write)
20
ns
Output Disable Time
6
ns
Output Hold Time
1.2
2
ns
Data In Setup Time
ns
Data In Hold Time
2
ns
Hold# Low Setup Time (Relative To Clock)
Hold# High Setup Time (Relative To Clock)
Hold# High Hold Time (Relative To Clock)
Hold# Low Hold Time (Relative To Clock)
Hold# Low To High-Z Output
5
ns
5
ns
5
ns
5
ns
6
6
7
6
ns
Hold# Low To Low-Z Output
ns
Clock Low To Output Valid (CL = 30pF)
Clock Low To Output Valid (CL = 15pF)
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
CS# High To Next Command After Reset (Except From Erase)
CS# High To Next Command After Reset (From Erase)
CS# High To Standby Mode Without Electronic Signature Read
CS# High To Standby Mode With Electronic Signature Read
CS# High To Next Command After Suspend
Latency Between Resume And Next Suspend
Write Status Register Cycle Time
Page Programming Time
ns
tCLQV
ns
tWHSL
tSHWL
tDP
20
ns
100
ns
20
30
12
20
20
20
μs
μs
ms
μs
μs
μs
μs
ms
ms
ms
s
tRST
tRST_E
tRES1
tRES2
tSUS
tRS
100
tW
5
0.5
70
30
2.4
400
1.2
2.4
120
tPP
tSE
Sector Erase Time
tBE1
tBE2
tCE
Block Erase Time (32K Bytes)
0.16
0.3
50
Block Erase Time (64K Bytes)
s
Chip Erase Time (GD25LQ128D)
s
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
68
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
(T= -40℃~125℃, VCC=1.65~2.0V, CL=30pf)
Symbol
fC
Parameter
Serial Clock Frequency For: all command except for 03H
Serial Clock Frequency For: Read (03H)
Serial Clock High Time
Min.
Typ.
Max.
104
80
Unit.
MHz
MHz
ns
fR
tCLH
4.0
4.0
0.2
0.2
5
tCLL
Serial Clock Low Time
ns
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
V/ns
V/ns
ns
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
5
ns
CS# Not Active Hold Time
5
ns
CS# High Time (Read/Write)
20
ns
Output Disable Time
6
ns
Output Hold Time
1.2
2
ns
Data In Setup Time
ns
Data In Hold Time
2
ns
Hold# Low Setup Time (Relative To Clock)
Hold# High Setup Time (Relative To Clock)
Hold# High Hold Time (Relative To Clock)
Hold# Low Hold Time (Relative To Clock)
Hold# Low To High-Z Output
5
ns
5
ns
5
ns
5
ns
6
6
7
6
ns
Hold# Low To Low-Z Output
ns
Clock Low To Output Valid (CL = 30pF)
Clock Low To Output Valid (CL = 15pF)
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
CS# High To Next Command After Reset (Except From Erase)
CS# High To Next Command After Reset (From Erase)
CS# High To Standby Mode Without Electronic Signature Read
CS# High To Standby Mode With Electronic Signature Read
CS# High To Next Command After Suspend
Latency Between Resume And Next Suspend
Write Status Register Cycle Time
Page Programming Time
ns
tCLQV
ns
tWHSL
tSHWL
tDP
20
ns
100
ns
20
30
12
20
20
20
μs
μs
ms
μs
μs
μs
μs
ms
ms
ms
s
tRST
tRST_E
tRES1
tRES2
tSUS
tRS
100
tW
5
0.5
70
30
4
tPP
tSE
Sector Erase Time
500
1.5
3.0
150
tBE1
tBE2
tCE
Block Erase Time (32K Bytes)
0.16
0.3
50
Block Erase Time (64K Bytes)
s
Chip Erase Time (GD25LQ128D)
s
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
69
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
Figure44. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tCLCH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
SI
MSB
High-Z
LSB
SO
Figure45. Output Timing
CS#
tCLH
tSHQZ
SCLK
tCLQV
tCLQV
tCLQX
tCLL
tCLQX
SO
SI
LSB
Least significant address bit (LIB) in
Figure46. Resume to Suspend Timing Diagram
tRS
Resume
Command
Suspend
Command
CS#
Figure47. Hold Timing
CS#
tCHHL
tHLCH
tCHHH
tHHCH
tHHQX
SCLK
tHLQZ
SO
HOLD#
SI do not care during HOLD operation.
70
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
9. ORDERING INFORMATION
GD XX XX XX X X X X X
Packing
T or no mark: Tube
Y: Tray
R: Tape and Reel
Green Code
G: Pb Free + Halogen Free Green Package
S: Pb Free + Halogen Free Green Package + SRP1
Function
Temperature Range
I: Industrial (-40℃ to +85℃)
J: Industrial (-40℃ to +105℃)
E: Industrial (-40℃ to +125℃)
F: Industrial+ (-40℃ to +85℃)
3: Automotive (-40℃ to +85℃)*
2: Automotive (-40℃ to +105℃)*
A: Automotive (-40℃ to +125℃)*
Package Type
S: SOP8 208mil
V: VSOP8 208mil
W: WSON8 (6x5mm)
Y: WSON8 (8x6mm)
Generation
D: D Version
Density
128: 128M bit
Series
LQ: 1.8V, 4KB Uniform Sector
Product Family
25: SPI Interface Flash
* Please contact GigaDevice sales for automotive products.
71
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
9.1. Valid Part Numbers
Please contact GigaDevice regional sales for the latest product selection and available form factors.
Temperature Range I: Industrial (-40℃ to +85℃)
Product Number
Density
128Mbit
128Mbit
128Mbit
128Mbit
Package Type
SOP8 208mil
GD25LQ128DSIG
GD25LQ128DSIS
GD25LQ128DVIG
GD25LQ128DVIS
GD25LQ128DWIG
GD25LQ128DWIS
GD25LQ128DYIG
GD25LQ128DYIS
VSOP8 208mil
WSON8 (6x5mm)
WSON8 (8x6mm)
Temperature Range J: Industrial (-40℃ to +105℃)
Product Number
Density
128Mbit
128Mbit
128Mbit
128Mbit
Package Type
SOP8 208mil
GD25LQ128DSJG
GD25LQ128DSJS
GD25LQ128DVJG
GD25LQ128DVJS
GD25LQ128DWJG
GD25LQ128DWJS
GD25LQ128DYJG
GD25LQ128DYJS
VSOP8 208mil
WSON8 (6x5mm)
WSON8 (8x6mm)
Temperature Range E: Industrial (-40℃ to +125℃)
Product Number
Density
128Mbit
128Mbit
128Mbit
128Mbit
Package Type
SOP8 208mil
GD25LQ128DSEG
GD25LQ128DSES
GD25LQ128DVEG
GD25LQ128DVES
GD25LQ128DWEG
GD25LQ128DWES
GD25LQ128DYEG
GD25LQ128DYES
VSOP8 208mil
WSON8 (6x5mm)
WSON8 (8x6mm)
72
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
Temperature Range F: Industrial+ (-40℃ to +85℃)
Product Number
Density
128Mbit
128Mbit
128Mbit
128Mbit
Package Type
GD25LQ128DSFG
GD25LQ128DSFS
GD25LQ128DVFG
GD25LQ128DVFS
GD25LQ128DWFG
GD25LQ128DWFS
GD25LQ128DYFG
GD25LQ128DYFS
SOP8 208mil
VSOP8 208mil
WSON8 (6x5mm)
WSON8 (8x6mm)
73
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
10. PACKAGE INFORMATION
10.1. Package SOP8 208MIL
D
E
E1
L1
L
θ
“A”
b
Base Metal
A
A2
c
Detail “A”
A1
b
e
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
Min
-
-
0.05
0.15
0.25
1.70
1.80
1.90
0.31
0.41
0.51
0.15
0.20
0.25
5.13
5.23
5.33
7.70
7.90
8.10
5.18
5.28
5.38
0.50
-
0°
-
mm Nom
Max
1.27
1.31
2.16
0.85
8°
Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.
74
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
10.2. Package VSOP8 208MIL
D
E
E1
L1
L
θ
“A”
b
Base Metal
A2
A1
A
c
b
e
Detail “A”
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
Min
-
-
0.05
0.10
0.15
0.75
0.80
0.85
0.35
0.42
0.50
0.09
0.15
0.20
5.18
5.28
5.38
7.70
7.90
8.10
5.18
5.28
5.38
0.50
-
0°
-
mm Nom
Max
1.27
1.31
1.00
0.80
10°
Note:
1. Both the package length and width include the mold flash.
2. Seating plane: Max. 0.1mm.
75
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
10.3. Package WSON8 (6*5mm)
c
D
E
A1
A
Top View
Side View
L
b
e
E2
D2
Bottom View
Dimensions
Symbol
A
A1
c
b
D
D2
E
E2
e
L
Unit
Min
0.70
0.75
0.80
0.00
0.02
0.05
0.180
0.203
0.250
0.35
0.40
0.50
5.90
6.00
6.10
3.30
3.40
3.50
4.90
5.00
5.10
3.90
4.00
4.10
0.50
0.60
0.75
mm
Nom
Max
1.27
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package lead frames. These lead
shapes are compatible with each other.
76
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
10.4. Package WSON8 (8*6mm)
c
D
E
A1
A
Top View
Side View
L
b
e
E2
D2
Bottom View
Dimensions
Symbol
Unit
A
A1
c
b
D
D2
E
E2
e
L
Min
0.70
0.75
0.80
0.00
0.02
0.05
0.180
0.203
0.250
0.35
0.40
0.45
7.90
8.00
8.10
3.30
3.40
3.50
5.90
6.00
6.10
4.20
4.30
4.40
0.45
0.50
0.55
mm Nom
Max
1.27
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package lead frames. These lead
shapes are compatible with each other.
77
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
11. REVISION HISTORY
Version No
Description
Page
All
Date
1.0
Initial Released
2017-3-10
Modified Input Pause Voltage from “0.2VCC to 0.8VCC” to
“0.1VCC to 0.8VCC”
P58
Modified Input Timing Reference Voltage from “0.3VCC to
0.7VCC” to “0.2VCC to 0.7VCC”
P58
1.1
2017-11-29
Deleted tRST_R and tRST_P
P60
P60
Added tRST, of which the max. value is 30us
Added Icc8, of which the max value is 20mA
Modified the description of the WSON8 packages
Modify VWI max value from 1.4V to 1.5V
Modify Icc2 max value from 5uA to 8uA
P59
P66-67
P57
P59
1.2
1.3
2017-12-25
2018-1-2
Add “F: Industrial+” to the 7th code of the ordering information
Update the description of the SOP8 and VSOP8 packages
Add “J”, “E”, “3”, “2” and “A” to the 7th code of the ordering
information
P62, 63
P64, 65
P62, 63
Modify tVSL min value from 5ms to 2.5ms
Add tRS, of which the min value is 100us
Modify tPP typ. value from 0.7ms to 0.5ms
Modify tSE from 90-500ms to 70-400ms
Modify tBE1 typ. value from 0.3s to 0.16s
Modify tBE2 typ. value from 0.5s to 0.3s
Modify tCE from 100-200s to 50-120s
P60
P63
P63
P63
P63
P63
P64
P48
P50
1.4
2018-6-12
Add 4BH command
1.5
Modify the sequence diagram of 42H command
Add AC/DC parameters @-40~105℃ and @-40~125℃
Modify the dummy configuration table of C0H command
Add tCLQV (CL = 15pF), of which the max value is 6ns
2018-7-23
P64, 64, 67, 68
P52
1.6
1.7
2018-8-7
P66, 68, 69
2018-10-29
78
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128D
Important Notice
This document is the property of GigaDevice Semiconductor (Beijing) Inc. and its subsidiaries (the "Company"). This
document, including any product of the Company described in this document (the “Product”), is owned by the Company
under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The
Company reserves all rights under such laws and treaties and does not grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. The names and brands of third party referred thereto (if any) are the property
of their respective owner and referred to for identification purposes only.
The Company makes no warranty of any kind, express or implied, with regard to this document or any Product,
including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company
does not assume any liability arising out of the application or use of any Product described in this document. Any information
provided in this document is provided only for reference purposes. It is the responsibility of the user of this document to
properly design, program, and test the functionality and safety of any application made of this information and any resulting
product. Except for customized products which has been expressly identified in the applicable agreement, the Products are
designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only.
The Products are not designed, intended, or authorized for use as components in systems designed or intended for the
operation of weapons, weapons systems, nuclear installations, atomic energy control instruments, combustion control
instruments, airplane or spaceship instruments, traffic signal instruments, life-support devices or systems, other medical
devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or Product could cause personal injury, death, property or
environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling the
Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, and
customers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage,
or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold the
Company as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products.
Information in this document is provided solely in connection with the Products. The Company reserves the
right to make changes, corrections, modifications or improvements to this document and the Products and
services described herein at any time, without notice.
79
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