GD5F2GQ4UE9IS [GIGADEVICE]
SPI(x1/x2/x4) NAND Flash;
| 型号： | GD5F2GQ4UE9IS |
| 厂家： | 
GigaDevice |
| 描述： | SPI(x1/x2/x4) NAND Flash |
| 文件： | 总57页 (文件大小：1593K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPI(x1/x2/x4) NAND Flash
2G
GD5F2GQ4xExxS
DATASHEET
1
SPI(x1/x2/x4) NAND Flash
Contents
2G
1
2
FEATURE...........................................................................................................................................................4
GENERAL DESCRIPTION...............................................................................................................................5
2.1 PRODUCT LIST ............................................................................................................................................................... 6
2.2 CONNECTING DIAGRAM .................................................................................................................................................. 6
2.3 PIN DESCRIPTION........................................................................................................................................................... 7
2.4 BLOCK DIAGRAM ........................................................................................................................................................... 7
3
4
ARRAY ORGANIZATION .................................................................................................................................8
3.1 MEMORY MAPPING ....................................................................................................................................................... 9
DEVICE OPERATION.....................................................................................................................................10
4.1 SPI MODES ................................................................................................................................................................ 10
4.2 HOLD MODE ............................................................................................................................................................. 11
4.3 WRITE PROTECTION ..................................................................................................................................................... 11
4.4 POWER OFF TIMING..................................................................................................................................................... 11
5
6
COMMANDS DESCRIPTION.........................................................................................................................12
WRITE OPERATIONS ....................................................................................................................................13
6.1 WRITE ENABLE (WREN) (06H) ..................................................................................................................................... 13
6.2 WRITE DISABLE (WRDI) (04H) ..................................................................................................................................... 13
7
8
FEATURE OPERATIONS...............................................................................................................................14
7.1 GET FEATURES (0FH) AND SET FEATURES (1FH) ............................................................................................................... 14
READ OPERATIONS......................................................................................................................................16
8.1 PAGE READ................................................................................................................................................................. 16
8.2 PAGE READ TO CACHE (13H)......................................................................................................................................... 16
8.3 READ FROM CACHE (03H OR 0BH) ................................................................................................................................ 17
8.4 READ FROM CACHE X2 (3BH)........................................................................................................................................ 17
8.5 READ FROM CACHE X4 (6BH)........................................................................................................................................ 18
8.6 READ FROM CACHE DUAL IO (BBH) ............................................................................................................................... 19
8.7 READ FROM CACHE QUAD IO (EBH)............................................................................................................................... 20
9
READ ID...........................................................................................................................................................21
9.1 READ ID (9FH) ........................................................................................................................................................... 21
9.2 READ UID .................................................................................................................................................................. 23
9.3 READ PARAMETER PAGE ............................................................................................................................................... 25
10
PROGRAM OPERATIONS.........................................................................................................................30
10.1 PAGE PROGRAM ........................................................................................................................................................ 30
10.2 PROGRAM LOAD (PL) (02H) ....................................................................................................................................... 31
2
SPI(x1/x2/x4) NAND Flash
2G
10.3 PROGRAM LOAD X4 (PL X4) (32H)............................................................................................................................... 32
10.4 PROGRAM EXECUTE (PE) (10H)................................................................................................................................... 33
10.5 INTERNAL DATA MOVE ............................................................................................................................................... 34
10.6 PROGRAM LOAD RANDOM DATA (84H) ........................................................................................................................ 34
10.7 PROGRAM LOAD RANDOM DATA X4 (C4H/34H)............................................................................................................ 35
10.8 PROGRAM LOAD RANDOM DATA QUAD IO (72H)........................................................................................................... 36
11
ERASE OPERATIONS ...............................................................................................................................37
11.1 BLOCK ERASE (D8H) .................................................................................................................................................. 37
RESET OPERATIONS................................................................................................................................38
12
12.1 SOFT RESET (FFH) ..................................................................................................................................................... 38
12.2 HARDWARE RESET.................................................................................................................................................... 38
12.2.1 HARDWARE RESET FUNCTION .................................................................................................................................. 38
12.2.2 HARDWARE RESET SETTING..................................................................................................................................... 39
13
ADVANCED FEATURES............................................................................................................................40
13.1 OTP REGION ............................................................................................................................................................ 40
13.2 BLOCK PROTECTION ................................................................................................................................................... 41
13.3 STATUS REGISTER AND DRIVER REGISTER........................................................................................................................ 42
13.4 ASSISTANT BAD BLOCK MANAGEMENT .......................................................................................................................... 43
13.5 INTERNAL ECC .......................................................................................................................................................... 44
14
15
16
17
18
19
20
21
22
POWER ON TIMING...................................................................................................................................45
ABSOLUTE MAXIMUM RATINGS............................................................................................................46
CAPACITANCE MEASUREMENT CONDITIONS....................................................................................47
DC CHARACTERISTIC..............................................................................................................................48
AC CHARACTERISTICS............................................................................................................................49
PERFORMANCE TIMING ..........................................................................................................................50
ORDERING INFORMATION ......................................................................................................................52
PACKAGE INFORMATION ........................................................................................................................53
REVISION HISTORY...................................................................................................................................55
3
SPI(x1/x2/x4) NAND Flash
2G
1 FEATURE
◆
◆
2Gb SLC NAND Flash
◆
Program/Erase/Read Speed
- Page Program time: 400us typical
- Block Erase time: 3ms typical
2048-Byte+128-Byte Physical Page Size(2)
- Internal ECC Off (ECC_EN=0):
- Page read time: 80us maximum(w/I ECC)
2048-Byte+128-Byte Full Access
- Internal ECC On (ECC_EN=1, default):
Program: 2048-Byte+64-Byte
◆
◆
◆
◆
◆
Reliability
- Endurance: 100K program/erase cycles
- Data retention: 10 Years
Read:
2048-Byte+128-Byte
◆
Standard, Dual, Quad SPI
Low Power Consumption
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- Dual SPI: SCLK, CS#, SIO0, SIO1, WP#, HOLD#
- Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3
- 40mA maximum active current
- 110uA(1) maximum standby current
Enhanced access performance
- 2kbyte cache for fast random read
- Cache read and cache program
◆
◆
High Speed Clock Frequency
- 120MHz for fast read with 30PF load
- Quad I/O Data transfer up to 480Mbits/s
Advanced Feature for NAND
- Internal ECC option, per 528bytes
- Internal data move by page with ECC
Software/Hardware Write Protection
- Write protect all/portion of memory via software
- Register protection with WP# Pin
- Top or Bottom, Block selection combination
The first block(Block0) is guaranteed to be a valid block
at the time of shipment.
◆
◆
Advanced security Features
- 8K-Byte OTP Region
Single Power Supply Voltage
- Full voltage range for 1.8V: 1.7V ~ 2.0V
- Full voltage range for 3.3V: 2.7V ~ 3.6V
Note (1): When Temperature is 105℃, the maximum standby current is 200uA
(2). 2048Byte+128Byte Page Size can accommodate more advanced ECC algorithm by user’s choice, even though
the internal 4-bit ECC algorithm only requires 64-Byte spare area.
Internal 4-bit ECC is set to on (ECC_EN=1) as shipment default, it can be disabled by setting ECC_EN=0.
- When Internal ECC is enabled, user can only program the first 64-Byte portion of the entire 128-Byte spare
area, and the rest 64-Byte spare area cannot be programed. User can still read the entire 128-Byte spare area.
- When Internal ECC is disabled, user can read and program the entire 128-Byte spare area.
4
SPI(x1/x2/x4) NAND Flash
2 GENERAL DESCRIPTION
2G
SPI (Serial Peripheral Interface) NAND Flash provides an ultra cost-effective while high density non-volatile memory
storage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an attractive
alternative to SPI-NOR and standard parallel NAND Flash, with advanced features:
• Total pin count is 8, including VCC and GND
• Density is 2G bit
• Superior write performance and cost per bit over SPI-NOR
• Significant low cost than parallel NAND
This low-pin-count NAND Flash memory follows the industry-standard serial peripheral interface, and always remains the
same pin-out from one density to another. The command sets resemble common SPI-NOR command sets, modified to
handle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flash
memory, with specified designed features to ease host management:
• User-selectable internal ECC. ECC code is generated internally during a page program operation. When a page
is read to the cache register, the ECC code is detect and correct the errors when necessary. The 64-bytes spare
area is available even when internal ECC enabled. The device outputs corrected data and returns an ECC error
status.
• Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage
collection task, without need of shift in and out of data.
• Power on Read with internal ECC. It is programmed and read in page-based operations, and erased in
block-based operations. Data is transferred to or from the NAND Flash memory array, page by page, to a data
register and a cache register. The cache register is closest to I/O control circuits and acts as a data buffer for the I/O
data; the data register is closest to the memory array and acts as a data buffer for the NAND Flash memory array
operation. The cache register functions as the buffer memory to enable page and random data READ/WRITE and
copy back operations. These devices also use a SPI status register that reports the status of device operation.
5
SPI(x1/x2/x4) NAND Flash
2G
2.1 Product List
Page Size
Product Number
GD5F2GQ4REZIS
GD5F2GQ4REZJS
GD5F2GQ4REZFS
GD5F2GQ4RE9IS
GD5F2GQ4RE9JS
GD5F2GQ4RE9FS
GD5F2GQ4UEZIS
GD5F2GQ4UEZJS
GD5F2GQ4UEZFS
GD5F2GQ4UE9IS
GD5F2GQ4UE9JS
GD5F2GQ4UE9FS
Density
Voltage
Package Type
Temperature
-40℃ to 85℃
-40℃ to 105℃
-40℃ to 85℃
-40℃ to 85℃
-40℃ to 105℃
-40℃ to 85℃
-40℃ to 85℃
-40℃ to 105℃
-40℃ to 85℃
-40℃ to 85℃
-40℃ to 105℃
-40℃ to 85℃
TFBGA24(6*4 Ball Array)
1.7V to 2.0V
LGA8(6*8mm)
TFBGA24(6*4 Ball Array)
LGA8(6*8mm)
2Kbytes + 128bytes
2Gbit
2.7V to 3.6V
2.2 Connecting Diagram
Top View
4
HOLD#
SI
WP#
NC
RESET# VCC
NC
NC
CS# 1
8
7
VCC
3
VSS
NC
NC
NC
NC
NC
NC
SO
2
HOLD#/RESET#
2
1
Top View
SCLK CS# SO
WP# 3
VSS 4
6 SCLK
SI
NC
A
NC
B
NC
NC
NC
E
NC
F
5
C
D
8–LEAD WSON
24-BALL TFBGA
Figure 2-1 Connect Diagram
6
SPI(x1/x2/x4) NAND Flash
2.3 Pin Description
2G
Pin Name
CS#
I/O
Description
I
Chip Select input, active low
SO/SIO1
WP#/SIO2
VSS
I/O
Serial Data Output / Serial Data Input Output 1
Write Protect, active low / Serial Data Input Output 2
Ground
I/O
Ground
SI/SIO0
SCLK
I/O
I
Serial Data Input / Serial Data Input Output 0
Serial Clock input
HOLD#/RESET#/SIO3 I/O
Hold input, active low / Reset input, active low / Serial Data Input Output3
Power Supply
VCC
Supply
2.4 Block Diagram
HOLD#/ WP#/
SCLK SI/SIO0 SO/SIO1
CS#
SIO3
SIO2
Serial NAND controler
Vcc
Vss
NAND
memory
core
Cache
memory
ECC and status register
Figure 2-2 Block Diagram
7
SPI(x1/x2/x4) NAND Flash
3 ARRAY ORGANIZATION
2G
Each device has
2G
Each block has
Each page has
256M+16M
2048 x 64
2048
128K+8K
2K+128
bytes
pages
blocks
64
-
-
-
Figure3-1. Array Organization
SO
SI
Cache Register
2048
2048
128
128
Data Register
1 page = (2K + 128 bytes)
1 block = (2K + 128 bytes) x 64 pages
= (128K + 8K) bytes
Per device:
2Gb: 2048blocks
1 device:
For 2Gb = (128K + 8K) bytes x 2048 blocks
= 1Gb
1 block
Internal ECC = OFF
SO
SI
Cache Register
Data Register
2048
2048
64
64
1 page = (2K + 64 bytes)
1 block = (2K + 64 bytes) x 64 pages
= (128K + 4K) bytes
Per device:
2Gb: 2048blocks
1 device:
For 2Gb = (128K + 4K) bytes x 2048 blocks
= 2Gb
1 block
Internal ECC= ON
Note:
1.When Internal ECC is enabled，user can program the first 64 bytes of the entire 128 bytes spare area and the
last 64 bytes of the whole spare area cannot be programed，user can read the entire 128 Byte spare area.
2.When Internal ECC is disabled，user can read and program the entire 128 bytes spare area.
8
SPI(x1/x2/x4) NAND Flash
3.1 Memory Mapping
2G
For 2G:
Blocks
RA<16:6>
0
0
0
1
1
1
2
2047
Pages
RA<5:0>
63
Bytes
CA<11:0>
2
2175
Note:
1. CA: Column Address. The 12-bit address is capable of addressing from 0 to 4095 bytes; however, only bytes 0
through 2175 are valid. Bytes 2176 through 4095 of each page are “out of bounds,” do not exist in the device,
and cannot be addressed.
2. RA: Row Address. RA<5:0> selects a page inside a block, and RA<16:6> selects a block.
9
SPI(x1/x2/x4) NAND Flash
4 DEVICE OPERATION
2G
4.1 SPI Modes
SPI NAND supports two SPI modes:
• CPOL = 0, CPHA = 0 (Mode 0)
• CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK for both modes. All timing
diagrams shown in this data sheet are mode 0. See Figure4-1 for more details.
Figure4-1. SPI Modes Sequence Diagram
CPOL CPHA
0
0
SCLK
1
1
SCLK
SI
MSB
LSB
SO
CS#
MSB
LSB
Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3).
Standard SPI
SPI NAND Flash features a standard serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select
(CS#), Serial Data Input (SI) and Serial Data Output (SO).
Dual SPI
SPI NAND Flash supports Dual SPI operation when using the x2 and dual IO commands. These commands allow
data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command
the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1.
Quad SPI
SPI NAND Flash supports Quad SPI operation when using the x4 and Quad IO commands. These commands allow
data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI
command the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1, and WP# and HOLD#/RESET# pins
become SIO2 and SIO3.
10
SPI(x1/x2/x4) NAND Flash
2G
4.2 HOLD Mode
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low
(if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high
and then CS# must be at low.
Figure4-2. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
4.3 Write Protection
SPI NAND provides Hardware Protection Mode besides the Software Mode. Write Protect (WP#) prevents the block lock
bits (BP0, BP1, BP2 and INV, CMP) from being overwritten. If the BRWD bit is set to 1 and WP# is LOW, the block
protect bits cannot be altered.
4.4 Power Off Timing
Please do not turn off the power before Write/Erase operation is complete. Avoid using the device when the battery is low.
Power shortage and/or power failure before Write/Erase operation is complete will cause loss of data and/or
damage to data.
11
SPI(x1/x2/x4) NAND Flash
5 COMMANDS DESCRIPTION
2G
Table5-1. Commands Set
Command Name
Write Enable
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte N
06H
Write Disable
04H
Read UID
EDH
13H
00H
Read parameter page
Get Features
A23-A16
A7-A0
A15-A8
(D7-D0)
(D7-D0)
A15-A8
A7-A0
A7-A0
0FH
Wrap
Set Feature
1FH
A7-A0
dummy(1)
A7-A0
dummy(2)
dummy(2)
dummy(2)
(D7-D0)x2
Page Read (to cache)
Read From Cache
Read From Cache x 2
Read From Cache x 4
Read From Cache Dual IO
Read From Cache Quad IO
Read ID(8)
13H
A23-A16
A15-A8(4)
A15-A8(4)
A15-A8(4)
A15-A0(4)
A15-A0(5)
A7-A0
03H/0BH
3BH
(D7-D0)
A7-A0
(D7-D0)x2
(D7-D0)x4
6BH
A7-A0
BBH
dummy(3)
(D7-D0)x4
MID
EBH
9FH
DID
Wrap
Program Load
02H
A15-A8(6)
A15-A8(6)
A23-A16
A15-A8(6)
A15-A8(6)
A15-A0(7)
A7-A0
(D7-D0)
Next byte
Byte N
Byte N
Program Load x4
Program Execute
Program Load Random Data
Program Load Random Data x4
32H
A7-A0
(D7-D0)x4 Next byte
A7-A0
10H
A15-A8
A7-A0
84H(10)
C4H/34H(10)
(D7-D0)
Next byte
Byte N
Byte N
Byte N
A7-A0
(D7-D0)x4 Next byte
Program Load Random Data Quad 72H
IO
(D7-D0)x4 Next byte
Block Erase(128K)
Reset(9)
D8H
FFH
A23-A16
A15-A8 A7-A0
Notes:
1. The dummy byte can be inputted or not.
2. The x8 clock = dummy<7:0>.
3. The x8 clock = dummy<7:0>, D7-D0.
4. The x8 clock = dummy<3-0>, A11-A8 or dummy<3-0>, A11-A0.
5. The x8 clock = dummy<3-0>, A11-A0, dummy<7:0>, D7-D0.
6. The x8 clock = dummy<3:0>, A<11:8>.
7. The x8 clock = dummy<3:0>, A<11:0>, D7-D0, D7-D0.
8. MID is Manufacture ID (C8h for GigaDevice), DID is Device ID
When A7-A0 is 00h, read MID and DID.
9. Reset command:
• During busy, Reset will reset PAGE READ/PROGRAM/ERASE operation.
• During idle, Reset will reset status register bits P_FAIL/E_FAIL/ECCS bits.
10. Those commands are only available in Internal Data Move operation.
11. Read UID/parameter page all are same as page read to cache.
12
SPI(x1/x2/x4) NAND Flash
6 WRITE OPERATIONS
2G
6.1 Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit
must be set prior to following operations that change the contents of the memory array:
• Page program
• OTP program/OTP protection
• Block erase
The WEL bit can be cleared after a reset command.
Figure6-1. Write Enable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
06H
High-Z
SO
6.2 Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The WEL bit is also reset by following
condition:
• Page program
• OTP program/OTP protection
• Block erase
Figure6-2. Write Disable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
04H
High-Z
SO
13
SPI(x1/x2/x4) NAND Flash
7 FEATURE OPERATIONS
2G
7.1 Get Features (0FH) and Set Features (1FH)
The GET FEATURES (0FH) and SET FEATURES (1FH) commands are used to monitor the device status and alter the
device behavior. These commands use a 1-byte feature address to determine which feature is to be read or modified.
Features such as OTP and block locking can be enabled or disabled by setting specific feature bits (shown in the
following table). The status register is mostly read, except WEL, which is a writable bit with the WRITE ENABLE (06H)
command.
When a feature is set, it remains active until the device is power cycled or the feature is written to. Unless otherwise
specified in the following table, once the device is set, it remains set, even if a RESET (FFH) command is issued.
Table7-1. Features Settings
Register
Addr.
7
6
5
4
3
2
1
0
Protection A0H
BRWD
OTP_PRT
Reserved
Reserved BP2
BP1
BP0
INV
CMP
Reserved
Feature
Status
B0H
C0H
D0H
F0H
OTP_EN Reserved ECC_EN Reserved Reserved Reserved QE
Reserved ECCS1 ECCS0 P_FAIL E_FAIL WEL OIP
DS_S0 Reserved Reserved Reserved Reserved Reserved
Reserved ECCSE1 ECCSE0 Reserved Reserved Reserved Reserved
Feature
Status
HOLDB/RST DS_S1
Reserved
Note: If BRWD is enabled and WP# is LOW, then the block lock register cannot be changed.
If QE is enabled, the quad IO operations can be executed.
All the reserved bits must be held low when the feature is set.
00h is the default data byte value for Output Driver Register after power-up.
HOLDB/RST is for WSON8 Package only. By default HOLDB/RST registers is 0 after power-on-reset or hardware
reset, and this bit default is HOLD function.
Figure7-1. Get Features Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
1 byte address
SCLK
SI
Command
0FH
7
6
5
4
3
2
1
0
Data byte
MSB
SO
High-Z
7
6
5
4
3
2
1
0
MSB
Note: The output would be updated by real-time, until CS# is driven high.
14
SPI(x1/x2/x4) NAND Flash
2G
The set features command supports a dummy byte mode after the data byte as well. The features in the feature byte B0H
are all volatile except OTP_PRT bit.
Figure7-2. Set Features Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
SI
Data byte
Command
1FH
1 byte address
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
SO
High-Z
15
SPI(x1/x2/x4) NAND Flash
8 READ OPERATIONS
2G
8.1 Page Read
The PAGE READ (13H) command transfers the data from the NAND Flash array to the cache register. The command
sequence is as follows:
• 13H (PAGE READ to cache)
• 0FH (GET FEATURES command to read the status)
• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH (Read from cache
dual IO)/EBH (Read from cache quad IO)
The PAGE READ command requires a 24-bit address. After the block/page addresses are registered, the device starts
the transfer from the main array to the cache register, and is busy for tRD time. During this time, the GET FEATURE (0FH)
command can be issued to monitor the status. Followed the page read operation, the RANDOM DATA READ
(03H/0BH/3BH/6BH/BBH/EBH) command must be issued in order to read out the data from cache. The output data starts
at the initial address specified in the command, once it reaches the ending boundary of the 2176-byte section, the output
will wrap around the beginning boundary automatically until CS# is pulled high to terminate this operation. Refer
waveforms to view the entire READ operation.
8.2 Page Read to Cache (13H)
Figure8-1. Page Read to cache Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
13H
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
1 byte address
SLK
SI
tCS
Get Feature
0FH
7
6
5
4
3
2
1
0
MSB
High-Z
SO
CS#
16 17 18 19 20 21 22 23 24
SCLK
SI
Data byte
SO
7
6
5
4
3
2
1
0
7
MSB
16
SPI(x1/x2/x4) NAND Flash
8.3 Read From Cache (03H or 0BH)
2G
Figure8-2. Read From Cache Sequence Diagram
CS#
10 11 12 13 14
0 1 2 3 4 5 6 7 8 9
22 23
SCLK
Command
A11-0
dummy<3:0>
0 12 11 10
SI
03H or 0BH
0
0
3
2
1
0
High-Z
SO
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
Dummy Byte
7 6 5 4 3 2 1 0
Data Out1
Data Out2
SO
7 6 5 4 3 2 1 0 7 6 5
MSB MSB
8.4 Read From Cache x2 (3BH)
Figure8-3. Read From Cache x2 Sequence Diagram
CS#
10 11 12 13 14
0 1 2 3 4 5 6 7 8 9
22 23
SCLK
Command
A11-0
dummy<3:0>
0 0 0 12 11 10
SI/SIO0
3BH
3 2 1 0
High-Z
SO/SIO1
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Dummy Byte
SCLK
7 6 5 4 3 2 1 0
SI/SIO0
6 4 2 0 6 4 2 0 6 4 2
Data Out1 Data Out2
7 5 3 1 7 5 3 1 7 5 3
MSB MSB
SO/SIO1
17
SPI(x1/x2/x4) NAND Flash
8.5 Read From Cache x4 (6BH)
2G
The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache x4 command.
Figure8-4. Read From Cache x4 Sequence Diagram
CS#
10 11 12 13 14
0 1 2 3 4 5 6 7 8 9
22 23
SCLK
Command
6BH
dummy<3:0>
0 0 0 12 11 10
A11-0
3 2 1 0
SI(SIO0)
SO(SIO1)
High-Z
High-Z
High-Z
WP#(SIO2)
HOLD#(SIO3)
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Dummy Byte
SCLK
7 6 5 4 3 2 1 0
4 0 4 0 4 0 4 0
5 1 5 1 5 1 5 1
6 2 6 2 6 2 6 2
4
5
6
7
SI(SIO0)
SO(SIO1)
WP#(SIO2)
HOLD#(SIO3)
7 3 7 3 7 3 7 3
Byte1 Byte2 Byte3 Byte4
18
SPI(x1/x2/x4) NAND Flash
8.6 Read From Cache Dual IO (BBH)
2G
The Read from Cache Dual I/O command (BBH) is similar to the Read form Cache x2 command (3BH) but with the
capability to input the 4 Dummy bits, followed by a 12-bit column address for the starting byte address and a dummy byte
by SIO0 and SIO1, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 2-bit
per clock cycle from SIO0 and SIO1. The first address byte can be at any location. The address increments automatically
to the next higher address after each byte of data shifted out until the boundary wrap bit.
Figure8-5. Read From Cache Dual IO Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
BBH
SI(SIO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(SIO1)
7
A7-0
Dummy
Byte1
dummy<3:0>, A11-8
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(SIO0)
SO(SIO1)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
Byte2
Byte3
Byte4
Byte5
19
SPI(x1/x2/x4) NAND Flash
8.7 Read From Cache Quad IO (EBH)
2G
The Read from Cache Quad IO command is similar to the Read from Cache x4 command but with the capability to input
the 4 dummy bits, followed a 12-bit column address for the starting byte address and a dummy byte by SIO0, SIO1, SIO3,
SIO4, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 4-bit per clock
cycle from SIO0, SIO1, SIO2, SIO3. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out until the boundary wrap bit. The Quad
Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache quad IO command.
Figure8-6. Read From Cache Quad IO Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
EBH
SI(SIO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(SIO1)
5
6
7
WP#(SIO2)
HOLD#(SIO3)
Byte1 Byte2
Dummy
dummy<3:0>, A11-A8 A7-0
20
SPI(x1/x2/x4) NAND Flash
2G
9 Read ID
9.1 Read ID (9FH)
The READ ID command is used to identify the NAND Flash device.
• With address 00H~01H, the READ ID command outputs the Manufacturer ID and the device ID. See Table9-1for
details.
Figure9-1_1. Read ID Sequence Diagram(Address 00h)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Address 00h
SCLK
Command
9FH
SI
7
6 5 4 3 2 1 0
High-Z
SO
CS#
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
16
SCLK
SI
Device ID
Manufacturer ID
SO
7
MSB
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
Figure9-1_2. Read ID Sequence Diagram(Address 01h)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
Command
9FH
Address 00h
SI
7 6 5 4 3 2 1 0
High-Z
SO
CS#
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
16
SCLK
SI
Device ID
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
Manufacturer ID
SO
21
SPI(x1/x2/x4) NAND Flash
2G
Table9-1. READ ID Table
Part No
Value
Page Size
Description
GD5F2GQ4UExxS
GD5F2GQ4RExxS
GD5F2GQ4UExxS
GD5F2GQ4RExxS
C8h
Manufacture ID (GigaDevice)
2Kbyte + 128Byte
D5h
C5h
Device ID (SPI NAND 2Gbit 3.3V)
Device ID (SPI NAND 2Gbit 1.8V)
22
SPI(x1/x2/x4) NAND Flash
2G
9.2 Read UID
The Read Unique ID function is used to retrieve the 16 byte unique ID (UID) for the device. The unique ID when
combined with the device manufacturer shall be unique.
The UID data may be stored within the Flash array. To allow the host to determine if the UID is without bit errors, the UID
is returned with its complement. If the XOR of the UID and its bit-wise complement is all ones, then the UID is valid. To
accommodate robust retrieval of the UID in the case of bit errors, sixteen copies of the UID and the corresponding
complement shall be stored by the target. For example, reading bytes 32-63 returns to the host another copy of the UID
and its complement.
Bytes
0-15
Value
UID
16-31
UID complement (bit-wise)
The Read UID command sequence is as follows:
1. Use EDh+00h read UID from array to cache.
2. Use 0FH (GET FEATURES command ) read the status
3. User can use Read from cache command (03H/0BH/3BH/6BH/BBH/EBH), read UID from cache.
Read UID to Cache (EDH+00H) + Get Feature (0FH)
23
SPI(x1/x2/x4) NAND Flash
2G
Figure9-2. Read UID to cache and Get Feature command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
11 12 13 14 15
SCLK
SI
Command
EDH
Command
00H
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
1 byte address
SLK
SI
tCS
Get Feature
0FH
7
6
5
4
3
2
1
0
MSB
High-Z
SO
CS#
16 17 18 19 20 21 22 23 24
SCLK
SI
Data byte
SO
7
6
5
4
3
2
1
0
7
MSB
24
SPI(x1/x2/x4) NAND Flash
9.3 Read Parameter Page
2G
The Read Parameter Page function retrieves the data structure that describes the chip’s organization, features, timings
and other behavioral parameters. This data structure enables the host processor to automatically recognize the
SPI-NAND Flash configuration of a device. The whole data structure is repeated at least three times. The Read from
cache command can be issued during execution of the read parameter page to read specific portion-soft the parameter
page.
The Read parameter page command sequence is as follows
1) Set “OTP_EN=1”, Use set_feature set data 0x50 to B0 register, to enable OTP_EN.
2) Send 13h command with address 24’h000004. Load parameter page from array to cache.
3) Use 0FH (GET FEATURES command ) read the status
4) User can use Read from cache command (03H/0BH/3BH/6BH/BBH/EBH), read parameter page from cache.
Figure9-4. Read parameter page to cache and Get Feature command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
13H
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
1 byte address
SLK
SI
tCS
Get Feature
0FH
7
6
5
4
3
2
1
0
MSB
High-Z
SO
CS#
16 17 18 19 20 21 22 23 24
SCLK
SI
Data byte
SO
7
6
5
4
3
2
1
0
7
MSB
25
SPI(x1/x2/x4) NAND Flash
2G
Parameter page table as follow
Byte
O/M Description
0-3
M
Parameter page signature
Byte 0: 4FH, “O”
4FH
4EH
46H
49H
Byte 1: 4EH, “N”
Byte 2: 46H, “F”
Byte 3: 49H, “I”
4-5
6-7
M
M
Revision number
0-15 Reserved (0)
Features supported
0-15 Reserved (0)
00H
00H
00H
00H
8-9
M
Reserved (0)
00H
00H
00H
…
10-31
Reserved (0)
00H
Manufacturer Information block
32-43
M
Device manufacturer (12 ASCII characters)“GIGADEVICE
”
47H
49H
47H
41H
44H
45H
56H
49H
43H
45H
20H
20H
47H
44H
35H
46H
32H
47H
51H
34H
44-63
M
Device model (20 ASCII characters)
Device Model
“GD5F2GQ4U”
“GD5F2GQ4R”
ORGANIZATION VCC RANGE
X4
X4
2.7v ~ 3.6v
1.7v ~ 1.95v
55H/52H
20H
20H
20H
20H
20H
26
SPI(x1/x2/x4) NAND Flash
2G
20H
20H
20H
20H
20H
20H
C8H
00H
00H
00H
00H
00H
64
M
O
JEDEC manufacturer ID“C8”
65-66
Date code
67-79
80-83
Reserved
Memory organization block
M
Number of data bytes per page
00H
08H
00H
00H
80H
00H
00H
02H
00H
00H
20H
00H
40H
00H
00H
00H
00H
08H
00H
00H
01H
00H
84-85
86-89
M
M
Number of spare bytes per page
Number of data bytes per partial page
90-91
92-95
M
M
Number of spare bytes per partial page
Number of pages per block
96-99
M
Number of blocks per logical unit (LUN)
100
101
M
M
Number of logical units (LUNs)
Reserved
102
M
M
Number of bits per cell
01H
28H
00H
01H
05H
01H
103-104
Bad blocks maximum per LUN
105-106
107
M
M
Block endurance
Guaranteed valid blocks at beginning of target
27
SPI(x1/x2/x4) NAND Flash
2G
108-109
M
Block endurance for guaranteed valid blocks
01H
05H
04H
00H
110
111
M
M
Number of programs per page
Partial programming attributes
5-7 Reserved
4 1 = partial page layout is partial page data followed by partial page spare
1-3 Reserved
0 1 = partial page programming has constraints
Number of bits ECC correct ability
Number of interleaved address bits
4-7 Reserved (0)
112
113
M
M
08H
00H
0-3 Number of interleaved address bits
Interleaved operation attributes
4-7 Reserved (0)
114
O
00H
3 Address restrictions for program cache
2 1 = program cache supported
1 1 = no block address restrictions
0 Overlapped / concurrent interleaving support
Reserved
115-127
00H
…
00H
Electrical parameters block
I/O capacitance
128
M
M
06H
01H
00H
129-130
IO clock support
3-1 5 Reserved (0)
2 1 = supports 80MHz
1 1 = supports 104MHz
0 1 = supports 120MHz
131-132
O
Reserved (0)
00H
00H
133-134
135-136
137-138
139-140
141-163
M
M
M
M
tPROG Maximum page program time (us)
tBERS Maximum block erase time (us)
tR Maximum page read time (us)
Reserved
BCH
02H
88H
13H
50H
00H
00H
00H
00H
Reserved
Vendor block
164-165
166-253
M
Vendor specific Revision number
Vendor specific
00H
00H
28
SPI(x1/x2/x4) NAND Flash
2G
254-255
M
Integrity CRC
Set on test
Redundant parameter pages
Value of bytes 0-255
256-511
512-767
768+
M
M
O
Value of bytes 0-255
Additional redundant parameter pages
Notes:
1. “O” Stands for Optional, “M” for Mandatory
2. The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the parameters page were
transferred correctly to the host. Please refer to ONFI 1.0 specifications for details.
The CRC shall be calculated using the following 16-bit generator polynomial: G(X) = X16 + X15 +X2 + 1，This
polynomial in hex may be represented as 8005h.
3．The CRC value shall be initialized with a value of 4F4Eh before the calculation begins. There is no XOR applied to the
final CRC value after it is calculated. There is no reversal of the data bytes or the CRC calculated value.
Device Model
ORGANIZATION
VCC RANGE
2.7v ~ 3.6v
CRC value B254/B255
07H/E9H
“GD5F2GQ4UxxxS”
“GD5F2GQ4RxxxS”
X4
X4
1.7v ~ 1.95v
DFH/24H
29
SPI(x1/x2/x4) NAND Flash
10 PROGRAM OPERATIONS
2G
10.1 Page Program
The PAGE PROGRAM operation sequence programs 1 byte to 2176 bytes of data within a page. The page program
sequence is as follows:
• 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4)
• 06H (WRITE ENABLE)
• 10H (PROGRAM EXECUTE)
• 0FH (GET FEATURE command to read the status)
Firstly, a PROGRAM LOAD (02H/32H) command is issued. PROGRAM LOAD consists of an 8-bit Op code, followed by 4
dummy bits and a 12-bit column address, then the data bytes to be programmed. The data bytes are loaded into a cache
register that is 2176 bytes long. If more than 2176 bytes are loaded, then those additional bytes are ignored by the cache
register. The command sequence ends when CS# goes from LOW to HIGH. Figure10-1 shows the PROGRAM LOAD
operation. Secondly, prior to performing the PROGRAM EXECUTE operation, a WRITE ENABLE (06H) command must
be issued. As with any command that changes the memory contents, the WRITE ENABLE must be executed in order to
set the WEL bit. If this command is not issued, then the rest of the program sequence is ignored.
Note:
1. The contents of Cache Register doesn’t reset when Program Load (02h) command, Program Random Load (84h)
command and RESET (FFh) command.
2. When Program Execute (10h) command was issued just after Program Load (02h) command, SPI-NAND controller
outputs 0xFF data to the NAND for the address that data was not loaded by Program Load (02h) command.
3. When Program Execute (10h) command was issued just after Program Load Random Data (84h) command,
SPI-NAND controller outputs contents of Cache Register to the NAND.
4. The addressing should be done in sequential order in a block.
30
SPI(x1/x2/x4) NAND Flash
10.2 Program Load (PL) (02H)
2G
Figure10-1. Program Load Sequence Diagram
CS#
10 11 12 13 14
0 1 2 3 4 5 6 7 8 9
22 23
SCLK
Command
Dummy<3:0>, A11-A0
SI
02H
0 0 0 0 11 10
3 2 1 0
CS#
17424
17431
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Data Byte
2176/2112
7 6 5 4 3 2 1 0
Data Byte1
Data Byte2
SI
7 6 5 4 3 2 1 0
MSB
7 6 5 4 3 2 1 0
Note: when internal ECC disabled the Data Byte is 2176, when internal ECC enabled the Data Byte is 2112.
31
SPI(x1/x2/x4) NAND Flash
10.3 Program Load x4 (PL x4) (32H)
2G
The Program Load x4 command (32H) is similar to the Program Load command (02H) but with the capability to input the
data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown below. The Quad Enable bit (QE)
of feature (B0[0]) must be set to enable the program load x4 command.
Figure10-2. Program Load x4 Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
SCLK
Command
32H
Dummy<3:0>, A11-A0
Byte1 Byte2
SI(SIO0)
15 14 13
3 2 1 0 4 0 4 0 4 0 4 0
SO(SIO1)
5 1 5 1 5 1 5 1
6 2 6 2 6 2 6 2
7 3 7 3 7 3 7 3
WP#(SIO2)
HOLD#(SIO3)
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Byte
2176/2112
Byte11Byte12
SI(SIO0)
4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0
4 0 4 0 4 0 4 0
5 1 5 1 5 1 5 1
6 2 6 2 6 2 6 2
7 3 7 3 7 3 7 3
SO(SIO1)
5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1
6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2
7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
WP#(SIO2)
HOLD#(SIO3)
Note: when internal ECC disabled the Data is 2176, when internal ECC enabled the Data is 2112.
32
SPI(x1/x2/x4) NAND Flash
10.4 Program Execute (PE) (10H)
2G
After the data is loaded, a PROGRAM EXECUTE (10H) command must be issued to initiate the transfer of data from the
cache register to the main array. PROGRAM EXECUTE consists of an 8-bit Op code, followed by a 24-bit address. After
the page/block address is registered, the memory device starts the transfer from the cache register to the main array, and
is busy for tPROG time. This operation is shown in Figure10-3. During this busy time, the status register can be polled to
monitor the status of the operation (refer to Status Register). When the operation completes successfully, the next series
of data can be loaded with the PROGRAM LOAD command.
Figure10-3. Program Execute Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
10H
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
tCS
Status register address
get feature
0FH
7
6
5
4
3
2
1
0
MSB
High-Z
SO
CS#
SCLK
SI
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Status register data out
Status register data out
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
MSB
MSB
33
SPI(x1/x2/x4) NAND Flash
10.5 Internal Data Move
2G
The INTERNAL DATA MOVE command sequence programs or replaces data in a page with existing data. The
INTERNAL DATA MOVE command sequence is as follows:
• 13H (PAGE READ to cache)
• Optional 84H/C4H/34H(PROGRAM LOAD RANDOM DATA)
• 06H (WRITE ENABLE)
• 10H (PROGRAM EXECUTE)
• 0FH (GET FEATURE command to read the status)
Prior to performing an internal data move operation, the target page content must be read out into the cache register by
issuing a PAGE READ (13H) command. The PROGRAM LOAD RANDOM DATA (84H/C4H/72H) command can be
issued, if user wants to update bytes of data in the page. New data is loaded in the 12-bit column address. If the random
data is not sequential, another PROGRAM LOAD RANDOM DATA (84H/C4H/72H) command must be issued with the
new column address. After the data is loaded, the WRITE ENABLE command must be issued, and then a PROGRAM
EXECUTE (10H) command can be issued to start the programming operation.
10.6 Program Load Random Data (84H)
This command consists of an 8-bit Op code, followed by 4 dummy bits, and a 12-bit column address. New data is loaded
in the column address provided with the 12 bits. If the random data is not sequential, then another PROGRAM LOAD
RANDOM DATA (84H) command must be issued with a new column address, seeFigure10-4 for details. This command
is only available during internal data move sequence.
Figure10-4. Program Load Random Data Sequence Diagram
CS#
10 11 12 13 14
0
1
2
3
4
5
6
7
8
9
22 23
SCLK
SI
Dummy<3:0>, A11-A0
Command
84H
0
0
0 0 11 10
3
2
1
0
CS#
17424
17431
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Data Byte
2176/2112
7 6 5 4 3 2 1 0
Data Byte1
Data Byte2
SI
7
6 5 4 3 2 1 0
7
6
5
4
3
2
1
0
MSB
Note: when internal ECC disabled the Data Byte is 2176, when internal ECC enabled the Data Byte is 2112.
34
SPI(x1/x2/x4) NAND Flash
2G
10.7 Program Load Random Data x4 (C4H/34H)
The Program Load Random Data x4 command (C4H/34H) is similar to the Program Load Random Data command (84H)
but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is
shown below. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable for the program load random data x4
command. SeeFigure10-5 for details. Those two commands are only available during internal data move sequence.
Figure10-5. Program Load Random Data x4 Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
SCLK
Command
C4H/34H
Dummy<3:0>, A11-A0
15 14 13
Byte1 Byte2
SI(SIO0)
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(SIO1)
WP#(SIO2)
HOLD#(SIO3)
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Byte11Byte12
SCLK
Byte
2176/2112
SI(SIO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(SIO1)
WP#(SIO2)
HOLD#(SIO3)
Note: when internal ECC disabled the Data is 2176, when internal ECC enabled the Data is 2112.
35
SPI(x1/x2/x4) NAND Flash
2G
10.8 Program Load Random Data Quad IO (72H)
The Program Load Random Data Quad IO command (72H) is similar to the Program Load Random Data x4 command
(C4H) but with the capability to input the 4 dummy bits, and a 12-bit column address by four pins: SIO0, SIO1, SIO2, and
SIO3. The command sequence is shown below. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable for
the program load random data x4 command. See Figure10-6 for details. This command is only available during internal
data move sequence.
Figure10-6. Program Load Random Data Quad IO Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10
11 12 13 14 15 16 17 18 19 20
Byte1 Byte2
SCLK
Dummy<3:0>
A11-A0
Command
72H
SI(SIO0)
4 0 4 0 4 0 4 0 4 0 4 0
SO(SIO1)
5 1 5 1 5 1 5 1 5 1 5 1
WP#(SIO2)
HOLD#(SIO3)
6
2
6
2 6
2 6 2 6 2 6 2
7 3 7 3 7 3 7 3 7 3 7 3
CS#
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SCLK
Byte
2176/2112
Byte11Byte12
SI(SIO0)
4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0
4 0 4 0 4 0 4 0
SO(SIO1)
5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1
6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2
7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
5 1 5 1 5 1 5 1
6 2 6 2 6 2 6 2
7 3 7 3 7 3 7 3
WP#(SIO2)
HOLD#(SIO3)
Note: when internal ECC disabled the Data is 2176, when internal ECC enabled the Data Byte is 2112.
36
SPI(x1/x2/x4) NAND Flash
11 ERASE OPERATIONS
2G
11.1 Block Erase (D8H)
Figure11-1. Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
D8H
24-bit address
23 22 21
SI
3
2
1
0
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SLK
SI
tCS
Status register address
get feature
0FH
7
6
5
4
3
2
1
0
MSB
High-Z
SO
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
SI
Status register data out
Status register data out
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
MSB
MSB
The BLOCK ERASE (D8H) command is used to erase at the block level. The blocks are organized as 64 pages per block,
2176 bytes per page (2048 + 128 bytes). Each block is 136 Kbytes. The BLOCK ERASE command (D8H) operates on
one block at a time. The command sequence for the BLOCK ERASE operation is as follows:
• 06H (WRITE ENBALE command)
• D8H (BLOCK ERASE command)
• 0FH (GET FEATURES command to read the status register)
Prior to performing the BLOCK ERASE operation, a WRITE ENABLE (06H) command must be issued. As with any
command that changes the memory contents, the WRITE ENABLE command must be executed in order to set the WEL
bit. If the WRITE ENABLE command is not issued, then the rest of the erase sequence is ignored. A WRITE ENABLE
command must be followed by a BLOCK ERASE (D8H) command. This command requires a 24-bit address. After the
row address is registered, the control logic automatically controls timing and erase-verify operations. The device is busy
for tERS time during the BLOCK ERASE operation. The GET FEATURES (0FH) command can be used to monitor the
status of the operation.
When
a
block erase operation is in progress, user can issue normal read from cache commands
(03H/0BH/3BH/6BH/BBH/EBH) to read the data in the cache.
37
SPI(x1/x2/x4) NAND Flash
12 RESET OPERATIONS
2G
12.1 Soft Reset (FFH)
Figure12-1. Reset Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
FFH
High-Z
SO
The RESET (FFH) command stops all operations. For example, in case of a program or erase or read operation, the
reset command can make the device enter the wait state.
During a cache program or cache read, a reset can also stops the previous operation and the pending operation. The
OIP status can be read from 300ns after the reset command is sent.
12.2 Hardware RESET
12.2.1 Hardware RESET Function
The RESET# pin allows the device to be reset by the host controller or system reset timer like watchdog for re-boot
without a power off and on sequence.
For the 8-pin package, pin7 can be configured as a RESET# pin depending on the status register setting, QE=0
and HOLD/RST=1(see Section Hardware RESET Setting). On the 24-pin package, a dedicated RESET# pin is provided
and it is independent of QE bit setting (see Section Hardware RESET Setting).
The RESET# pin goes low for a period of tRLRH or longer will reset the flash memory. After a reset cycle, the flash
is at the following states:
-In standby mode
-All the volatile bits return to the default value as after power-on-reset.
-Data of page0/block0 is read out to the cache, user can issue read from cache command (03/0B/3B/6B/BB/EB) for
data.
Please note that No command is accepted during the reset cycle (tRB1 or tRB2).
Figure12-2. Hardware RESET Timing
38
SPI(x1/x2/x4) NAND Flash
2G
Table12-1. Hardware RESET Timing
Symbol
tRLRH
tRHSL
tRB1
Parameter
Setup
MIN
Speed
500
50
Unit.
Reset pulse width
us
ns
Reset high time before read
MIN
Reset recovery time (For NOT busy mode)
Reset recovery time (For busy mode)
MAX
MAX
500
1
us
tRB2
ms
12.2.2 Hardware RESET Setting
a) 8-pin package
For the 8-pin package, RESET#, HOLD# and data IO3 share the same pin7. The pin7 can be configured as any of
the three functions depending on the status register setting. When QE=0, HOLDB/RST=1, the pin7 acts as a RESET# pin.
When QE=1 or QE=0 HOLDB/RST=0, the pin7 will be configured as the other functions and Hardware Reset function
can’t be used.
QE and HOLDB/RST registers can be set by Set Feature command (see Table12-2). QE can be set by Set Feature
command when address is B0H and HOLDB/RST can be set by Set Feature command when address is D0H. Both of
them can be read out by Get Feature command with related address. Through reading the status registers, users could
know the value and infer which function is supported on the pin7.
By default QE and HOLDB/RST registers are both 0 after power-on-reset or hardware reset.
Table12-2. Features Settings
Register
Addr.
7
6
5
4
3
2
1
0
Protection A0H
BRWD
OTP_PRT
Reserved
Reserved BP2
BP1
BP0
INV
CMP
Reserved
Feature
Status
B0H
C0H
D0H
F0H
OTP_EN Reserved ECC_EN Reserved Reserved Reserved QE
Reserved ECCS1 ECCS0 P_FAIL E_FAIL WEL OIP
DS_S0 Reserved Reserved Reserved Reserved Reserved
Reserved ECCSE1 ECCSE0 Reserved Reserved Reserved Reserved
Feature
Status
HOLDB/RST DS_S1
Reserved
b) 24-pin package
For 24-pin package (see Figure2-1), a dedicated RESET# pin is provided and it is independent of QE bit setting. At
the same time, HOLDB/RST register is not existed in 24-pin package, and the corresponding bit in command Set/Get
Feature with address D0H is reserved.
Table12-3. Features Settings
Register
Addr.
7
6
5
4
3
2
1
0
Protection A0H
BRWD
Reserved BP2
BP1
BP0
INV
CMP
Reserved
Feature
Status
B0H
C0H
D0H
F0H
OTP_PRT OTP_EN
Reserved Reserved ECCS1
Reserved DS_S1 DS_S0
Reserved ECC_EN Reserved Reserved Reserved QE
ECCS0 P_FAIL E_FAIL WEL OIP
Reserved Reserved Reserved Reserved Reserved
Feature
Status
Reserved Reserved ECCSE1 ECCSE0 Reserved Reserved Reserved Reserved
39
SPI(x1/x2/x4) NAND Flash
13 ADVANCED FEATURES
2G
13.1 OTP Region
The serial device offers a protected, One-Time Programmable NAND Flash memory area. 4 full pages (2176 bytes per
page) are available on the device. Customers can use the OTP area any way they want, like programming serial
numbers, or other data, for permanent storage. When delivered from factory, feature bit OTP_PRT is 0.
To access the OTP feature, the user must set feature bits OTP_EN/OTP_PRT by SET FEATURES command. When the
OTP is ready for access, pages 00h–03H can be programmed in sequential order by PROGRAM LOAD (02H) and
PROGRAM EXECUTE (10H) commands ( when not yet protected), and read out by PAGE READ (13H) command and
output data by READ from CACHE(03H/0BH/3BH/6BH/BBH/EBH).
Table13-1. OTP States
OTP_PRT
OTP_EN
State
x
0
1
0
1
1
Normal operation
Access OTP region, read and program data.
1. When the device power on state OTP_PRT is 0, user can set feature bit
OTP_PRT and OTP_EN to 1, then issue PROGRAM EXECUTE (10H) to
lock OTP, and after that OTP_PRT will permanently remain 1.
2. When the device power on state OTP_PRT is 1, user can only read the
OTP region data.
Note: The OTP space cannot be erased and after it has been protected, it cannot be programmed again, please use this function
carefully.
Access to OTP data
• Issue the SET FEATURES command (1FH)
• Set feature bit OTP_EN
• Issue the PAGE PROGRAM (only when OTP_PRT is 0) or PAGE READ command
Protect OTP region
Only when the following steps are completed, the OTP_PRT will be set and users can get this feature out with 0FH
command.
• Issue the SET FEATURES command (1FH)
• Set feature bit OTP_EN and OTP_PRT
• 06H (WRITE ENABLE)
• Issue the PROGRAM EXECUTE (10H) command.
40
SPI(x1/x2/x4) NAND Flash
13.2 Block Protection
2G
The block lock feature provides the ability to protect the entire device, or ranges of blocks, from the PROGRAM and
ERASE operations. After power-up, the device is in the “locked” state, i.e., feature bits BP0, BP1and BP2 are set to 1,
INV, CMP and BRWD are set to 0. To unlock all the blocks, or a range of blocks, the SET FEATURES command must be
issued to alter the state of protection feature bits. When BRWD is set and WP# is LOW, none of the writable protection
feature bits can be set. Also, when a PROGRAM/ERASE command is issued to a locked block, status bit OIP remains 0.
When an ERASE command is issued to a locked block, the erase failure, 04H, is returned. When a PROGRAM
command is issued to a locked block, program failure, 08h, is returned.
Table13-2. Block Lock Register Block Protect Bits
CMP
INV
BP2
BP1
BP0
Protect Row Address
2G
Protect Rows
NONE
None—all unlocked
Upper 1/64 locked
Upper 1/32 locked
Upper 1/16 locked
Upper 1/8 locked
Upper 1/4 locked
Upper 1/2 locked
All locked (default)
Lower 1/64 locked
Lower 1/32 locked
Lower 1/16 locked
Lower 1/8 locked
Lower 1/4 locked
Lower 1/2 locked
Lower 63/64 locked
Lower31/32 locked
Lower 15/16 locked
Lower7/8 locked
Lower3/4 locked
Block0
x
0
0
0
0
0
0
x
x
0
0
0
0
0
0
x
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1F800h ~ 1FFFFh
1F000h ~ 1FFFFh
1E000h ~ 1FFFFh
1C000h ~ 1FFFFh
18000h ~ 1FFFFh
10000h ~ 1FFFFh
0000h ~ 1FFFFh
0000h ~7FFh
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0000h ~FFFh
0000h ~ 1FFFh
0000h ~ 3FFFh
0000h ~ 7FFFh
0000h ~ FFFFh
0000h ~ 1F7FFh
0000h ~ 1EFFFh
0000h ~ 1DFFFh
0000h ~ 1BFFFh
0000h ~ 17FFFh
0000h ~ 003Fh
0800h ~ 1FFFFh
1000h ~ 1FFFFh
2000h ~ 1FFFFh
4000h ~ 1FFFFh
8000h ~ 1FFFFh
0000h ~ 003Fh
Upper 63/64 locked
Upper31/32 locked
Upper 15/16 locked
Upper7/8 locked
Upper3/4 locked
Block0
When WP# is not LOW, user can issue bellows commands to alter the protection states as want.
• Issue SET FEATURES register write (1FH)
• Issue the feature bit address (A0h) and the feature bits combination as the table
41
SPI(x1/x2/x4) NAND Flash
2G
13.3 Status Register and Driver Register
The NAND Flash device has an 8-bit status register that software can read during the device operation for operation state
query. The status register can be read by issuing the GET FEATURES (0FH) command, followed by the feature address
C0h or F0h (see FEATURE OPERATION). The Output Driver Register can be set and read by issuing the SET FEATURE
(0FH) and GET FEATURE command followed by the feature address D0h (see FEATURE OPERATION).
Table13-3. Status Register Bit Descriptions
Bit
Bit Name
Description
P_FAIL
Program
Fail
This bit indicates that a program failure has occurred (P_FAIL set to 1). It will also be
set if the user attempts to program an invalid address or a protected region, including
the OTP area. This bit is cleared during the PROGRAM EXECUTE command
sequence or a RESET command (P_FAIL = 0).
E_FAIL
WEL
Erase Fail
This bit indicates that an erase failure has occurred (E_FAIL set to 1). It will also be
set if the user attempts to erase a locked region. This bit is cleared (E_FAIL = 0) at
the start of the BLOCK ERASE command sequence or the RESET command.
This bit indicates the current status of the write enable latch (WEL) and must be set
(WEL = 1), prior to issuing a PROGRAM EXECUTE or BLOCK ERASE command. It
is set by issuing the WRITE ENABLE command. WEL can also be disabled (WEL =
0), by issuing the WRITE DISABLE command.
Write
Enable
Latch
OIP
Operation
This bit is set (OIP = 1 ) when a PROGRAM EXECUTE, PAGE READ, BLOCK
In Progress ERASE, or RESET command is executing, indicating the device is busy. When the
bit is 0, the interface is in the ready state.
ECCS1,
ECCS0
ECC Status ECCS provides ECC status as the following table.
ECCS and ECCSE are set to 00b either following a RESET, or at the beginning of
the READ. They are then updated after the device completes a valid READ
operation.
ECCSE1
ECCSE0
ECCS and ECCSE are invalid if internal ECC is disabled (via a SET FEATURES
command to reset ECC_EN to 0).
After power-on RESET, ECC status is set to reflect the contents of block 0, page 0.
Table13-4. ECC Error Bits Descriptions
ECCS1
ECCS0
ECCSE1 ECCSE0
Description
No bit errors were detected during the previous read
algorithm.
0
0
x
x
Bit errors(<4) were detected and corrected.
Bit errors(=5) were detected and corrected.
Bit errors(=6) were detected and corrected.
Bit errors(=7) were detected and corrected.
Bit errors greater than ECC capability(8 bits) and not corrected
Bit errors reach ECC capability( 8 bits) and corrected
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
1
x
x
0
1
0
1
x
x
42
SPI(x1/x2/x4) NAND Flash
2G
Table13-5. Driver Register Bits Descriptions
DS_S1
DS_S0
Driver Strength
0
0
1
1
0
1
0
1
50%
25%
75%
100%
13.4 Assistant Bad Block Management
As a NAND Flash, the device may have blocks that are invalid when shipped from the factory, and a minimum number of
valid blocks (NVB) of the total available blocks are specified. An invalid block is one that contains at least one page that
has more bad bits than can be corrected by the minimum required ECC. Additional bad blocks may develop with use.
However, the total number of available blocks will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices may contain bad blocks, they can be used reliably in systems that provide
bad-block management and error-correction algorithms, which ensure data integrity. Internal circuitry isolates each block
from other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by
programming the Bad Block Mark (00h) to the first spare area location in each bad block. This method is compliant with
ONFI Factory Defect Mapping requirements. See the following table for the bad-block mark.
System software should initially check the first spare area location for non-FFH data on the first page of each block prior
to performing any program or erase operations on the NAND Flash device. A bad-block table can then be created,
enabling system software to map around these areas. Factory testing is performed under worst-case conditions. Because
invalid blocks may be marginal, it may not be possible to recover the bad-block marking if the block is erased.
To simplify the system requirement and guard the data integration, GigaDevice SPI NAND provides assistant
Management options as below.
Table13-6. Bad Block Mark information
Description
Density
Requirement
Minimum number of valid blocks 2G
(NVB
2008
)
Total available blocks per die
First spare area location
2G
2048
Byte 2048
Bad-block mark
00h(use non FFH to check)
43
SPI(x1/x2/x4) NAND Flash
13.5 Internal ECC
2G
The serial device offers data corruption protection by offering optional internal ECC. READs and PROGRAMs with
internal ECC can be enabled or disabled by setting feature bit ECC_EN. ECC is enabled after device power up, so the
default READ and PROGRAM commands operate with internal ECC in the “active” state. To enable/disable ECC,
perform the following command sequence:
• Issue the SET FEATURES command (1FH).
• Set the feature bit ECC_EN as you want:
1. To enable ECC, Set ECC_EN to 1.
2. To disable ECC, Clear ECC_EN to 0.
During a PROGRAM operation, the device calculates an ECC code on the 2k page in the cache register, before the page
is written to the NAND Flash array.
During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated
and compared with the ECC code value read from the array. If error bits are detected, the error is corrected in the cache
register. Only corrected data is output on the I/O bus. The ECC status bit indicates whether or not the error correction
was successful. The ECC Protection table below shows the ECC protection scheme used throughout a page.
With internal ECC, the user must accommodate the following:
• Spare area definitions provided in the ECC Protection table below. User meta data I is not protected by internal
ECC and User meta data II is protected by internal ECC.
• ECC can protect main data and spare areas data. Any data wrote to the ECC area are ignored.
Table13-7. ECC Protection and Spare Area
Min Byte Address
000H
Max Byte Address
1FFH
ECC Protected Area
Description
Yes
Yes
Main 0
User data 0
200H
3FFH
Main 1
User data 1
400H
5FFH
Yes
Main 2
User data 2
600H
7FFH
Yes
Main 3
User data 3
800H
803H
No(2)
Yes
Spare 0
Spare 0
Spare 1
Spare 1
Spare 2
Spare 2
Spare 3
Spare 3
User meta 0 data I(1)
User meta 0 data II
User meta 1 data I
User meta 1 data II
User meta 2 data I
User meta 2 data II
User meta 3 data I
User meta 3 data II
804H
80FH
810H
813H
No(2)
Yes
814H
81FH
820H
823H
No(2)
Yes
824H
82FH
830H
833H
No(2)
Yes
834H
83FH
840H
87FH
Yes
Spare area Internal ECC parity data
Note:
1. 800H is reserved for initial bad block mark
2. There is no internal ECC for this area, so external protection must be provided by the user. Please see
AN-00180-GD5FxGxxxExxx for detailed information
3. When Internal ECC is enabled，user cannot program the Address 840H~87FH but user can read the Address
840H~87FH.
4. When Internal ECC is disabled, the whole page area is open for user.
44
SPI(x1/x2/x4) NAND Flash
14 POWER ON TIMING
2G
Figure14-1. Power on Timing Sequence
Vcc(max)
Vcc(min)
VWI
Chip Selection is not allowed
tVSL
Device is fully
accessible
Time
Table14-1. Power-On Timing and Write Inhibit Threshold for 1.8V/3.3V
Symbol
Parameter
VCC(min) To CS# Low
Write Inhibit Voltage
Min
Max
Unit
tVSL
5
ms
1.8V
3.3V
1.7
2.5
VWI
V
45
SPI(x1/x2/x4) NAND Flash
2G
15 ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Operating Temperature
Storage Temperature
Applied Input/Output Voltage
VCC
Value
Unit
-40 to 105
-55 to 125
-0.6 to 4.0
-0.6 to 4.0
℃
℃
V
V
46
SPI(x1/x2/x4) NAND Flash
2G
16 CAPACITANCE MEASUREMENT CONDITIONS
Symbol
CIN
Parameter
Min
Typ
Max
6
Unit
pF
pF
pF
ns
V
Conditions
Input Capacitance
VIN=0V
COUT
CL
Output Capacitance
8
VOUT=0V
Load Capacitance
30
Input Rise And Fall time
Input Pulse Voltage
5
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
V
V
Figure16-1. Input Test Waveform and Measurement Level
Input timing reference level
0.7VCC
Output timing reference level
0.5VCC
0.8VCC
0.1VCC
AC Measurement Level
0.2VCC
Note: Input pulse rise and fall time are<5ns
47
SPI(x1/x2/x4) NAND Flash
17 DC CHARACTERISTIC
2G
(T= -40℃~85℃, VCC=1.7~2.0V/2.7~3.6V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
110(1)
μA
VIN=VCC or VSS
CLK=0.1VCC /
0.9VCC
40
30
mA
mA
at 108MHz,
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC /
0.9VCC
ICC2
Operating Current (Read)
at 80MHz,
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC3
ICC4
VIL
Operation Current (PP)
Operation Current (BE)
Input Low Voltage
40
40
mA
mA
V
CS#=VCC
0.2VCC
VIH
Input High Voltage
0.7VCC
VCC-0.2
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =1.6mA
0.4
V
IOH =-100μA
V
Note: 1. When Temperature is 105℃, the maximum standby current is 200uA
48
SPI(x1/x2/x4) NAND Flash
18 AC CHARACTERISTICS
2G
(T= -40℃~105℃, VCC=1.7~2.0V/2.7~3.6V, CL=30pf)
Symbol
FC
Parameter
Serial Clock Frequency For: all command
Serial Clock High Time
Min.
DC.
4
Typ.
Max.
Unit.
120
MHz
ns
tCH
tCL
Serial Clock Low Time
4
ns
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
0.2
0.2
5
V/ns
V/ns
ns
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
CS# Not Active Hold Time
5
ns
5
ns
tSHSL/tCS CS# High Time
Output Disable Time
20
ns
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
tCLQV
tWHSL
tSHWL
20
ns
Output Hold Time
2
2
2
5
5
5
5
ns
Data In Setup Time
ns
Data In Hold Time
ns
Hold# Low Setup Time (relative to Clock)
Hold# High Setup Time (relative to Clock)
Hold# High Hold Time (relative to Clock)
Hold# Low Hold Time (relative to Clock)
Hold# Low To High-Z Output
Hold# High To Low-Z Output
Clock Low To Output Valid
ns
ns
ns
ns
15
15
8
ns
ns
ns
WP# Setup Time Before CS# Low
WP# Hold Time After CS# High
20
ns
100
ns
49
SPI(x1/x2/x4) NAND Flash
19 PERFORMANCE TIMING
2G
Symbol
TRST
Parameter
CS# High To Next Command After Reset(FFh)
Read From Array
Min.
Typ.
Max.
500
80
Unit.
us
us
tRD
tPROG
tBERS
Page Programming Time
0.4
3
0.7
5
ms
ms
Block Erase Time
Figure19-1. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCLCH
tCHDX
SI
MSB
High-Z
LSB
SO
Figure19-2. Output Timing
CS#
tCH
tSHQZ
SCLK
tCLQV
tCLQV
tCLQX
tCL
tCLQX
SO
SI
LSB
Least significant address bit (LIB) in
50
SPI(x1/x2/x4) NAND Flash
2G
Figure19-3. Hold Timing
CS#
tCHHL
tHLCH
tHHCH
tHHQX
SCLK
tCHHH
tHLQZ
SO
HOLD#
SI do not care during HOLD operation.
Figure19-4. Reset Timing
FFh
OIP
OIP
tRST
Note: The maximum tRST depends on different operations.
Idle:
maximum tRST = 5us;
maximum tRST = 5us;
Read:
Program: maximum tRST = 10us;
Erase: maximum tRST = 500us;
51
SPI(x1/x2/x4) NAND Flash
20 ORDERING INFORMATION
2G
GD XX XX XX X X X X X X
Packing Type
T or No mark: Tube
R: Tape & Reel
Y: Tray
GD Prefix
Green Code
G: Pb Free & Halogen Free Green Package
S: G + special function (HW Reset + UID +
Parameter Page)
H: Pb Free & Halogen Free Green Package +
Half of Spare Size
Temperature Range
I: Industrial(-40C to +85C)
J:Industrial(-40 to +105 )
F: Industrial+(1) (-40 ꢀto +85 )
Package Type
Y: WSON8 (6*8mm)
F: SOP16 300mil
Z:TFBGA24(6*4 Ball Array)
9: LGA8 6*8mm
Generation
B: B Version
C: C Version
E: E Version
F: F Version
Voltage
U:3.3V(2.7~3.6V)
R:1.8V(1.7~2.0V)
Interface
Q4: Qua SPI x1/x2/x4
Density
1G: 1Gb 2G: 2Gb
4G: 4Gb 8G: 8Gb
Product Family
5F: SPI NAND Flash
Note: (1) Industrial+: Full Function Test for Automotive application and no AECQ.
52
SPI(x1/x2/x4) NAND Flash
21 PACKAGE INFORMATION
2G
Figure21-1. TFBGA-24BALL 6*8mm (6*4 ball array)
1
2
3
4
4
3
2
1
A
B
C
D
E
F
A
e
B
C
D
E
F
SD
E1
E
SE
e
D
D1
Φb
Dimensions
Symbol
Unit
A
A1
A2
b
D
D1
E
E1
e
SE
SD
Min
0.25
0.30
0.35
0.70
0.80
0.85
0.35
0.40
0.45
5.90
6.00
7.90
8.00
3.00
BSC
5.00
BSC
1.00
BSC
0.50
TYP
0.50
TYP
mm
Nom
Max
Min
1.20
6.10
8.10
0.010 0.028 0.014
0.012 0.031 0.016
0.232
0.236
0.240
0.311
0.315
0.319
0.118
BSC
0.197
BSC
0.039
BSC
0.020
TYP
0.020
TYP
Inch Nom
Max
0.047 0.014 0.034 0.018
Note: Both the package length and width do not include the mold flash.
53
SPI(x1/x2/x4) NAND Flash
2G
Figure21-2. LGA8 GD Type2 (6*8 mm)
D2
A
D
L
2
A2
A
Lead Type design Gap
c
Soldermask
LAND PAD
A1
Dimensions
Symbol
A
A2
GD
E2
e
A1
c
b
D
D2
E
L
Unit
GD
Type2
Type2
Min
0.80
0.15
0.18
0.21
0.35
0.40
0.45
7.90
8.00
3.30
3.40
5.90
6.00
4.20
4.30
0.45
0.50
0.02
0.70
1.27
0.05
mm
Nom
Max
Min
0.95
8.10
3.50
6.10
4.40
0.55
0.031
0.006 0.014
0.311
0.315
0.319
0.130
0.134
0.138
0.232
0.165
0.018
0,020
0.022
Inch
Nom
Max
0.001
0.028
0.007
0.008
0.016
0.018
0.236 0.169
0.240 0.173
0.037
54
SPI(x1/x2/x4) NAND Flash
22 REVISION HISTORY
2G
Version No
Description
Date
Page
1.0
1.1
Initial Release
2017-07-03
2017-07-14
Add parameter page CRC value
Modify Package TFBGA-24BALL (6*8 ball array)
Delete Package WSON8 (6*8mm) & SOP16 300MIL
Modify the Number of Figure and Table
Modify some typo of Read Operation Sequence Diagram
Reduce the size of parameter page device model table
Modify TFBGA-24BALL description
1.2
2017-7-20
1.3
2017-9-1
Modify Read CID command sequence description
Delete Package WSON8 in ORDERING INFORMATION
Add the Note article 4 of Page Program
Add the chapter of Valid Part Numbers
Add the description of 2Gb SLC NAND Flash
Add the description of Reliability
1.4
1.5
1.6
2017-9-26
2017-10-23
2017-11-03
1.7
2017-12-11
Modify the Figure of Program Load Sequence Diagram typo
Modify the package of LGA8
Modify the package of TFBGA24
1.8
1.9
Modify the typo of LGA8
2017-12-27
2018-1-16
Add a note for Figure7-1
Add 01h address for ID table
Add LGA8 package description for hardware reset section
Modify some typo.
Add Temperature Range J:Industrial(-40 ℃ to 105℃) and
related description
Change Memory Mapping CA from <12:0> to <11:0>,RA from
<17:6> to <16:6>
Add a figure to description Read ID sequence
Add page size 2048bytes + 64bytes with ECC enabled
Modify figure 10-1,11-1,11-4,11-5,11-6 Byte from 4352 or 4351 to
2176/2112, and add a note to explain
2.0
2018-2-13
Change Parameter page table Byte 105-106 and 108-109,and
change CRC Value
Merge chapters 2.1 and 20.1
Change the description of protection with WP# Pin
Add Temperature Range F:Industrial+ (-40℃ to 85℃)
Modify the Value of Applied Input/ Output Voltage and VCC in
Chapter15
2.1
2.2
2018-3-12
2018-7-25
Modify the description of LGA8 6*8mm package
Update Ordering Information
55
SPI(x1/x2/x4) NAND Flash
2G
2.3
2.4
Add Note2 to Table13-7
2018-8-22
Modify the file name
2018-10-17
Update the ordering information
Add Note describe the spare size with Internal ECC ON.
Add the Array Organization with Internal ECC ON.
Add Note of Address with Internal ECC ON.
Add “Power Off Timing” in Device Operation.
Correct the ID table, delete useless description.
Update the Important Notice. “Customers shall discard the device
according to the local environmental law.”
Correct “ABSOLUTE MAXIMUM RATINGS” Applied Input/ Output
Voltage
4/8
8
45
11
22
58
2.5
2019-3-25
47
Update Parameter Page Byte 97,Byte 103; Recalculate CRC
Remove CID function
28/30
25
56
SPI(x1/x2/x4) NAND Flash
2G
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57
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