GS256418GB-250IVT_技术文档

Advanced Information

GS8256418/36(GB/GD)-xxxV

119- & 165-Bump BGA

Commercial Temp

Industrial Temp

333 MHz–200 MHz

16M x 18, 8M x 36

288Mb DCD Sync Burst SRAMs

1.8 V or 2.5 V V

DD

1.8 V or 2.5 V I/O

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 1.8 V +10%/–10% core power supply

• 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• ZZ pin for automatic power-down

• RoHS-compliant 119-bump and 165-bump BGA packages

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

Register.

DCD Pipelined Reads

The GS8256418/36-xxxV is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of clock.

Functional Description

Applications

The GS8256418/36-xxxV is a 301,989,888-bit high performance

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Controls

FLXDrive™

Addresses, data I/Os, chip enable (E1), address burst control

The ZQ pin allows selection between high drive strength (ZQ low)

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Core and Interface Voltages

The GS8256418/36-xxxV operates on a 1.8 V or 2.5 V power

supply. All input are 31.8 V or 2.5 V compatible. Separate output

Parameter Synopsis

-333

2.5

3.0

-250

-200

Unit

t_KQ

2.5

4.0

3.0

5.0

ns

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x36)

TBD

mA

t_KQ

tCycle

4.5

5.5

6.5

ns

Flow Through

2-1-1-1

Curr (x18)

Curr (x36)

TBD

mA

Rev: 1.01 8/2016

1/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

119-Bump BGA—x36 Common I/O—Top View

1

2

A

3

A

4

5

A

6

A

7

V

DDQ

A

B

C

D

E

F

ADSP

ADSC

A

B

C

D

E

F

DDQ

A

NC

V

A

DD

V

DQC

DQPC

DQC

ZQ

E1

DQPB

DQB

SS

V

DDQ

G

DDQ

G

H

J

DQC2

BC

ADV

GW

BB

DQB

G

H

J

V

SS

DQC

DQB

SS

V

NC

DDQ

DD

DDQ

DQA

V

K

L

DQD

DQPD

A

CK

NU

BW

A1

DQA

DQPA

A

K

L

SS

BD

BA

V

DDQ

M

N

P

R

T

M

N

P

R

T

DDQ

SS

V

DQD

NC

DQA

SS

V

A0

DQA

NC

ZZ

SS

V

LBO

A

FT

A

DD

NC

A

TCK

2

A

V

DDQ

U

TMS

TDI

TDO

NC

U

DDQ

7 x 17 Bump BGA—14 x 22 mm Body—1.27 mm Bump Pitch

Rev: 1.01 8/2016

2/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

119-Bump BGA—x18 Common I/O—Top View

1

2

A

3

A

4

5

A

6

A

7

V

DDQ

A

B

C

D

E

F

ADSP

ADSC

A

B

C

D

E

F

DDQ

A

NC

V

A

DD

V

DQB

NC

DQB

NC

DQB

NC

ZQ

E1

DQPA

NC

DQA

NC

DQA

NC

SS

V

DQA

V

DDQ

G

DDQ

G

H

J

NC

BB

ADV

GW

NC

DQA

G

H

J

V

DQB

NC

SS

V

NC

DDQ

DD

DDQ

DQA

NC

V

K

L

NC

DQB

NC

CK

NU

BW

A1

NC

DQA

NC

DQA

NC

A

K

L

SS

DQB

NC

BA

V

DDQ

M

N

P

R

T

DQB

NC

M

N

P

R

T

DDQ

SS

V

DQB

NC

SS

V

NC

A

DQPB

A

A0

DQA

NC

ZZ

SS

V

LBO

A

FT

A

DD

A

TCK

2

A

V

DDQ

U

TMS

TDI

TDO

NC

U

DDQ

7 x 17 Bump BGA—14 x 22 mm Body—1.27 mm Bump Pitch

Rev: 1.01 8/2016

3/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

119-Bump BGA Pin Description

Symbol

A0, A1

An

Type

Description

I

Address field LSBs and Address Counter Preset Inputs

Address Inputs

DQ^A

DQB

DQC

DQD

I/O

Data Input and Output pins

BA, BB, BC, BD

I

—

I

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

No Connect

NC

CK

Clock Input Signal; active high

BW

I

Byte Write—Writes all enabled bytes; active low

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

GW

I

E1

I

G

ADV

I

Output Enable; active low

I

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep mode control; active high

ADSP, ADSC

ZZ

I

FT

I

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

LBO

I

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

ZQ

I

Scan Test Mode Select

Scan Test Data In

TMS

TDI

O

I

Scan Test Data Out

Scan Test Clock

TDO

TCK

V

I

Core power supply

I/O and Core Ground

DD

V

I

SS

V

I

SS

V

I

Output driver power supply

No Connect

DDQ

NC

NU

—

Not Used

Rev: 1.01 8/2016

4/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

165-Bump BGA—x18 Commom I/O—Top View

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

A

E1

BB

NC

BW

ADSC

ADV

A

B

C

D

E

F

A

NC

A

NC

DQB

NC

NU

A

NC

BA

CK

GW

G

ADSP

A

NC

ZQ

NC

DQPA

DQA

ZZ

V

DDQ

SS

DD

SS

DD

DDQ

NC

V

NC

G

H

J

NC

G

H

J

FT

NC

DQB

DQPB

NC

V

DQA

NC

A

NC

DDQ

K

L

V

NC

K

L

NC

M

N

P

R

NC

M

N

P

R

V

NC

TDI

A

NC

V

NC

DDQ

SS

DDQ

A

A1

A0

TDO

TCK

A

LBO

A

TMS

A

11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch

Rev: 1.01 8/2016

5/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

165-Bump BGA—x36 Common I/O—Top View

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

A

E1

BC

BB

NC

BW

ADSC

ADV

NC

A

B

C

D

E

F

A

NC

BD

BA

CK

GW

G

ADSP

A

NC

DQPB

DQB

ZZ

DQPC

DQC

FT

NC

V

NC

DDQ

SS

DD

SS

DD

DDQ

DQC

NC

V

DQB

ZQ

G

H

J

G

H

J

NC

DQD

DQPD

NC

DQD

NU

V

DQA

NC

DQA

DQPA

A

DDQ

K

L

V

K

L

M

N

P

R

M

N

P

R

V

NC

TDI

A

NC

V

SS

DDQ

SS

DDQ

A

A1

A0

TDO

TCK

A

LBO

A

TMS

A

11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch

Rev: 1.01 8/2016

6/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

165-Bump BGA Pin Description

Symbol

A0, A1

A

Type

Description

I

Address field LSBs and Address Counter Preset Inputs

Address Inputs

DQ^A

DQB

DQC

DQD

I/O

Data Input and Output pins

BA, BB, BC, BD

I

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)

Clock Input Signal; active high

CK

BW

Byte Write—Writes all enabled bytes; active low

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

GW

E1

G

ADV

Output Enable; active low

Burst address counter advance enable; active l0w

Address Strobe (Processor, Cache Controller); active low

Sleep mode control; active high

ADSC, ADSP

ZZ

FT

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

LBO

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

ZQ

I

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

TMS

TDI

O

I

TDO

TCK

MCL

—

I

Must Connect Low

Core power supply

I/O and Core Ground

V

DD

V

I

SS

V

I

Output driver power supply

No Connect

DDQ

NC

NU

—

Not Used

Rev: 1.01 8/2016

7/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

GS8256418/36 Block Diagram

Register

A0–An

D

Q

A0

A1

D0

D1

Q0

A1

Q1

Counter

Load

A

LBO

ADV

Memory

Array

CK

ADSC

ADSP

Q

D

Register

GW

BW

BA

D

Q

Register

36

D

Q

BB

BC

BD

4

Register

D

Q

Register

D

Q

Register

D

Q

Register

E1

D

Q

Register

D

Q

FT

G

1

Power Down

Control

DQx1–DQx9

ZZ

Note: Only x36 version shown for simplicity.

Rev: 1.01 8/2016

8/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

Mode Pin Functions

Mode Name

Pin Name

State

Function

Linear Burst

Interleaved Burst

Flow Through

Pipeline

L

Burst Order Control

LBO

H

L

Output Register Control

FT

ZZ

ZQ

H or NC

L or NC

H

Active

Power Down Control

Standby, I = I

DD SB

L

High Drive (Low Impedance)

Low Drive (High Impedance)

FLXDrive Output Impedance Control

H or NC

Note:

There are pull-up devices on the ZQ and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip

will operate in the default states as specified in the above tables.

Burst Counter Sequences

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

1st address

2nd address

3rd address

4th address

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Note:

The burst counter wraps to initial state on the 5th clock.

Note:

The burst counter wraps to initial state on the 5th clock.

Rev: 1.01 8/2016

9/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

Byte Write Truth Table

Function

Read

GW

H

BW

H

L

BA

X

BB

X

BC

X

BD

X

Notes

1

Write No Bytes

Write byte a

Write byte b

Write byte c

Write byte d

Write all bytes

H

L

H

L

H

L

H

L

1

H

L

2, 3

H

L

H

L

2, 3

H

L

H

L

2, 3, 4

H

L

H

L

H

L

Write all bytes

L

X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.

2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x32 and x36 versions.

Rev: 1.01 8/2016

10/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

Synchronous Truth Table

State

Diagram

Key

Address

Used

3

Operation

E1

ADSP

ADSC

ADV

W

DQ

Deselect Cycle, Power Down

Read Cycle, Begin Burst

None

External

R

H

L

X

L

X

L

X

L

H

X

F

T

F

T

F

T

High-Z

Q

D

Q

D

Q

D

Read Cycle, Begin Burst

R

L

H

X

H

X

H

X

H

X

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

W

L

CR

CW

X

H

X

H

X

H

X

H

Current

Notes:

1. X = Don’t Care, H = High, L = Low

2. E = T (True) when E1 = 0

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.01 8/2016

11/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

Simplified State Diagram

X

Deselect

W

R

W

R

X

R

X

First Write

First Read

CW

CR

W

R

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and

that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and

assumes ADSP is tied high and ADV is tied low.

Rev: 1.01 8/2016

12/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

Simplified State Diagram with G

X

Deselect

W

R

W

R

X

W

R

X

First Write

First Read

CR

CW

CR

W

R

W

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.01 8/2016

13/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

V_DD

V_DDQ

V_I/O

Description

Value

Unit

V

Voltage on V_DDPins

Voltage in V_DDQPins

–0.5 to 4.6

V

–0.5 to V_DDQ+0.5 ( 4.6 V max.)

–0.5 to V_DD+0.5 ( 4.6 V max.)

Voltage on I/O Pins

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

V

V_IN

V

I_IN

+/–20

mA

W

I_OUT

P_D

1.5

^oC

T_STG

–55 to 125

T_BIAS

Temperature Under Bias

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Power Supply Voltage Ranges (1.8 V/2.5 V Version)

Parameter

Symbol

Min.

1.7

Typ.

1.8

Max.

2.0

Unit

V

1.8 V Supply Voltage

2.5 V Supply Voltage

V

DD1

V

2.3

2.5

2.7

DD2

1.8 V V

I/O Supply Voltage

V

1.7

1.8

DDQ

DDQ1

DD

2.5 V V

I/O Supply Voltage

V

2.3

2.5

DDQ2

DD

V

& V

Range Logic Levels

Parameter

DDQ2

DDQ1

Symbol

Min.

Typ.

—

Max.

Unit

V

Input High Voltage

Input Low Voltage

V

0.6*V

V

+ 0.3

DD

IH

DD

V

0.3*V

DD

–0.3

—

V

DD

IL

Note:

Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.

Rev: 1.01 8/2016

14/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

Recommended Operating Temperatures

Parameter

Symbol

Min.

0

Typ.

25

Max.

85

Unit

C

T_J

Junction Temperature (Commercial Range Versions)

Junction Temperature (Industrial Range Versions)*

–40

25

100

C

Note:

* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications

quoted are evaluated for worst case in the temperature range marked on the device.

Thermal Impedance

Test PCB

Substrate

JA (C°/W)

Airflow = 0 m/s

 JA (C°/W)

Airflow = 1 m/s

 JA (C°/W)

Airflow = 2 m/s

Package

JB (C°/W)

 JC (C°/W)

119 BGA

165 BGA

4-layer

TBD

9.14

TBD

2.96

20.70

17.51

16.44

Notes:

1. Thermal Impedance data is based on a number of samples from multiple lots and should be viewed as a typical number.

2. Please refer to JEDEC standard JESD51-6.

3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to

the PCB can result in cooling or heating of the RAM depending on PCB temperature.

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKC

V

+ 2.0 V

DD

V

SS

50%

V

DD

V

– 2.0 V

SS

20% tKC

V

IL

Note:

Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 2.5 V)

A

DD

Parameter

Symbol

C_IN

Test conditions

V_IN= 0 V

Typ.

Max.

Unit

pF

Input Capacitance

4

6

5

7

C_I/O

V_OUT= 0 V

Input/Output Capacitance

pF

Note:

These parameters are sample tested.

Rev: 1.01 8/2016

15/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

AC Test Conditions

Parameter

Input high level

Input low level

Conditions

V_DD– 0.2 V

0.2 V

1 V/ns

V_DD/2

Input slew rate

Input reference level

V

_DDQ/2

Output reference level

Output load

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

Output Load 1

DQ

*

50

30pF

V

DDQ/2

* Distributed Test Jig Capacitance

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I_IL

V_IN= 0 to V_DD

–1 uA

1 uA

V_DD V_IN V_IH

0 V V_INV_IH

–1 uA

1 uA

100 uA

I_IN1

ZZ Input Current

V_DD V_IN V_IL

0 V V_INV_IL

–100 uA

–1 uA

1 uA

I_IN2

FT, ZQ Input Current

I_OL

Output Disable, V_OUT= 0 to V_DD

I_OH= –8 mA, V_DDQ= 2.375 V

I_OH= –8 mA, V_DDQ= 3.135 V

I_OL= 8 mA

Output Leakage Current

Output High Voltage

Output Low Voltage

–1 uA

1.7 V

2.4 V

—

1 uA

—

V_OH2

V_OH3

V_OL

—

0.4 V

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

Operating Currents

-333

-250

-200

0

to

–40

to

0

to

–40

to

0

to

–40

to

Parameter

Test Conditions

Mode

Symbol

Unit

85°C

100°C

85°C

100°C

85°C

100°C

I_DD

TBD

Pipeline

mA

I_DDQ

(x36)

(x18)

I_DD

I_DDQ

TBD

Device Selected;

All other inputs

V_IHor V_IL

Flow Through

Pipeline

Operating

Current

I_DD

I_DDQ

TBD

Output open

I_DD

TBD

Flow Through

I_DDQ

I_SB

I_DD

Pipeline

Flow Through

Pipeline

TBD

mA

Standby

Current

ZZ V_DD– 0.2 V

—

Device Deselected;

All other inputs

V_IHor  V_IL

Deselect

Current

I_DD

Flow Through

TBD

mA

Notes:

1.

2. All parameters listed are worst case scenario.

I

and I

apply to any combination of V , V , V

, and V operation.

DDQ2

DD

DDQ

DD3 DD2 DDQ3

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

AC Electrical Characteristics

-333

-250

-200

Parameter

Symbol

Min

3.0

—

Max

—

2.5

—

4.5

—

Min

4.0

—

Max

—

2.5

—

5.5

—

Min

5.0

—

Max

—

3.0

—

6.5

—

Clock Cycle Time

Clock to Output Valid

Clock to Output Invalid

Clock to Output in Low-Z

Setup time

tKC

tKQ

ns

tKQX

1.5

1.0

0.1

4.5

—

1.5

1.2

0.2

5.5

—

1.5

1.4

0.4

6.5

—

Pipeline

1

tLZ

tS

tH

Hold time

Clock Cycle Time

Clock to Output Valid

Clock to Output Invalid

Clock to Output in Low-Z

Setup time

tKC

tKQ

tKQX

2.0

1.3

0.3

1.0

1.2

2.0

1.5

0.5

1.3

1.5

2.0

1.5

0.5

1.3

1.5

Flow Through

1

tLZ

tS

tH

Hold time

Clock HIGH Time

Clock LOW Time

tKH

tKL

Clock to Output in

High-Z

1

1.5

2.5

1.5

2.5

1.5

3.0

ns

tHZ

G to Output Valid

G to output in Low-Z

G to output in High-Z

ZZ setup time

tOE

—

0

2.5

—

2.5

—

0

2.5

—

2.5

—

0

3.0

—

3.0

—

ns

1

tOLZ

1

—

5

—

5

—

5

tOHZ

2

tZZS

2

ZZ hold time

1

tZZH

ZZ recovery

tZZR

20

Notes:

1. These parameters are sampled and are not 100% tested.

ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as

specified above

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Advanced Information

GS8256418/36(GB/GD)-xxxV

Pipeline Mode Timing (DCD)

Begin

Read A

Cont

Deselect Deselect Write B

tKL

Read C

Read C+1 Read C+2 Read C+3 Cont

Deselect Deselect

tKH

tKC

CK

ADSP

tS

tH

ADSC initiated read

ADSC

ADV

tS

tH

tS

tH

Ao-An

GW

A

B

C

tS

tH

BW

tS

Ba -Bd

tS

tH

Deselected with E1

E1

G

tS

tKQ

tLZ

tHZ

tOE

tOHZ

Q(A)

tH

tKQX

DQa-DQd

Hi-Z

D(B)

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

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Advanced Information

GS8256418/36(GB/GD)-xxxV

Flow Through Mode Timing (DCD)

Begin

Read A

Cont

tKH

Deselect

tKC

Write B

Read C

Read C+1 Read C+2 Read C+3 Read C

Deselect

tKL

CK

ADSP

Fixed High

tS

ADSC initiated read

tH

ADSC

ADV

tS

tH

tS

tH

Ao-An

GW

A

B

C

tS

tH

tS

tH

BW

tH

tS

Ba -Bd

tS

E1 masks ADSP

tH

Deselected with E1

E1

G

tOE

tKQ

tS

tHZ

tKQX

tOHZ

tH

tLZ

DQa-DQd

Q(A)

D(B)

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

Q(C)

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of

SB

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

SB

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing

tKH

tKC

tKL

CK

Setup

Hold

ADSP

ADSC

tZZR

tZZS

tZZH

ZZ

Application Tips

Dual Cycle Deselect

DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait

states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus

contention.

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output

DD

drivers are powered by V

.

DDQ

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

DD

SS

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Advanced Information

GS8256418/36(GB/GD)-xxxV

JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TCK

Test Clock

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

TMS

TDI

Test Mode Select

Test Data In

In controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in

Out response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

TDO

Test Data Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

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Advanced Information

GS8256418/36(GB/GD)-xxxV

JTAG TAP Block Diagram

·

Boundary Scan Register

·

0

Bypass Register

2

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1

0

·

· · ·

Control Signals

Test Access Port (TAP) Controller

TMS

TCK

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

GSI Technology

Not Used

JEDEC Vendor

ID Code

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

0 1 1 0 1 1 0 0 1

0

1

X

0

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Advanced Information

GS8256418/36(GB/GD)-xxxV

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

1

Run Test Idle

Select DR

Select IR

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This

occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-

tate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is

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Advanced Information

GS8256418/36(GB/GD)-xxxV

loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and

I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and

are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because

the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will

not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the

TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP

operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then

places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with

all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is

still determined by its input pins.



Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.

Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output

drivers on the falling edge of TCK when the controller is in the Update-IR state.



Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-

tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-

ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR

state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-

ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

Rev: 1.01 8/2016

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

JTAG TAP Instruction Set Summary

Instruction

EXTEST

Code

000

Description

Notes

1

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

IDCODE

001

1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z

010

011

TDO.

1

Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

100

101

110

111

1

GSI

GSI private instruction.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

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Advanced Information

GS8256418/36(GB/GD)-xxxV

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

2.0

Max.

Unit Notes

V

+0.3

DD3

3.3 V Test Port Input High Voltage

3.3 V Test Port Input Low Voltage

2.5 V Test Port Input High Voltage

2.5 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

V

1

IHJ3

V

–0.3

0.8

+0.3

ILJ3

V

0.6 * V

V

1

IHJ2

DD2

V

0.3 * V

1

–0.3

–300

–1

V

1

ILJ2

DD2

I

uA

V

2

INHJ

I

100

1

3

INLJ

I

–1

4

OLJ

V

Test Port Output High Voltage

1.7

—

5, 6

5, 7

5, 8

5, 9

OHJ

V

Test Port Output Low Voltage

—

0.4

V

OLJ

V

– 100 mV

DDQ

Test Port Output CMOS High

—

V

OHJC

V

Test Port Output CMOS Low

—

100 mV

V

OLJC

Notes:

1. Input Under/overshoot voltage must be –2 V < Vi < V

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

2.

V

 V V

ILJ

IN

DDn

ILJn

3. 0 V V V

IN

4. Output Disable, V

= 0 to V

DDn

OUT

5. The TDO output driver is served by the V

supply.

DDQ

6.

7.

8.

9.

I

= –4 mA

OHJ

= + 4 mA

OLJ

= –100 uA

= +100 uA

OHJC

OLJC

JTAG Port AC Test Conditions

Parameter

Conditions

JTAG Port AC Test Load

V

– 0.2 V

Input high level

Input low level

DQ

DD

0.2 V

1 V/ns

*

50

Input slew rate

30pF

V

/2

Input reference level

DDQ

V

/2

DDQ

/2

Output reference level

DDQ

* Distributed Test Jig Capacitance

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

JTAG Port Timing Diagram

tTKC

tTKH

tTKL

TCK

TDI

tTH

tTS

TMS

TDO

tTKQ

tTH

tTS

Parallel SRAM input

JTAG Port AC Electrical Characteristics

Parameter

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

Max

—

Unit

TCK Cycle Time

50

—

ns

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

20

—

20

10

—

tTH

—

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications

Engineering Department at: apps@gsitechnology.com.

Rev: 1.01 8/2016

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Advanced Information

GS8256418/36(GB/GD)-xxxV

Package Dimensions—119-Bump FPBGA, Variation 2

TOP VIEW

BOTTOM VIEW

A1

S

Ø0.10

C

S

Ø0.30 C A

B

Ø0.60~0.90 (119x)

1

2

3

4

5

6

7

6

5

4 3

2

1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

M

N

P

K

L

M

N

P

R

T

U

R

T

U

B

1.27

7.62

14±0.10

A

0.20(4x)

SEATING PLANE

C

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Advanced Information

GS8256418/36(GB/GD)-xxxV

Package Dimensions—165-Bump FPBGA (Package GD)

A1 CORNER

TOP VIEW

BOTTOM VIEW

A1 CORNER

M

Ø0.10

C

Ø0.25 C A B

Ø0.40~0.60 (165x)

1

2 3 4 5 6 7 8 9 10 11

11 10 9 8

7 6 5 4 3 2 1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

M

N

P

R

A

1.0

10.0

1.0

13±0.05

B

0.20(4x)

SEATING PLANE

C

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

Ordering Information for GSI Synchronous Burst RAMs

2

Speed

3

1

Org

Type

Package

T

Part Number

J

(MHz/ns)

16M x 18

8M x 36

16M x 18

8M x 36

16M x 18

8M x 36

16M x 18

8M x 36

GS8256418GB-333V

GS8256418GB-250V

GS8256418GB-200V

GS8256436GB-333V

GS8256436GB-250V

GS8256436GB-200V

GS8256418GB-333IV

GS256418GB-250IV

GS8256418GB-200IV

GS8256436GB-333IV

GS8256436GB-250IV

GS8256436GB-200IV

GS8256418GD-333V

GS8256418GD-250V

GS8256418GD-200V

GS8256436GD-333V

GS8256436GD-250V

GS8256436GD-200V

GS8256418GD-333IV

GS8256418GD-250IV

GS8256418GD-200IV

GS8256436GD-333IV

GS8256436GD-250IV

GS8256436GD-200IV

PL/FT

RoHS-compliant 119 BGA (var.2)

RoHS-compliant 165 BGA

333/4.5

250/5.5

200/6.5

333/4.5

250/5.5

200/6.5

333/4.5

250/5.5

200/6.5

333/4.5

250/5.5

200/6.5

333/4.5

250/5.5

200/6.5

333/4.5

250/5.5

200/6.5

333/4.5

250/5.5

200/6.5

333/4.5

250/5.5

200/6.5

C

I

C

I

RoHS-compliant 165 BGA

I

RoHS-compliant 165 BGA

I

RoHS-compliant 165 BGA

I

RoHS-compliant 165 BGA

I

RoHS-compliant 165 BGA

I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8256418GB-200IVT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/

Flow Through mode-selectable by the user.

3. C = Commercial Temperature Range. I = Industrial Temperature Range.

4.

GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this

data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.01 8/2016

31/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Advanced Information

GS8256418/36(GB/GD)-xxxV

288Mb Sync SRAM Datasheet Revision History

Types of Changes

File Name

Revision(s)

Format or Content

• Creation of new datasheet

• Removed all SCD references

82564xx_V_r1

82564xx_V_r1_01

Content

Rev: 1.01 8/2016

32/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS256418GB-250IVT
厂家：	GSI TECHNOLOGY
描述：	Cache SRAM, 16MX18, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-119 静态存储器内存集成电路
文件：	总32页 (文件大小：581K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS256418GB-250IVT [GSI]

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