GS4576C18L-33 [GSI]
576Mb CIO Low Latency DRAM (LLDRAM II);
| 型号： | GS4576C18L-33 |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | 576Mb CIO Low Latency DRAM (LLDRAM II) 动态存储器 |
| 文件： | 总63页 (文件大小：2120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS4576C09/18/36L
533 MHz–300 MHz
144-Ball BGA
Commercial Temp
Industrial Temp
64M x 9, 32M x 18, 16M x 36
576Mb CIO Low Latency DRAM (LLDRAM II)
2.5 V VEXT
1.8 V VDD
1.5 V or 1.8 V VDDQ
Features
Introduction
• Pin- and function-compatible with Micron RLDRAM® II
• 533 MHz DDR operation (1.067Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency)
• 16M x 36, 32M x 18, and 64M x 9 organizations available
• 8 banks
• Reduced cycle time (15 ns at 533 MHz)
• Address Multiplexing (Nonmultiplexed address option
available)
• SRAM-type interface
• Programmable Read Latency (RL), row cycle time, and burst
sequence length
• Balanced Read and Write Latencies in order to optimize data
bus utilization
The GSI Technology 576Mb Low Latency DRAM
(LLDRAM II) is a high speed memory device designed for
high address rate data processing typically found in networking
and telecommunications applications. The 8-bank architecture
and low tRC allows access rates formerly only found in
SRAMs.
The Double Data Rate (DDR) I/O interface provides high
bandwidth data transfers, clocking out two beats of data per
clock cycle at the I/O balls. Source-synchronous clocking can
be implemented on the host device with the provided free-
running data output clock.
• Data mask for Write commands
Commands, addresses, and control signals are single data rate
signals clocked in by the True differential input clock
transition, while input data is clocked in on both crossings of
the input data clock(s).
• Differential input clocks (CK, CK)
• Differential input data clocks (DKx, DKx)
• On-chip DLL generates CK edge-aligned data and output
data clock signals
• Data valid signal (QVLD)
Read and Write data transfers always in short bursts. The burst
length is programmable to 2, 4 or 8 by setting the Mode
Register.
• 32 ms refresh (16K refresh for each bank; 128K refresh
command must be issued in total each 32 ms)
• 144-ball BGA package
• HSTL I/O (1.5 V or 1.8 V nominal)
The device is supplied with 2.5 V V
and 1.8 V V for the
EXT DD
• 25–60 matched impedance outputs
core, and 1.5 V or 1.8 V for the HSTL output drivers.
• 2.5 V V , 1.8 V V , 1.5 V or 1.8 V V I/O
DDQ
EXT
DD
• On-die termination (ODT) R
Internally generated row addresses facilitate bank-scheduled
refresh.
TT
• Commerical and Industrial Temperature
Commercial (+0° T +95°C)
C
The device is delivered in an efficent BGA 144-ball package.
Industrial (–40° T +95°C)
C
Rev: 1.04 11/2013
1/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
64M x 9 Mb Ball Assignments—144-Ball BGA—Top View
1
2
3
4
5
6
7
8
9
10
11
12
V
V
V
V
V
V
EXT
A
B
C
D
E
F
TMS
TCK
REF
SS
DNU
DNU
DNU
DNU
EXT
SS
SS
SS
SS
3
3
3
3
3
3
3
V
V
V
V
DQ0
DNU
DNU
DNU
DNU
DNU
DNU
DD
DD
3
3
3
3
3
V
V
V
V
V
V
DQ1
QK0
DQ2
DQ3
A2
TT
DDQ
DDQ
TT
1
V
V
V
QK0
A22
SS
SS
SS
3
A21
A5
A20
QVLD
A0
DNU
DDQ
DDQ
3
V
V
DNU
A6
DNU
A7
DNU
A1
SS
SS
V
V
G
H
J
A8
DD
DD
V
V
V
V
V
V
B2
A9
A4
A3
SS
SS
SS
SS
2
2
V
V
B0
CK
NF
NF
DD
DD
DD
DD
DD
V
V
V
V
K
L
DK
REF
WE
DK
CS
B1
CK
DD
DD
DD
V
V
V
V
V
V
A14
A11
A13
A10
A19
DM
SS
SS
SS
SS
M
N
P
R
T
A16
A17
A12
DQ4
DQ5
DQ6
DQ7
DQ8
DD
DD
3
3
3
3
3
3
3
V
V
SS
A18
A15
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
SS
3
3
3
3
3
3
3
3
V
V
V
V
DDQ
DDQ
V
V
V
V
SS
SS
SS
SS
V
V
TT
DDQ
DDQ
TT
V
V
V
V
U
DNU
ZQ
DNU
V
DD
SS
SS
SS
SS
DD
V
V
V
V
V
TDO
TDI
REF
EXT
EXT
Notes:
1. Reserved for future use. This pin may be connected to ground.
2. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND.
3. Do not use. This pin may have parasitic characteristics of an I/O. It may be connected to GND.
Rev: 1.04 11/2013
2/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
32M x 18 Ball Assignments—144-Ball BGA—Top View
1
2
3
4
5
6
7
8
9
10
11
12
V
V
V
V
V
V
EXT
A
B
C
D
E
F
TMS
TCK
REF
SS
DNU
DNU
DNU
DNU
EXT
SS
SS
SS
SS
4
4
4
4
4
4
V
V
V
V
DQ0
DQ4
DQ5
DQ6
DNU
DNU
DD
DD
4
V
V
V
V
V
V
DQ1
QK0
DQ2
DQ3
A2
TT
DDQ
DDQ
TT
1
2
V
V
V
QK0
A22
A21
A5
SS
SS
SS
4
A20
QVLD
A0
DQ7
DNU
DDQ
DDQ
4
V
V
DNU
A6
DQ8
A7
DNU
A1
SS
SS
V
V
G
H
J
A8
DD
DD
V
V
V
V
V
V
B2
A9
A4
A3
SS
SS
SS
SS
3
3
V
V
B0
CK
NF
NF
DD
DD
DD
DD
V
V
V
V
K
L
DK
DK
CS
B1
CK
DD
DD
DD
DD
V
V
V
V
V
V
REF
WE
A14
A11
A13
A10
A19
DM
SS
SS
SS
SS
M
N
P
R
T
A16
A17
A12
DD
DD
4
4
4
V
V
SS
A18
A15
DQ9
DNU
DNU
DQ14
DQ15
QK1
DNU
DNU
DNU
DNU
DNU
SS
4
4
4
4
V
V
V
V
DQ10
DQ11
DQ12
DQ13
DDQ
DDQ
V
V
V
V
QK1
SS
SS
SS
SS
4
V
V
DNU
DQ16
DQ17
TT
DDQ
DDQ
TT
4
V
V
V
V
U
DNU
ZQ
DD
SS
SS
SS
SS
DD
V
V
V
V
V
V
TDO
TDI
REF
EXT
EXT
Notes:
1. Reserved for future use. This pin may be connected to GND.
2. Reserved for future use. This pin may have parasitic characteristics of an address input signal. It may be connected to GND.
3. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND.
4. Do not use. This pin may have parasitic characteristics of an I/O. It may be connected to GND.
Rev: 1.04 11/2013
3/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
16M x 36 Ball Assignments—144-Ball BGA—Top View
1
2
3
4
5
6
7
8
9
10
11
12
V
V
V
V
V
V
EXT
A
B
C
D
E
F
TMS
DQ0
DQ2
QK0
TCK
REF
SS
EXT
SS
SS
SS
SS
V
V
V
V
DQ8
DQ9
DQ11
DQ13
DQ15
DQ17
A7
DQ1
DD
DD
V
V
V
V
V
V
DQ10
DQ12
DQ14
DQ16
A6
DQ3
QK0
DQ5
DQ7
A2
TT
DDQ
DDQ
TT
1
2
V
V
V
A22
SS
SS
SS
2
DQ4
DQ6
A1
A21
A5
A20
QVLD
A0
DDQ
DDQ
V
V
SS
SS
V
V
G
H
J
A8
DD
DD
V
V
V
V
V
V
B2
A9
A4
A3
SS
SS
SS
SS
V
V
DK0
DK1
REF
WE
DK0
DK1
CS
B0
CK
DD
DD
DD
DD
DD
DD
V
V
V
V
K
L
B1
CK
DD
DD
V
V
V
V
V
V
A14
A13
A10
A19
SS
SS
SS
SS
M
N
P
R
T
A16
A17
A12
A11
DD
DD
V
V
SS
A18
A15
DQ25
DQ23
QK1
DQ35
DQ33
DQ31
DQ29
DQ27
DQ34
DQ32
DQ30
DQ28
DQ26
TDO
DQ24
DQ22
SS
V
V
DM
DDQ
DDQ
V
V
V
V
QK1
SS
SS
SS
SS
V
V
V
V
DQ20
DQ21
DQ19
TT
DDQ
DDQ
TT
V
V
V
V
U
DQ18
ZQ
DD
SS
SS
SS
SS
DD
V
V
V
V
V
V
TDI
REF
EXT
EXT
Notes:
1. Reserved for future use. This pin may be connected to GND.
2. Reserved for future use. This pin may have parasitic characteristics of an address pin. It may be connected to GND.
Rev: 1.04 11/2013
4/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Ball Descriptions
Symbol
Type
Description
Address Inputs—A0–A21 define the row and column addresses for Read and Write Operations. During
a Mode Register Set (MRS), the address inputs define the register settings. They are sampled at the
rising edge of CK.
A0–A21
Input
BA0–B2
CK, CK
Input
Input
Bank Address inputs—Select to which internal bank a command is being applied.
Input Clock—CK and CK are differential input clocks. Addresses and commands are latched on the
rising edge of CK. CK is ideally 180º out of phase with CK.
Chip Select—CS enables the command decoder when Low and disables it when High. When the
Input
Input
CS
command decoder is disabled, new commands are ignored, but internal operations continue.
Data Input—The DQ signals form the 36-bit data bus. During Read commands, the data is referenced to
DQ0–DQ35
both edges of QKx. During Write commands, the data is sampled at both edges of DK.
Input Data Clock—DK and DK are the differential input data clocks. All input data is referenced to both
edges of DK. DK is ideally 180º out of phase with DK. For the x36 device, DQ0– DQ17 are referenced to
DK0 and DK0 and DQ18–DQ35 are referenced to DK1 and DK1. For the x9 and x18 devices, all DQs
are referenced to DK and DK. All DKx and DKx pins must always be supplied to the device.
Input
Input
DK, DK
DM
Input Data Mask—The DM signal is the input mask signal for Write data. Input data is masked when DM
is sampled High. DM is sampled on both edges of DK (DK1 for the x36 configuration). Tie signal to
ground if not used.
IEEE 1149.1 clock input—This ball must be tied to V if the JTAG function is not used.
TCK
Input
Input
SS
IEEE 1149.1 test inputs—These balls may be left as no connects if the JTAG function is not used.
TMS, TDI
Command Inputs—Sampled at the positive edge of CK, WE and REF define (together with CS) the
Input
Input
WE, REF
command to be executed.
Input Reference Voltage—Nominally V /2. Provides a reference voltage for the input buffers.
V
DDQ
REF
External Impedance (25–60)—This signal is used to tune the device outputs to the system data bus
impedance. DQ output impedance is set to 0.2 * RQ, where RQ is a resistor from this signal to ground.
Connecting ZQ to GND invokes the Minimum Impedance mode. Connecting ZQ to V invokes the
I/O
ZQ
DD
Maximum Impedance mode. Refer to the Mode Register Definition diagrams (Mode Register Bit 8 (M8))
to activate or deactivate this function.
Output Data Clocks—QKx and QKx are opposite polarity, output data clocks. They are free running,
and during Reads, are edge-aligned with data output from the LLDRAM II. QKx is ideally 180º out of
phase with QKx. For the x36 device, QK0 and QK0 are aligned with DQ0–DQ17, and QK1 and QK1 are
aligned with DQ18–DQ35. For the x18 device, QK0 and QK0 are aligned with DQ0–DQ8, while QK1 and
QK1 are aligned with Q9–Q17. For the x9 device, all DQs are aligned with QK0 and QK0.
Output
QKx, QKx
Rev: 1.04 11/2013
5/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Ball Descriptions (Continued)
Symbol
Type
Description
Output
Data Valid—The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and QKx.
QVLD
IEEE 1149.1 Test Output—JTAG output. This ball may be left as no connect if the JTAG function is not
Output
Supply
Supply
TDO
used.
Power Supply—Nominally, 1.8 V. See the DC Electrical Characteristics and Operating Conditions
V
DD
section for range.
DQ Power Supply—Nominally, 1.5 V or 1.8 V. Isolated on the device for improved noise immunity. See
V
DDQ
the DC Electrical Characteristics and Operating Conditions section for range.
Power Supply—Nominally, 2.5 V. See the DC Electrical Characteristics and Operating Conditions
V
Supply
Supply
—
EXT
section for range.
V
Ground
SS
Power Supply—Isolated termination supply. Nominally, V /2. See the DC Electrical Characteristics
DDQ
V
TT
and Operating Conditions section for range.
—
—
—
Reserved for Future Use—This signal is not connected and may be connected to ground.
Do Not Use—These balls may be connected to ground.
A22
DNU
NF
No Function—These balls can be connected to ground.
Rev: 1.04 11/2013
6/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Operations
Initialization
A specific power-up and initialization sequence must be observed. Other sequences may result in undefined operations or
permanent damage to the device.
Power-up:
1. Apply power (VEXT, VDD, VDDQ, VREF, VTT) . Start clock after the supply voltages are stable. Apply VDD and VEXT before or
1
at the same time as VDDQ . Apply VDDQ before or at the same time as VREF and VTT. The chip starts internal initlization
2
only after both voltages approach their nominal levels. CK/CK must meet VID DC prior to being applied . Apply only
(
)
NOP commands to start. Ensuring CK/CK meet VID DC while loading NOP commands guarantees that the LLDRAM II
(
)
will not receive damaging commands during initialization.
2. Idle with continuing NOP commands for 200s (MIN).
3. Issue three or more consecutive MRS commands: two or more dummies plus one valid MRS. The consecutive MRS
commands will reset internal logic of the LLDRAM II. tMRSC does not need to be met between these consecutive
commands. Address pins should be held Low during the dummy MRS commands.
4. tMRSC after the valid MRS, issues an AUTO REFRESH command to all 8 banks in any order (along with 1024 NOP
commands) prior to normal operation. As always, tRC must be met between any AUTO REFRESH and any subsequent
valid command to the same bank.
Notes:
1. It is possible to apply VDDQ before VDD. However, when doing this, the DQs, DM, and all other pins with an output driver, will
go High instead of tri-stating. These pins will remain High until VDD is at the same level as VDDQ. Care should be taken to
avoid bus conflicts during this period.
2. If VID DC on CK/CK can not be met prior to being applied to the LLDRAM II, placing a large external resistor from CS to VDD
(
)
is a viable option for ensuring the command bus does not receive unwanted commands during this unspecified state.
Rev: 1.04 11/2013
7/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Power–Up Initialization Sequence
VEXT
VDD
VDDQ
VREF
VTT
Refresh
All Banks(5)
200us Min
Mode Initialization
tMRSC
1024 Cycles NOP Cycles Min
tCK
tDK
tCKH
tDKH
tCKL
tDKL
CK
CK
DK
DK
Command
ADDR
BA
NOP
NOP
MRS
MRS
MRS
NOP
AREF
AREF
NOP
AC
CODE(1,2)
CODE(1,2)
CODE(2)
ADDR
Valid
Bank 0
Bank 7
DM
DQ
Notes:
1. Recommend all address pins held Low during dummy MRS commands.
2. A10–A17 must be Low.
3. DLL must be reset if tCK or VDD are changed.
4. CK and CK must be separated at all times to prevent bogus commands from being issued.
5. The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP commands) does not matter. As is required for any operation,
tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank.
Rev: 1.04 11/2013
8/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Power–Up Initialization Flow Chart
Step
VDD and VEXT ramp
VDDQ ramp
1
2
Voltage rails can
be applied
simultaneously
Apply VREF and VTT
3
4
Apply stable CK/CK and DK/DK
Wait at least 200s
5
6
Issue MRS command—A10–A17 must be Low
Issue MRS command—A10–A17 must be Low
Desired load mode register with A10–A17 Low
Assert NOP for tMRSC
MRS commands
must be on
consecutive
clock cycles
7
8
9
10
11
12
13
14
15
16
17
18
19
Issue AUTO REFRESH to bank 0
Issue AUTO REFRESH to bank 1
Issue AUTO REFRESH to bank 2
Issue AUTO REFRESH to bank 3
Issue AUTO REFRESH to bank 4
Issue AUTO REFRESH to bank 5
Issue AUTO REFRESH to bank 6
Issue AUTO REFRESH to bank 7
Wait 1024 NOP commands*
Valid command
*Note:
The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP commands) does not matter. As is required for any
operation, tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank.
Rev: 1.04 11/2013
9/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
DLL Reset
Mode Register Bit 7 (M7) selects DLL Reset as is shown in the Mode Register Definition tables. The default setting for M7 is Low,
whereby the DLL is disabled. Once M7 is set High, 1024 cycles (5s at 200 MHz) are needed before a Read command can be
issued. The delay allows the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur
may result in a violation of the tCKQK parameter. A reset of the DLL is necessary if tCK or VDD is changed after the DLL has
already been enabled. To reset the DLL, set M7 is Low. After waiting tMRSC, an MRS command should be issued to set M7 High.
1024 clock cycles must pass before loading the next Read command.
Driver Impedance Mapping
The LLDRAM II is equipped with programmable impedance output buffers. Setting Mode Register Bit 8 (M8) High during the
MRS command activates the feature. Programmable impedance output buffers allow the user to match the driver impedance to the
PCB trace impedance. To adjust the impedance, an external resistor (RQ) is connected between the ZQ ball and VSS. The value of
the resistor must be five times the desired impedance (e.g., a 300 resistor produces an output impedance of 60). RQ values of
125–300 are supported, allowing an output impedance range of 25–60 (+/- 15 %).
The drive impedance of uncompensated output transistors can change over time due to changes in supply voltage and die
temperature. When drive impedance control is enabled in the MRS, the value of RQ is periodically sampled and any needed
impedance update is made automatically. Updates do not affect normal device operation or signal timing.
When Bit M8 is set Low during the MRS command, the output compensation circuits are still active but reference an internal
resistance reference. The internal reference is imprecise and subject to temperature and voltage variations so output buffers are set
to a nominal output impedance of 50, but are subject to a ±30 percent variance over the Commercial temperature range of the
device.
Rev: 1.04 11/2013
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
On–Die Termination (ODT)
Mode Register Bit 9 (M9) set to 1 during an MRS command enables ODT. With ODT on, the DQs and DM are terminated to VTT
with a resistance, RTT. Command, address, QVLD, and clock signals are not terminated. The diagram below shows the equivalent
circuit of a DQ receiver with ODT. When a tri-stated DQ begins to drive, the ODT function is briefly switched off. When a DQ
stops driving at the end of a data transfer, ODT is switched back on. Two-state DM pin never deactivates ODT.
On–Die Termination DC Parameters
Description
Symbol
Min
Max
Units
V
Notes
1, 2
3
V
0.95 * V
1.05 * V
REF
Termination Voltage
On–Die Termination
TT
REF
R
125
185
TT
Notes:
1. All voltages referenced to V (GND).
SS
2.
V
is expected to be set equal to V
and must track variations in the DC level of V
.
REF
TT
REF
3. The R value is measured at 95°C T .
TT
C
On–Die Termination–Equivalent Circuit
VTT
SW
RTT
Receiver
DQ
VREF
Rev: 1.04 11/2013
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Read NOP Read On-Die Termination Burst Length 2, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
CK
CMD
ADDR
BA
RD
A
NOP
RD
A
NOP
NOP
NOP
NOP
NOP
NOP
BA0
BA2
RL = 4
QKx
QKx
QVLD
DQ
Q0a
Q0b
Q2a
Q2b
ODT
ODT ON
ODT OFF
ODT ON
ODT OFF
ODT ON
Read-Write On-Die Termination Burst Length 2, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
CK
CMD
ADDR
BA
RD
A
WT
A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
BA0
BA1
WL = 5
DK
DK
DQ
Q0a
Q0b
D1a
D1b
RL = 4
QKx
QKx
QVLD
ODT
ODT ON
ODT OFF
ODT ON
Rev: 1.04 11/2013
12/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Read Burst On-die Termination Burst Length 2, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
CK
CMD
ADDR
BA
RD
A
RD
A
RD
A
NOP
NOP
NOP
NOP
NOP
NOP
BA0
BA1
BA2
RL = 4
QKx
QKx
QVLD
DQ
Q0a
Q0b
Q1a
Q1b
Q2a
Q2b
ODT
ODT ON
ODT OFF
ODT ON
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GS4576C09/18/36L
Commands
Valid control commands are listed below. Any input commands not shown are illegal or reserved. All inputs must meet specified
setup and hold times around the true crossing of CK.
Description of Commands
Command
Description
Notes
The NOP command is used to perform a no operation to the LLDRAM II, which essentially deselects the
chip. Use the NOP command to prevent unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected. Output values depend on command history.
DSEL/NOP
1
The Mode Register is set via the address inputs A0–A17. See the Mode Register Definition diagrams for
further information. The MRS command can only be issued when all banks are idle and no bursts are in
progress.
MRS
—
2
The Read command is used to initiate a burst read access to a bank. The value on the BA0–BA2 inputs
selects the bank, and the address provided on inputs A0–An selects the data location within the bank.
READ
The Write command is used to initiate a burst write access to a bank. The value on the BA0–BA2 inputs
selects the bank, and the address provided on inputs A0–An selects the data location within the bank.
Input data appearing on the DQ is written to the memory array subject to the DM input logic level
appearing coincident with the data. If the DM signal is registered Low, the corresponding data will be
written to memory. If the DM signal is registered High, the corresponding data inputs will be ignored (that
is, this part of the data word will not be written).
WRITE
AREF
2
The AREF command is used during normal operation of the LLDRAM II to refresh the memory content
of a bank. The command is non-persistent, so it must be issued each time a refresh is required. The
value on the BA0–BA2 inputs selects the bank. The refresh address is generated by an internal refresh
controller, effectively making each address bit a “Don’t Care” during the AREF command.
See the Auto Refresh section for more details.
—
Notes:
1. When the chip is deselected, internal NOP commands are generated and no commands are accepted.
2. For the value of “n”, see Address Widths at Different Burst Lengths table.
Command Table
Operation
Command
CS
WE
REF
BA0–BA2
A0–An
Device Deselect/No Operation
DSEL/NOP
MRS
H
L
L
L
L
X
L
X
L
X
X
1
MRS
Read
CODE
X
1, 3
1, 2
1, 2
1
READ
H
L
H
H
L
A
A
X
BA
BA
BA
Write
WRITE
AREF
Auto Refresh
H
Notes:
1. X= Don’t Care; H = Logic High; L = Logic Low; A = Valid Address; BA = Valid Bank Address.
2. For the value of “n”, see Address Widths at Different Burst Lengths table.
3. Only A0–A17 are used for the MRS command.
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GS4576C09/18/36L
State Diagram
Initialization
Sequence
DSEL/
NOP
Write
Read
AREF
MRS
Notes:
Automatic Sequence
Command Sequence
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GS4576C09/18/36L
Mode Register Set
Mode Register Set controls the operating modes of the memory, including configuration, burst length, test mode, and I/O options.
During an MRS command, the address inputs A0–A17 are sampled and stored in the Mode Register. Except during initialization to
force internal reset, after a valid MRS command, tMRSC must be met before any command except NOP can be issued to the
LLDRAM II. All banks must be idle and no bursts may be in progress when an MRS command is loaded.
Note: Changing the burst length configuration may scramble previously written data. A burst length change must be assumed to
invalidate all stored data.
Mode Register Set
CK
CK
CS
WE
REF
Addr
CODE
BA(2:0)
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GS4576C09/18/36L
Mode Register Definition in Nonmultiplexed Address Mode
Address Bus
A17 ... A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A0
17–10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
1
2
Reserved
ODT IM DLL NA AM
BL
Config
M2 M1 M0
Configuration
On Die
M9
Termination
3
0
0
0
1 (default)
0
1
Off (default)
On
3
0
0
0
1
0
1
1
0
1
0
1
0
1
2
3
M8
Drive Impedance
M7
DLL Reset
3
4
5
0
1
Internal 50 (default)
4
0
1
DLL reset (default)
1
1
1
0
1
1
1
0
1
5
External (ZQ)
DLL enabled
Reserved
Reserved
M5
0
Address MUX
Nonmulitplexed (default)
Multiplexed
Burst
Length
M4
M3
0
0
1
1
0
1
0
1
2 (default)
1
4
8
Reserved
Notes:
1. A10–A17 must be set to zero; A18–An = “Don’t Care”.
2. A6 not used in MRS.
3. BL = 8 is not available.
4. DLL RESET turns the DLL off.
5. +/–30% over rated temperature range.
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GS4576C09/18/36L
Configuration Tables
The relationship between cycle time and read/write latency is selected by the user. The configuration table below lists valid
configurations available via Mode Register bits M0, M1, and M2 and the clock frequencies supported for each setting. Write
Latency is equal to the Read Latency plus one in each configuration to reduce bus conflicts.
Cycle Time and Read/Write Latency Configuration Table
Configuration
Parameter
Units
2
2, 3
2
3
5
1
4
tRC
4
6
8
3
3
4
5
tCK
tCK
tCK
MHz
tRL
tWL
4
5
6
7
8
9
5
6
Valid Frequency Range
266–175
400–175
533–175
200–175
333–175
Notes:
1. tRC < 20 ns in any configuration is only available with –18 and –24 speed grades.
2. BL= 8 is not available.
3. The minimum tRC is typically 3 cycles, except in the case of a Write followed by a Read to the same bank. In this instance the minimum
tRC is 4 cycles.
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GS4576C09/18/36L
Burst Length
Read and Write data transfers occur in bursts of 2, 4, or 8 beats. Burst Length is programmed by the user via Mode Register Bit 3
(M3) and Bit 4 (M4). The Read Burst Length diagrams illustrate the different burst lengths with respect to a Read Command.
Changes in the burst length affect the width of the address bus.
Note: Changing the burst length configuration may scramble previously written data. A burst length change must be assumed to
invalidate all stored data.
Read Burst Lengths
Example BL=2
CK
CK
Command
READ
READ
READ
RL = 5
RL = 5
RL = 5
QKx
QKx
QVLD
DQ
Q0
Q1
Example BL=4
CK1
CK1
Command1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
QKx1
QKx1
QVLD1
DQ1
Q0
Q1
Q2
Q3
Example BL=8
CK2
CK2
Command2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
QKx2
QKx2
QVLD2
DQ2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Address Widths at Different Burst Lengths
Configuration
x 18
Burst Length
x 9
x36
2
4
8
A0–A21
A0–A20
A0–A19
A0–A20
A0–A19
A0–A18
A0–A19
A0–A18
A0–A17
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GS4576C09/18/36L
Write
Write data transfers are launched with a Write command, as shown below. A valid address must be provided during the Write
command.
During Write data transfers, each beat of incoming data is registered on crossings of DK and DK until the burst transfer is
complete. Write Latency (WL) that is always one cycle longer than the programmed Read Latency (RL), so the first valid data
registered at the first True crossing of the DK clocks WL cycles after the Write command.
A Write burst may be followed by a Read command (assuming tRC is met). At least one NOP command is required between Write
and Read commands to avoid data bus contention. The Write-to-Read timing diagrams illustrate the timing requirements for a
Write followed by a Read. Setup and hold times for incoming DQ relative to the DK edges are specified as tDS and tDH. Input
data may be masked a High on an associated DM pin. The setup and hold times for the DM signal are tDS and tDH.W
Write Command
CK
CK
CS
WE
REF
Addr
A
BA(2:0)
BA
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GS4576C09/18/36L
Write Burst Length 2, Configuration 1
T0
T1
T2
RC = 4
T3
T4
T5
T6
T7
T8
CK
CK
CMD
ADDR
BA
WR
A
WR
A
WR
A
WR
A
WR
A
WR
A
WR
A
WR
A
WR
A
BA0
BA1
BA2
BA3
BA0
BA4
BA5
BA6
BA7
WL=5
DK
DK
DM
DQ
D0a
D0b
D1a
D1b
D2a
D2b
D3a
D3b
Write Burst Length 4, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
RC = 4
CK
CK
CMD
ADDR
BA
WR
A
NOP
WR
A
NOP
WR
NOP
WR
A
NOP
WR
A
A
BA0
BA1
BA0
BA3
BA0
WL = 5
DK
DK
DM
DQ
D0a
D0b
D0c
D0d
D1a
D1b
D1c
D1d
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GS4576C09/18/36L
Write-Read Burst Length 2, Configuration 1
0
1
2
3
4
5
6
7
8
9
RL = 4
CK
CK
CMD
ADDR
BA
WR
A
NOP
RD
A
RD
A
NOP
NOP
NOP
NOP
NOP
NOP
BA0
BA1
BA2
WL = 5
DK
DK
DM
DQ
D0a
D0b
Q1a
Q1b
Q2a
Q2b
QVLD
QKx
QKx
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GS4576C09/18/36L
Write-Read Burst Length 4, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
RL = 4
CK
CK
CMD
ADDR
BA
WR
A
NOP
NOP
RD
A
NOP
RD
A
NOP
NOP
NOP
NOP
BA0
BA1
BA2
WL = 5
DK
DK
DM
DQ
D0a
D0b
D0c
D0d
Q1a
Q1b
Q1c
Q1d
Q2a
QVLD
QKx
QKx
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GS4576C09/18/36L
Read
Read data transfers are launched with a Read command, as shown below. Read Addresses must provided with the Read command.
Each beat of a Read data transfer is edge-aligned with the QKx signals. After a programmable Read Latency, data is available at the
outputs. One half clock cycle prior to valid data on the read bus, the data valid signal (QVLD) is driven High. QVLD is also edge-
aligned with the QKx signals. The QK clocks are free-running.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the skew between QK0 and the last valid data
edge generated at the DQ signals associated with QK0 (tQKQ0 is referenced to DQ0–DQ17 for the x36 configuration and DQ0–DQ8
for the x18 configuration). tQKQ1 is the skew between QK1 and the last valid data edge generated at the DQ signals associated with
QK1 (tQKQ1 is referenced to DQ18–DQ35 for the x36 and DQ9–DQ17 for the x18 configuration). tQKQx is derived at each QKx
clock edge and is not cumulative over time. tQKQ is defined as the skew between either QK differential pair and any output data edge.
At the end of a burst transfer, assuming no other commands have been initiated, output data (DQ) will go High-Z. The QVLD signal
transitions Low on the beat of a Read burst. Note that if CK/CK violates the V
specification while a Read burst is occurring,
ID(DC)
QVLD remains High until a dummy Read command is issued. Back-to-back Read commands are possible, producing a continuous
flow of output data.
The data valid window specification is referenced to QK transitions and is defined as: tQHP – (tQKQ [MAX] + |tQKQ [MIN]|). See the
Read Data Valid Window section for illustration.
Any Read transfer may be followed by a subsequent Write command. The Read-to-Write timing diagram illustrates the timing
requirements for a Read followed by a Write. Some systems having long line lengths or severe skews may need additional NOP cycles
inserted between Read and Write commands to prevent data bus contention.
Read Command
CK
CK
CS
WE
REF
Addr
A
BA(2:0)
BA
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GS4576C09/18/36L
Read Burst Length 2, Configuration 1
T0
T1
T2
RC = 4
T3
T4
T5
T6
T7
T8
CK
CK
CMD
ADDR
BA
RD
A
RD
A
RD
A
RD
A
RD
A
RD
A
RD
A
RD
A
RD
A
BA0
BA1
BA2
BA3
BA0
BA7
BA6
BA5
BA4
RL = 4
QKx
QKx
QVLD
DQ
Q0a
Q0b
Q1a
Q1b
Q2a
Q2b
Q3a
Q3b
Q0a
Read Burst Length 4, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
RC = 4
CK
CK
CMD
ADDR
BA
RD
A
NOP
RD
A
NOP
RD
A
NOP
RD
A
NOP
RD
A
BA0
BA1
BA0
BA1
BA3
RL = 4
QKx
QKx
QVLD
DQ
Q0a
Q0b
Q0c
Q0d
Q1a
Q1b
Q1c
Q1d
Q0a
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GS4576C09/18/36L
Read-Write Burst Length 2, Configuration 1
T0
T1
T2
T3
T4
T5
T6
T7
CK
CK
CMD
ADDR
BA
RD
A
WR
A
WR
A
NOP
NOP
NOP
NOP
NOP
D2a
T7
BA0
BA1
BA2
WL = 5
DK
DK
DM
DQ
Q0a
Q0b
D1a
D1b
D2b
QVLD
RL = 4
QKx
QKx
Read-Write Burst Length 4, Configuration 1
T0
T1
T2
T3
T4
T5
T6
CK
CK
CMD
ADDR
BA
RD
A
NOP
WR
A
NOP
NOP
NOP
NOP
NOP
BA0
BA1
WL = 5
DK
DK
DM
DQ
Q0a
Q0b
Q0c
Q0d
D1a
D1b
QVLD
RL = 4
QKx
QKx
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GS4576C09/18/36L
Auto Refresh
The Auto Refresh (AREF) command launches a REFRESH cycle on one row in the bank addressed. Refresh row addresses are
generated by an internal refresh counter, so address inputs are Don’t Care, but a bank addresses (BA 2:0) must be provided during
the AREF command. A refresh may be contining in one bank while other commands, including other AREF commands, are
launched in other banks. The delay between the AREF command and a READ, WRITE or AREF command to the same bank must
be at least tRC.
The entire memory must be refreshed every 32 ms (tREF). This means that this 576Mb device requires 128K refresh cycles at an
average periodic interval of 0.24s MAX (actual periodic refresh interval is 32 ms/16K rows/8 = 0.244s). To improve efficiency,
eight AREF commands (one for each bank) can be launched at periodic intervals of 1.95s (32 ms/16K rows = 1.95s). The Auto
Refresh Cycle diagram illustrates an example of a refresh sequence.
Auto Refresh (AREF) Command
CK
CK
CS
WE
REF
A(20:0)
BA(2:0)
BA
Auto Refresh Cycle
CK
CK
CMD
Bank
AREF
BA0
AREF
NOP
AREF
BA4
BA3
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GS4576C09/18/36L
Address Multiplexing
LLDRAM II defaults to “broadside” addressing at power up, meaning, it registers all address inputs on a single clock transition.
However, for most configurations of the device, considerable efficiency can be gained by operating in Address Multiplexed mode,
cutting the address pin count on the host device in half. In Multiplexed Address mode, the address is loaded in two consecutive
clock transitions. Broadside Addressing only improves Continuous Burst mode data transfer efficiency of Burst Length 2 (BL = 2)
configuration.
In Address Multiplex mode, bank addresses are loaded on the same clock transition as Command and the first half of the address,
Ax. The 576Mb Address Mapping in Multiplexed Address Mode table and Cycle Time and Read/Write Latency Configuration in
Mulitplexed Mode table show the addresses needed for both the first and second clock transitions (Ax and Ay, respectively). The
AREF command does not require an address on the second clock transition, as only the Bank Address are loaded for refresh
commands. Therefore, AREF commands may be issued on consecutive clocks, even when in Address Multiplex mode.
Setting Mode Register Bit 5 (M5) to 1 in the Mode Register activates the Multiplexed Address mode. Once this bit is set
subsequent MRS, READ, and WRITE operate as described in the Multiplexed Address Mode diagram.
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GS4576C09/18/36L
Power-Up Multiplexed Address Mode
VEXT
VDD
VDDQ
VREF
VTT
200us Min
tMRSC
tMRSC
Refresh All Banks(9) 1024 NOP cycles Min
tCK
tCKL
tCKH
CK
CK
tDK
tDKH
tDKL
DK
DK
Command
ADDR
NOP
NOP
MRS
MRS
MRS
NOP
MRS
NOP
REF
REF
NOP
AC
CODE(1,2)
CODE(1,2)
CODE(2,3)
Ax(2,4)
Ay(2)
Valid(5)
Valid(5)
Bank
Bank 0
Bank 7
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GS4576C09/18/36L
MRS Command In Multiplexed Mode
The Mode Register Set command stores the data for controlling the RAM into the Mode Register. The register allows the user to
modify Read and Write pipeline length, burst length, test mode, and I/O options. The Multiplexed MRS command requires two
cycles to complete The Ax address is sampled on the true crossing of clock with the MRS Command. The Ay address and a
required NOP command are captured on the next next crossing of clock. After issuing a valid MRS command, tMRSC must be met
before any READ, WRITE, MRS, or AREF command can be issued to the LLDRAM II. This statement does not apply to the
consecutive MRS commands needed for internal logic reset during the initialization routine. The MRS command can only be
issued when all banks are idle and no bursts are in progress.
Note: The data written by the prior burst length is not guaranteed to be accurate when the burst length of the device is changed.
MRS Command in Multiplexed Mode
MRS
CK
CK
CS
WE
REF
A(20:0)
BA(2:0)
Ax
Ay
Notes:
1. Recommended that all address pins held Low during dummy MRS commands.
2. A10–A18 must be Low.
3. Set address A5 High. This enbles the part to enter Multiplexed Address mode when in Non-Multiplexed mode operation. Multiplexed
Address mode can also be entered at some later time by issuing an MRS command with A5 High. Once address Bit A5 is set High, tMRSC
must be satisfied before the two-cycle multiplexed mode MRS command is issued.
4. Address A5 must be set High. This and the following step set the desired mode register once the LLDRAM II is in Multiplexed Address
mode.
5. Any command or address.
6. The above sequence must be followed in order to power up the LLDRAM II in the Multiplexed Address mode.
7. DLL must be reset if tCK or V are changed.
DD
8. CK and CK must separated at all times to prevent bogus commands from being issued.
9. The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP commands) does not matter. As is required for any
operation, tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank.
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GS4576C09/18/36L
Mode Register Definition in Multiplexed Address Mode
Ax
Ay
A18...A10
A18...A10
A9 A8
A5 A4 A3
A0
A9 A8
A4 A3
18–10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
1
5
Reserved
ODT IM DLL NA AM
BL
Config
M2 M1 M0
Configuration
On Die
M9
Termination
2
0
0
0
1 (default)
0
1
Off (default)
On
2
0
0
0
1
0
1
1
0
1
0
1
0
1
2
3
M8
Drive Impedance
M7
DLL Reset
2
4
3
0
1
Internal 50 (default)
4
0
1
DLL reset (default)
1
1
1
0
1
1
1
0
1
5
External (ZQ)
DLL enabled
Reserved
Reserved
M5
0
Address MUX
Nonmulitplexed (default)
Multiplexed
Burst
Length
M4
M3
0
0
1
1
0
1
0
1
2 (default)
1
4
8
Reserved
Notes:
1. A10–A18 must be set to zero.
2. BL = 8 is not available.
3. +/–30% over rated temperature range.
4. DLL RESET turns the DLL off.
5. Ay8 not used in MRS.
6. BA0–BA2 are “Don’t Care”.
7. Addresses A0, A3, A4, A5, A8, and A9 must be set as shown in order to activate the Mode Register in the Multiplexed Address mode.
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GS4576C09/18/36L
576Mb Address Mapping in Multiplexed Address Mode
Address
A9
A9
Burst
Length
Data Width
Ball
A0
A0
X
A3
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A4
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A5
A5
X
A8
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A10
A10
A19
A10
X
A13
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A14
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A17
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A18
A18
A15
A18
A15
X
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
2
A7
A0
X
A5
X
A9
x36
4
8
2
4
8
2
4
8
A7
A0
X
A5
X
A9
A10
X
A7
A15
A18
A15
A18
A15
A18
A15
A18
A15
A18
A15
A18
A15
A0
A20
A0
X
A5
X
A9
A10
A19
A10
A19
A10
X
A7
A5
X
A9
x18
A7
A0
X
A5
X
A9
A7
A0
A20
A0
A20
A0
X
A5
A21
A5
X
A9
A10
A19
A10
A19
A10
A19
A7
A9
x9
A7
A5
X
A9
A7
Notes:
X= Don’t Care.
Configuration in Mulitplexed Mode
In Multiplexed Address mode, the Read and Write latencies are increased by one clock cycle. However, the LLDRAM II cycle time
remains the same as when in Nonmultiplexed Address mode.
Cycle Time and Read/Write Latency Configuration in Mulitplexed Mode
Configuration
Parameter
Units
2
2, 3
2
3
5
1
4
tRC
4
6
8
3
4
5
5
tCK
tCK
tCK
MHz
tRL
tWL
5
6
7
8
9
10
6
7
Valid Frequency Range
266–175
400–175
533–175
200–175
333–175
Notes:
1. tRC < 20 ns in any configuration is only available with –24 and –18 speed grades.
2. Minimum operating frequency for –18 is 370 MHz.
3. The minimum tRC is typically 3 cycles, except in the case of a Write followed by a Read to the same bank. In this instance the minimum
tRC is 4 cycles.
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GS4576C09/18/36L
Write Command in Multiplexed Mode
Address Multiplexed Write data transfers are launched with a Write command, as shown below. A valid address must be provided
during the Write command. The Ax address must be loaded on the same true clock crossing used to load the Write command and
the Bank address. The Ay address and a NOP command must be provided at the next clock crossing.
During Write data transfers, each beat of incoming data is registered on crossings of DK and DK until the burst transfer is
complete. Write Latency (WL) is always one cycle longer than the programmed Read Latency (RL).
A Write burst may be followed by a Read command (assuming tRC is met). At least one NOP command is required between Write
and Read commands to avoid data bus contention. The Write-to-Read timing diagrams illustrate the timing requirements for a
Write followed by a Read. Setup and hold times for incoming DQ relative to the DK edges are specified as tDS and tDH. Input data
may be masked high on an associated DM pin. The setup and hold times for the DM signal are tDS and tDH.
Write Command in Multiplexed Mode
WRITE
CK
CK
CS
WE
REF
A(20:0)
BA(2:0)
Ax
Ay
BA
Write Burst Length 4, Configuration 1 in Multiplexed Mode
T0
T1
T2
RC = 4
T3
T4
T5
T6
T7
T8
CK
CK
CMD
ADDR
BA
WR
NOP
WR
Ax
NOP
WR
NOP
WR
NOP
WR
Ax
Ay
Ay
Ax
Ay
Ax
Ay
Ax
BA0
BA1
BA0
BA3
BA0
WL = 6
DK
DK
DM
D
D0a
D0b
D0c
D0d
D1a
D1b
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GS4576C09/18/36L
Read Command in Multiplexed Mode
Address Multiplexed Read data transfers are launched with a Read command, as shown below. A valid address must be provided
during the READ command. The Ax address must be loaded on the same True clock crossing used to load the READ command
and the Bank address. The Ay address and a NOP command must be provided at the next clock crossing.
Each beat of a Read data transfer is edge-aligned with the QKx signals. After a programmable Read Latency, data is available at
the outputs. One half clock cycle prior to valid data on the read bus, the data valid signal (QVLD) is driven High. QVLD is also
edge-aligned with the QKx signals. The QK clocks are free-running.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the skew between QK0 and the last valid
data edge generated at the DQ signals associated with QK0 (tQKQ0 is referenced to DQ0–DQ17 for the x36 configuration and
DQ0–DQ8 for the x18 configuration). tQKQ1 is the skew between QK1 and the last valid data edge generated at the DQ signals
associated with QK1 (tQKQ1 is referenced to DQ18–DQ35 for the x36 and DQ9–DQ17 for the x18 configuration). tQKQx is
derived at each QKx clock edge and is not cumulative over time. tQKQ is defined as the skew between either QK differential pair
and any output data edge.
At the end of a burst transfer, assuming no other commands have been initiated, output data (DQ) will go High–Z. The QVLD
signal transitions Low on the beat of a Read burst. Note that if CK/CK violates the V
specification while a Read burst is
ID(DC)
occurring, QVLD remains High until a dummy Read command is issued. Back-to-back Read commands are possible, producing a
continuous flow of output data.
The data valid window specification is referenced to QK transitions and is defined as: tQHP – (tQKQ [MAX] + |tQKQ [MIN]|). See
the Read Data Valid Window section.
Any Read transfer may be followed by a subsequent Write command. The Read-to-Write timing diagram illustrates the timing
requirements for a Read followed by a Write. Some systems having long line lengths or severe skews may need additional NOP
cycles inserted between Read and Write commands to prevent data bus contention.
Read Command in Mulitplexed Mode
READ
CK
CK
CS
WE
REF
A(20:0)
BA(2:0)
Ax
Ay
BA
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GS4576C09/18/36L
Read Burst Length 4, Configuration 1 in Multiplexed Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
RC = 4
CK
CK
CMD
ADDR
BA
RD
NOP
RD
NOP
RD
NOP
RD
NOP
RD
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
BA0
BA1
BA2
BA0
BA1
RL = 5
QKx
QKx
QVLD
Q
Q0a
Q0b
Q0c
Q0d
Q1a
Q1b
Q1c
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GS4576C09/18/36L
Refresh Commands in Multiplexed Address Mode
The AREF command launches a REFRESH cycle on one row in the bank addressed. Refresh row addresses are generated by an
internal refresh counter. so address inputs are Don’t Care, but Bank addresses (BA 2:0) must be provided during the AREF
command. A refresh may be continuing in one bank while other commands, including other AREF commands, are launched in
other banks. The delay between the AREF command and a READ, WRITE or AREF command to the same bank must be at least
tRC.
The entire memory must be refreshed every 32 ms (tREF). This means that this 576Mb device requires 128K refresh cycles at an
average periodic interval of 0.24s MAX (actual periodic refresh interval is 32 ms/16K rows/8 = 0.244s). To improve efficiency,
eight AREF commands (one for each bank) can be launched at periodic intervals of 1.95s (32 ms/16K rows = 1.95s). The Auto
Refresh Cycle diagram illustrates an example of a refresh sequence.
Unlike READ and WRITE commands in Address Multiplex mode, all the information needed to execute an AREF command (the
AREF command and the Band Address (BA 2:0)) is loaded in a single clock crossing, another AREF command (to a different
bank) may be loaded on the next clock crossing.
Consecutive Refresh Operations with Multiplexed Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
CK
CMD
ADDR
BA
AC
Ax
NOP
AREF
AREF
AREF
AREF
AREF
AREF
AREF
AREF
AC
Ax
NOP
Ay
Ay
BAn
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
BAn
Notes:
1. Any command.
2. Bank n is chosen so that tRC is met.
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GS4576C09/18/36L
Absolute Maximum Ratings
Absolute Maximum Voltage
(All voltages reference to V
)
SS
Parameter
Min
–0.3
–0.3
–0.3
–0.3
Max
+ 0.3
Unit
V
V
I/O Voltage
DDQ
Voltage on V supply
+2.8
+2.1
+2.1
V
EXT
Voltage on V supply relative to V
V
DD
SS
Voltage on V
supply relative to V
SS
V
DDQ
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Absolute Maximum Temperature
Temperature
Parameter
Symbol
Min.
Max.
Unit
Notes
Range
T
Storage Temperature
—
–55
—
+150
+110
+110
C°
C°
C°
1
2
2
STG
Commercial
Industrial
T
Reliability junction temperature
J
—
Notes:
1. Max storage case temperature; T
is measured in the center of the package.
STG
2. Temperatures greater than 110 C° may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at or above this is not implied. Exposure to the absolute maximum ratings condtions for extended periods may affect reliability of
the part.
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GS4576C09/18/36L
Recommended Operating Temperature and Thermal Impedance
Like any other semiconcuctor device, the LLDRAM II must be operated within the temperature specifications shown in the
Temperature Limits table for the device to meet datasheet specifications. The thermal impedance characteristics of the device are
are listed below. In applications where the ambient temperature or PCB temperature are too high, use of forced air and/or heat
sinks may be required in order to satisfy the case temperature specifications.
Temperature Limits
Temperature
Parameter
Symbol
Min.
Max.
Unit
Notes
Range
Commercial
Industrial
0
+100
+100
+95
C°
C°
C°
C°
1
1
T
Operating junction temperature
J
–40
0
Commercial
Industrial
2, 3
2, 3, 4
T
Operating case temperature
C
–40
+95
Notes:
1. Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow.
2. Maximum operating case temperature, T , is measured in the center of the package.
C
3. Device functionality is not guaranteed if the device exceeds maximum T during operation.
C
4. Junction and case temperature specifications must be satisfied.
Thermal Impedance
Test PCB
Substrate
JA (C°/W)
Airflow = 0 m/s
JA (C°/W)
Airflow = 1 m/s
JA (C°/W)
Airflow = 2 m/s
JB (C°/W)
JC (C°/W)
Package
2-layer
4-layer
TBD
22.4
TBD
19.0
TBD
16.2
TBD
5.3
TBD
1.7
BGA
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. The minimal metalization of a 2-layer
board tends to minimize the utility of the junction-to-board heat path. The 4-layer test fixture PCB is intended to highlight the effect of
connection to power planes typically found in the PCBs used in most applications. Be advised that a good thermal path to the PCB can
result in cooling or heating of the RAM depending on PCB temperature.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Recommended DC Operating Conditions and Electrical Characteristics
Description
Supply Voltage
Conditions
Symbol
Min.
2.38
Max.
2.63
1.9
Unit
V
Notes
V
—
—
EXT
V
Supply Voltage
—
1.7
V
2
2, 3
4, 5, 6
7, 8
2
DD
V
V
Isolated Output Buffer Supply
Reference Voltage
—
1.4
V
DDQ
DD
V
0.49 * V
0.51 * V
DDQ
—
V
REF
DDQ
V
0.95 * V
1.05 * V
REF
Termination Voltage
—
V
TT
REF
V
V
+ 0.1
V
DDQ
+ 0.3
– 0.1
Input High (logic 1) voltage
Input Low (logic 0) voltage
Ouput High Current
—
V
IH(DC)
REF
V
V
– 0.3
V
REF
—
V
2
IL(DC)
SS
V
V
= V /2
I
(V /2)/(1.15 * RQ/5)
(V /2)/(0.85 * RQ/5)
A
9, 10, 11
9, 10, 11
—
OUT
OUT
DDQ
OH
DDQ
DDQ
= V /2
I
(V /2)/(1.15 * RQ/5)
(V /2)/(0.85 * RQ/5)
Ouput Low Current
A
DDQ
OL
DDQ
DDQ
0 V V V
I
Clock Input Leakage Current
Input Leakage Current
Output Leakage Current
Reference Voltage Current
–5
–5
–5
–5
5
5
5
5
A
A
A
A
IN
DD
DD
LC
0 V V V
I
—
IN
LI
0 V V V
I
—
IN
DDQ
LO
I
—
—
REF
Notes:
1. All voltages referenced to V (GND). This note applies to the entire table.
SS
2. Overshoot V
V + 0.7 V for t tCK/2. Undershoot: V
–0.5 V for t tCK/2. During normal operation V
must not exceed
DDQ
IH(AC)
DD
IL(AC)
V
V
. Control input signals may not have pulse widthts less than tCK/2 or operate at frequencies exceeding tCK (MAX).
DD
3.
can be set to a nominal 1.5 V ± 0.1 V or 1.8 V ± 0.1 V supply.
DDQ
4. Typically the value of V
is expected to be 0.5 * V
of the transmitting device. V
is expected to track variations in V
.
DDQ
REF
DDQ
REF
5. Peak-to-Peak AC noise on V
must not exceed ±2% of V
.
REF
REF(DC)
6.
V
is expected to equal V /2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise
REF DDQ
(non-common mode) on V
may not exceed ±2% of the DC value. Thus, from V /2, V
is allowed ±2% V /2 for DC error and an
REF DDQ
REF
DDQ
addtional ±2% V /2 for AC noise. This measurement is to be taken at the nearest V
bypass capacitor.
REF
DDQ
7.
V
is expected to be set equal to V
and must track variations in the DC level of V
.
REF
TT
REF
8. On-die termination may be selected using Mode Register Bit 9 (M9). A resistance R from each data input signal to the nearest V can be
TT
TT
enabled. R = 125–185at 95° C T .
TT
C
9.
I
and I are defined as absolute values and are measured at V /2. I flows from the device, I flows into the device.
OH OL DDQ OH OL
10. If Mode Register Bit 8 (M8) is 0, use RQ = 250in the equation in lieu of presence of an external impedance matched resistor.
11. For V and V , refer to the LLDRAM II IBIS models.
OL
OH
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GS4576C09/18/36L
DC Differential Input Clock Logic Levels
Parameter
Symbol
Min.
–0.3
0.2
Max.
Unit
V
Notes
1–4
V
V
V
+ 0.3
Clock input voltage level: CK and CK
IN(DC)
DDQ
V
+ 0.6
Clock input differential voltage: CK and CK
V
1–5
ID(DC)
DDQ
Notes:
1. DKx and DKx have the same requirements as CK and CK.
2. All voltages referenced to V (GND).
SS
3. The CK and CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross. The input reference level for
signals other than CK/CK is V
REF.
4. The CK and CK input slew rate must be 2 V/ns ( 4 V/ns if measured differentially).
5. is the magnitude of the difference between the input level on CK and the input level on CK.
V
ID
Recommended AC Operating Conditions and Electrical Characteristics
Input AC Logic Levels
Parameter
Symbol
Min.
+ 0.2
Max.
Unit
V
Notes
1, 2, 3
1, 2, 3
V
V
Input High (logic 1) Voltage
Input Low (logic 0) Voltage
—
IH
REF
V
V
– 0.2
REF
—
V
IL
Notes:
1. All voltages referenced to V (GND).
SS
2. The AC and the DC input level specifications are defined in the HSTL standard (that is, the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above (see drawing below) the DC
input Low (High) level).
3. The minimum slew rate for the input signals used to test the device is 2 V/ns in the range between V
and V
.
IL(AC)
IH(AC)
Nominal tAS/ tCS/ tDS and tAH/ tCH/ tDH Slew Rate
V
DDQ
V
IH(AC)MIN
V
IH(DC)MIN
V
REF
V
IL(DC)MAX
V
IL(AC)MAX
V
SS
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GS4576C09/18/36L
AC Differential Input Clock Levels
Parameter
Symbol
Min.
Max.
+ 0.6
Unit
V
Notes
1–5
V
V
Clock input differential voltage: CK and CK
0.4
ID(AC)
DDQ
V
V
/2 – 0.15
V
/2 + 0.15
DDQ
Clock input crossing point voltage: CK and CK
V
1–4, 6
IX(AC)
DDQ
Notes:
1. DKx and DKx have the same requirements as CK and CK.
2. All voltages referenced to V (GND).
SS
3. The CK and CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross. The input reference level for
signals other than CK/CK is V
REF.
4. The CK and CK input slew rate must be 2 V/ns ( 4 V/ns if measured differentially).
5. is the magnitude of the difference between the input level on CK and the input level on CK.
V
ID
6. The value of V is expected to equal V /2 of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
Differential Clock Input Requirements
VIN(DC) MAX
Maximum Clock Level
CK
VIX(AC)MAX
V
DDQ/2 + 0.15
3
VID(AC)
2
VID(DC)
VDDQ/2
1
VDDQ/2 – 0.15
VIX(AC)MIN
CK
VIN(DC) MIN
Minimum Clock Level
Notes:
1. CK and CK must cross within this region.
2. CK and CK must meet at least V
when static and centered around V /2.
DDQ
ID(DC)MIN
3. Minimum peak-to-peak swing.
4. It is a violation to tristate CK and CK after the part is initialized.
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GS4576C09/18/36L
Input Slew Rate Derating
The Address and Command Setup and Hold Derating Values shown in the following table should be added to the default tAS/tCS/
tDS and tAH/tCH/tDH specifications when the slew rate of any of these input signals is less than the 2 V/ns.
To determine the setup and hold time needed for a given slew rate, add the tAS/tCS default specification to the “tAS/tCS VREF to
CK/CK Crossing” and the tAH/tCH default specification to the "tAH/tCH CK/CK Crossing to V " derated values in the Address
REF
and Command Setup and Hold Derating Values table. The derated data setup and hold values can be determined the same way
using the “tDS V
to CK/CK Crossing” and “tDH to CK/CK Crossing to V ” values in the Data Setup and Hold Derating
REF
REF
Values table. The derating values apply to all speed grades.
The setup times in the table relate to a rising signal. The time from the rising signal crossing V
to the CK/CK cross point
IH(AC)MIN
is static and must be maintained across all slew rates. The derated setup timing describes the point at which the rising signal crosses
to the CK/CK cross point. This derated value is calculated by determining the time needed to maintain the given slew
V
REF(DC)
rate and the delta between V
and the CK/CK cross point. All these same values are also valid for falling signals (with
IH(AC)MIN
respect to V
and the CK/ CK cross point).
IL(AC)MAX
The hold times in the table relate to falling signals. The time from the CK/CK cross point to when the signal crosses V
is
IH(DC) MIN
static and must be maintained across all slew rates. The derated hold timing describes the delta between the CK/CK cross point to
when the falling signal crosses V . This derated value is calculated by determining the time needed to maintain the given
REF(DC)
slew rate and the delta between the CK/CK cross point and V
. The hold values are also valid for rising signals (with respect
IH(DC)
to V
and the CK and CK cross point).
IL(DC)MAX
Note: The above descriptions also pertain to data setup and hold derating when CK/CK are replaced with DK/DK.
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GS4576C09/18/36L
Address and Command Setup and Hold Derating Values
tAH/tCH
CK/CK crossing to
tAS/tCS V
CK/CK crossing
to
tAS/tCS V
CK/CK crossing
tAH/tCH
CK/CK crossing to V
Command/Address
Slew Rate (V/ns)
REF
IH(AC)MIN
REF
V
IH(DC)MIN
CK/CK Differential Slew Rate: 2.0 V/ns
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0
5
–100
–100
–100
–100
0
3
6
9
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
11
18
25
33
43
54
67
82
100
–100
–100
–100
–100
–100
–100
–100
13
17
22
27
34
41
50
CK/CK Differential Slew Rate: 1.5 V/ns
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
30
35
–70
–70
–70
–70
–70
–70
–70
–70
–70
–70
–70
30
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
33
36
39
43
47
52
57
64
71
80
41
48
55
63
73
84
97
112
130
CK/CK Differential Slew Rate: 1.0 V/ns
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
60
65
–40
–40
–40
–40
–40
–40
–40
–40
–40
–40
–40
60
10
10
10
10
10
10
10
10
10
10
10
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
63
66
71
78
69
85
73
93
77
103
114
127
142
160
82
87
94
101
110
Rev: 1.04 11/2013
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Data Setup and Hold Derating Values
tDS
tDS V
to CK/CK tDS V
CK/CK
IH(AC)MIN
crossing
tDS
REF
CK/CK crossing to
Data Slew Rate (V/ns)
CK/CK crossing to V
crossing
REF
V
IH(DC)MIN
DK/DK Differential Slew Rate: 2.0 V/ns
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0
5
–100
–100
–100
–100
0
3
6
9
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
11
18
25
33
43
54
67
82
100
–100
–100
–100
–100
–100
–100
–100
13
17
22
27
34
41
50
DK/DK Differential Slew Rate: 1.5 V/ns
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
30
35
–70
–70
–70
–70
–70
–70
–70
–70
–70
–70
–70
30
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
33
36
39
43
47
52
57
64
71
80
41
48
55
63
73
84
97
112
130
DK/DK Differential Slew Rate: 1.0 V/ns
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
60
65
–40
–40
–40
–40
–40
–40
–40
–40
–40
–40
–40
60
10
10
10
10
10
10
10
10
10
10
10
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
63
66
71
78
69
85
73
93
77
103
114
127
142
160
82
87
94
101
110
Rev: 1.04 11/2013
44/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Capacitance
Description
Symbol
Conditions
Min.
1.0
3.0
1.5
1.5
Max.
2.0
Unit
pF
C
Address/control input capacitance
Input/Output capacitance (DQ, DM, and QK, QK)
Clock capacitance (CK/CK and DK/DK)
JTAG pins
I
C
4.5
pF
O
TA = 25° C; f = 100 MHz
V
= V
= 1.8 V
DD
DDQ
C
2.5
pF
CK
C
4.5
pF
JTAG
Notes:
1. Capacitance is not tested on the ZQ pin.
2. JTAG Pins are tested at 50 MHz.
IDD Operating Conditions
Description
Condition
Symbol
-18
-24
-25
-33
I
1 (V ) x9/x18
55
55
55
55
55
55
5
55
55
SB
DD
tCK = idle, All banks idle; No inputs
toggling.
I
1 (V ) x36
Standby Current
mA
mA
SB
DD
I
1 (V
)
EXT
5
5
5
SB
I
I
2 (V ) x9/x18
385
385
5
360
360
5
360
360
5
340
340
5
SB
DD
CS = 1, No commands; Bank address
incremented and half address/data change
once every four clock cycles.
I
2 (V ) x36
Active Standby Current
SB
DD
I
2 (V
)
EXT
SB
BL = 2, Sequential bank access; Bank
transitions once every tRC; Half address
transitions once every tRC; Read followed
by Write sequence; Continuous data during
Write Commands.
1 (V ) x9/x18
495
510
470
485
445
455
425
435
DD
DD
I
1 (V ) x36
DD
DD
Operational Current
Operational Current
mA
mA
I
1 (V
)
EXT
15
15
15
10
DD
BL = 4, Sequential bank access; Bank
I
I
2 (V ) x9/x18
495
540
480
525
450
485
435
470
DD
DD
transitions once every t ; Half address
RC
I
2 (V ) x36
DD
DD
transitions once every t ; Read followed
RC
by Write sequence; Continuous data during
Write Commands.
I
2 (V
)
EXT
25
25
25
20
DD
BL = 8, Sequential bank access; Bank
3 (V ) x9/x18
580
665
555
640
500
570
480
550
DD
DD
transitions once every t ; Half address
RC
I
3 (V ) x36
DD
DD
Operational Current
transitions once every t . Read followed
mA
mA
RC
by Write sequence; Continuous data during
Write Commands.
I
3 (V
)
EXT
40
40
40
30
DD
I
1 (V ) x9/x18
720
720
60
625
625
60
615
615
60
540
540
45
REF
DD
Eight bank cyclic refresh; Continuous
address/data; Command bus remains in
refresh for all eight banks.
I
1 (V ) x36
Burst Refresh Current
REF
DD
I
1 (V
)
EXT
REF
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
IDD Operating Conditions (Continued)
Description
Condition
Symbol
-18
-24
-25
-33
I
2 (V )x9/x18
425
425
15
400
400
15
390
390
15
370
370
10
REF
DD
Single bank refresh; Sequential bank
Distributed Refresh Current access; Half address transitions once every
tRC; Continuous data.
I
2 (V )x36
mA
mA
mA
mA
mA
mA
mA
REF
DD
I
2 (V
)
EXT
REF
I
2W (V ) x9/x18
BL= 2; Cyclic bank access; Half of address
Operating Burst Write Current bits change every clock cycle; Continuous
960
995
60
820
855
60
810
850
60
695
735
45
DD
DD
I
2W (V ) x36
DD
DD
Example
data; Measurement is taken during
continuous Write.
I
2W (V
)
EXT
DD
I
4W (V )x9/x18
BL= 4; Cyclic bank access; Half of address
bits change every two clock cycles;
Continuous data; Measurement is taken
during continuous Write.
755
895
55
655
765
55
655
765
55
575
660
40
DD
DD
Operating Burst Write Current
Example
I
4W (V ) x36
DD
DD
I
4W (V
)
EXT
DD
I
8W (V ) x9/x18
BL= 8; Cyclic bank access; Half of address
bits change every four clock cycles;
Continuous data; Measurement is taken
during continuous Write.
720
855
55
620
730
55
620
730
55
540
630
40
DD
DD
Operating Burst Write Current
Example
I
8W (V ) x36
DD
DD
I
8W (V
)
EXT
DD
BL= 2; Cyclic bank access; Half of address
bits change every clock cycle; Continuous
data; Measurement is taken during
continuous Read.
I
2R (V )x9/x18
850
865
60
725
740
60
720
730
60
620
630
45
DD
DD
Operating Burst Read
Current Example
I
2R (V )x36
DD
DD
I
2R (V
)
EXT
DD
BL= 4; Cyclic bank access; Half of address
bits change every two clock cycles;
Continuous data; Measurement is taken
during continuous Read.
I
I
4R (V ) x9/x18
675
785
55
580
665
55
580
665
55
505
570
40
DD
DD
Operating Burst Read
Current Example
I
4R (V ) x36
DD
DD
I
4R (V
)
EXT
DD
8R (V ) x9/x18
BL= 8; Cyclic bank access; Half of address
bits change every four clock cycles;
Continuous data; Measurement is taken
during continuous Read.
645
760
55
555
645
55
555
645
55
485
550
40
DD
DD
Operating Burst Read
Current Example
I
8R (V ) x36
DD
DD
I
8R (V
)
EXT
DD
Notes:
1. IDD specifications are tested after the device is properly initialized and is operating at worst-case rated temperature and voltage specifications.
2. Definitions of IDD Conditions:
3a. Low is defined as VIN VIL AC
.
(
) MAX
3b. High is defined as VIN VIH AC
.
(
) MIN
3c. Stable is defined as inputs remaining at a High or Low level.
3d. Floating is defined as inputs at VREF = VDDQ/2.
3e. Continuous data is defined as half the DQ signals changng between High and Low every half clock cycle (twice per clock).
3f. Continuous address is defined as half the address signals changing between High and Low every clock cycles (once per clock).
3g. Sequential bank access is defined as the bank address incrementing by one every tRC.
3h. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2 this is every clock, for BL = 4 this
is every other clock, and for BL = 8 this is every fourth clock.
3. CS is High unless a Read, Write, AREF, or MRS command is registered. CS never transitions more than once per clock cycle.
4. IDD parameters are specified with ODT disabled.
5. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operations are tested for the full voltage range specified.
6. IDD tests may use a VIL-to-VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and
parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test
the device is 2 V/ns in the range between VIL AC andVIH AC .
(
)
( )
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
AC Electrical Characteristics
–18
–24
–25
–33
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Clock
Input Clock Cycle Time
Input data clock cycle time
Clock jitter: period
tCK
tDK
1.875
5.7
2.5
5.7
2.5
5.7
3.3
5.7
ns
ns
ps
—
—
tCK
tCK
tCK
tCK
tJITPER
–100
—
100
200
–150
—
150
300
–150
—
150
300
–200
—
200
400
5, 6
tJITCC
Clock jitter: cycle-to-cycle
Clock High Time
ps
—
—
tCKH
tDKH
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCKL
tDKL
Clock Low Time
tCK
—
Clock to input data clock
tCKDK
tMRSC
–0.3
6
0.3
—
–0.45
6
0.5
—
–0.45
6
0.5
—
–0.45
6
1.2
—
ns
—
—
Mode register set cycle time
to any command
tCK
Setup Times
Address/command and input
setup time
tAS/tCS
tDS
0.3
—
—
0.4
—
—
0.4
—
—
0.5
0.3
—
—
ns
ns
—
—
Data–in and data mask to
DK set up time
0.17
0.25
0.25
Hold Times
Address/command and input
hold time
Data-in and data mask to
DK setup time
tAH/tCS
tDH
0.3
—
—
0.4
—
—
0.4
—
—
0.5
0.3
—
—
ns
ns
—
—
0.17
0.25
0.25
Data and Data Strobe
tCKH
tCKL
Output data clock High time
tQKH
tQKL
0.9
0.9
1.1
1.1
0.9
0.9
1.1
1.1
0.9
0.9
1.1
1.1
0.9
0.9
1.1
1.1
—
—
Output data clock Low time
Half–clock period
MIN
(tQKH, tQKL)
MIN
(tQKH, tQKL)
MIN
(tQKH, tQKL)
MIN
(tQKH, tQKL)
tQHP
—
0.2
—
0.25
0.2
—
0.25
0.2
—
0.3
—
ns
ns
—
—
7
QK edge to clock edge skew
tCKQK
–0.2
–0.25
–0.25
–0.3
tQKQ0,
tQKQ1
QK edge to output data
edge
–0.12
–0.22
0.12
–0.2
–0.3
–0.2
–0.3
–0.25
–0.35
0.25
QK edge to any output data
edge
tQKQ
0.22
0.3
0.3
0.35
ns
8
QK edge to QVLD
Data Valid Window
tQKVLD
tDVW
–0.22
0.22
—
–0.3
0.3
—
–0.3
0.3
—
–0.35
0.35
—
ns
—
—
9
tDVW (MIN)
tDVW (MIN)
tDVW (MIN)
tDVW (MIN)
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
AC Electrical Characteristics (Continued)
–18
–24
–25
–33
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Refresh
Average Periodic Refresh
Interval
tREFI
—
0.24
—
0.24
—
0.24
—
0.24
10
Notes:
1. All timing parameters are measured relative to the crossing point of CK/CK, DK/DK and to the crossing point with V
of the command,
REF
address, and data signals.
2. Outputs measured with equivalent load:
V
TT
50
DQ
Test Point
10 pF
V
OUT
3. Tests for AC timing I , and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the
DD
related specifications and device operations are tested for the full voltage range specified.
4. AC timing may use a V – to–V swing of up to 1.5 V in the test environment, but input timing is still referenced to V (or to the crossing
IL
IH
REF
point for CK/CK), and parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew
rate for the input signals used to test the device is 2 V/ns in the rance between V and V
.
IH(AC)
IL(AC)
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Frequency drift is not allowed.
7. tQKQ0 is referenced to DQ0–DQ17 for the x36 xconfiguration and DQ0–DQ8 for the x18 configuration. tQKQ1 is referenced to
DQ18–DQ35 for the x36 configuration and the DQ9–DQ17 for the x18 configuration.
8. tQKQ takes in to account the skew between any QKx and any Q.
9. tDVW (MIN) tQHP – (tQKQx [MAX] + |tQKQx [MIN]|)
10. To improve efficiency, eight AREF commands (one for each bank) can be posted to the LLDRAM II on consecutive cycles at periodic
intervals of 1.95 s
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Read Data Valid Window for x18 Device
tQHP1
tQHP1
QK0
QK0
DQ_Lower_0
DQ_Lower_1
DQ_Lower_2
DQ_Lower_3
DQ_Lower_4
DQ_Lower_5
DQ_Lower_6
DQ_Lower_7
DQ_Lower_8
B"1"
B"0"
B"0"
B"1"
B"1"
B"0"
B"0"
B"0"
B"1"
B"1"
B"1"
B"0"
B"1"
B"0"
B"0"
B"1"
B"1"
B"0"
tQKQ0(Min)
tQKQ0(Min)
tQKQ0(Min)
tQKQ0(Max)
tQKQ0(Max)
tDVW3
X"155"
tDVW3
X"0AA"
DQ_Lower
X"ZZZ"
X"ZZZ"
tQHP1
tQHP1
QK1
QK1
DQ_Upper_9
DQ_Upper_10
DQ_Upper_11
DQ_Upper_12
DQ_Upper_13
DQ_Upper_14
DQ_Upper_15
DQ_Upper_16
DQ_Upper_17
B"0"
B"1"
B"1"
B"0"
B"0"
B"1"
B"1"
B"1"
B"0"
B"0"
B"0"
B"1"
B"0"
B"1"
B"1"
B"0"
B"0"
B"1"
tQKQ1(Min)
tQKQ1(Min)
tQKQ1(Min)
tQKQ1(Max)
tQKQ0(Max)
tDVW3
X"0AA"
tDVW3
X"155"
DQ_Upper
X"ZZZ"
X"ZZZ"
Notes:
1. tQHP is defined as the lesser of tQKH or tQKL.
2. tQKQ0 is referenced to DQ0–DQ8.
3. Minimum data valid window (tDVW) can be expressed as tQHP – (tQKQx [MAX] + |tQKQx [MIN]|).
4. tQKQ1 is referenced to DQ9–DQ17.
5. tQKQ takes into account the skew between any QKx and any DQ.
Read Burst Timing
tCKH
tCKL
tCK
CK
CK
tCKQK
tQKL
tQKH
QKx
QKx
tQKVLDmax
tQKVLDmin
QVLD
tQKQmin
Q1
tQKQmax
Q0
tDVW
Q3
DQ
Q2
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
IEEE 1149.1 Serial Boundary Scan (JTAG)
LLDRAM II includes an IEEE 1149.1 (JTAG) serial boundary scan Test Access Port (TAP). JTAG ports are generally used to
verify the connectivity of the device once it has been mounted on a Printed Circuit Board (PCB). The port operates in accordance
with IEEE Standard 1149.1-2001 (JTAG). Because the ZQ pin is actually an analog output, to ensure proper boundary-scan testing
of the ZQ pin, Mode Register Bit 8 (M8) needs to be set to 0 until the JTAG testing of the pin is complete. Note that upon power
up, the default state of Mode Register Bit 8 (M8) is Low.
Whenever the JTAG port is used prior to the initialization of the LLDRAM II device, such as when initial conectivity testing is
conducted, it is critical that the CK and CK pins meet V
or that CS be held High from power-up until testing begins. Failure
ID(DC)
to do so can result in inadvertent MRS commands being loaded and causing unexpected test results. Alternately a partial
initialization can be conducted that consists of simply loading a single MRS command with desired MRS Register settings. JTAG
testing may then begin as soon as tMRSC is satisfied. JTAG testing can be conducted after full initilization as well.
The input signals of the test access port (TDI, TMS, and TCK) are referenced to the V as a supply, while the output driver of the
DD
TAP (TDO) is powered by V
.
DDQ
The JTAG test access port incorporates a standardTAP controller from which the Instruction Register, Boundary Scan Register,
Bypass Register, and ID Code Register can be selected. Each of these functions of the TAP controller are described below.
Disabling the JTAG Feature
Use of the JTAG port is never required for RAM operation. To disable the TAP controller, TCK must be tied Low (V ) to prevent
SS
clocking of the device. TDI and TMS are internally pulled up and may be unconnected or they can be connected to V directly or
DD
through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state, which will not
interfere with the operation of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK.
All of the states in the TAP Controller State Diagram are entered through the serial input of the TMS pin. A “0” in the diagram
represents a Low on the TMS pin during the rising edge of TCK while a “1” represents a High on TMS.
Test Data-In (TDI)
The TDI ball is used to serially input test instructions and data into the registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP Controller State Diagram. TDI is connected to the Most Significant Bit
(MSB) of any register (see the TAP Controller Block Diagram).
Test Data-Out (TDO)
The TDO output ball is used to serially clock test instructions and data out from the registers. The TDO output driver is only active
during the Shift-IR and Shift-DR TAP controller states. In all other states, the TDO pin is in a High-Z state. The output changes on
the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register (see the TAP Controller Block
Diagram).
TAP Controller
The TAP controller is a finite state machine that uses the state of the TMS pin at the rising edge of TCK to navigate through its
various modes of operation. See the TAP Controller State Diagram. Each state is described in detail below.
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GS4576C09/18/36L
Test-Logic-Reset
The test-logic-reset controller state is entered when TMS is held High for at least five consecutive rising edges of TCK. As long as
TMS remains High, the TAP controller will remain in the test-logic-reset state. The test logic is inactive during this state.
Run-Test/Idle
The run-test/idle is a controller state in between scan operations. This state can be maintained by holding TMS Low. From here
either the data register scan, or subsequently, the instruction register scan can be selected.
Select-DR-Scan
Select-DR-scan is a temporary controller state. All test data registers retain their previous state while here.
Capture-DR
The Capture-DR state is where the data is parallel-loaded into the test data registers. If the Boundary Scan Register is the currently
selected register, then the data currently on the pins is latched into the test data registers.
Shift-DR
Data is shifted serially through the data register while in this state. As new data is input through the TDI pin, data is shifted out of
the TDO pin.
Exit1-DR, Pause-DR, and Exit2-DR
The purpose of Exit1-DR is used to provide a path to return back to the run-test/idle state (through the Update-DR state). The
Pause-DR state is entered when the shifting of data through the test registers needs to be suspended. When shifting is to reconvene,
the controller enters the Exit2-DR state and then can re-enter the Shift-DR state.
Update-DR
When the EXTEST instruction is selected, there are latched parallel outputs of the boundary scan shift register that only change
state during the Update-DR controller state.
Instruction Register States
The instruction register states of the TAP controller are similar to the data register states. The desired instruction is serially shifted
into the instruction register during the Shift-IR state and is loaded during the Update-IR state.
Loading Instruction Code and Shifting Out Data
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
8-bit Instruction Code
TCK
TMS
TDI
TAP State
TDO
Logic-Reset
Idle
Select-DR
Select-IR
Capture-IR
Shift-IR
Shift-IR
Exit 1-IR
Pause-IR
Pause-IR
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Loading Instruction Code and Shifting Out Data (Continued)
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
n-bit Register between TDI and TDO
TCK
TMS
TDI
TAP State
TDO
Exit 2-IR
Update-IR
Select-DR
Capture-DR
Shift-DR
Shift-DR
Shift-DR
Exit 1-DR
Update-DR
Idle
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Select IR-scan
Select DR-scan
Run Test Idle
0
0
0
1
1
Capture-IR
Capture-DR
0
0
Shift-IR
Shift-DR
0
0
1
1
1
1
Exit1-IR
Exit1-DR
0
0
Pause-IR
Pause-DR
0
0
1
1
0
0
Exit2-IR
Exit2-DR
1
1
Update-IR
Update-DR
1
0
1
0
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
TAP Controller Block Diagram
0
Bypass Regsiter
7
6
5
4
3
2
1
0
0
Instruction Regsiter
Selection
circuitry
Selection
circuitry
TDO
TDI
31 30 29
.
.
.
2
1
Identification Regsiter
x1
.
.
.
.
.
2
1
0
Boundary Scan Regsiter
TCK
TMS
TAP Controller
Note:
x= 112 for all configurations
Performing a TAP RESET
A reset is performed by forcing TMS High (V
) for five rising edges of TCK. This RESET does not affect the operation of the
DDQ
LLDRAM II and may be performed while the LLDRAM II is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the LLDRAM II test
circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is loaded during the Update-IR state of the
TAP controller. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state, the two LSBs are loaded with a binary “01” pattern to allow for fault isolation
of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is
a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the LLDRAM II with
minimal delay. The bypass register is set Low (V ) when the BYPASS instruction is executed.
SS
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Boundary Scan Register
The Boundary Scan Register is connected to all the input and bidirectional balls on the LLDRAM II. Several bits are also included
in the scan register for reserved balls. The LLDRAM II has a 113-bit register.
The Boundary Scan Register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state.
The Boundary Scan Register table shows the order in which the bits are connected. Each bit corresponds to one of the balls on the
LLDRAM II package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE command is loaded in
the instruction register. The IDCODE is hardwired into the LLDRAM II and can be shifted out when the TAP controller is in the
shift-DR state. The ID register has a vendor code and other information described in the table below.
Identification Register Definitions
Instruction Field
Bit Size
Bit Size
ab = die revision
cd = 00 for x9, 01 for x18, 10 for x36
Revision number (31:28)
abcd
def = 000 for 288Mb, 001 for 576Mb
i = 0 for common I/O, 1 for separate I/O
jk = 01 for LLDRAM II
Device ID (27:12)
00jkidef10100111
GSI JEDEC ID code (11:1)
01011011001
1
Allows unique identification of LLDRAM II vendor
Indicates the presence of an ID register
ID register presence indicator (0)
TAP Instruction Set
Overview
Many different instructions (256) are possible with the 8-bit instruction register. All combinations used are listed in the Instruction
Codes table. These six instructions are described in detail below. The remaining instructions are reserved and should not be used.
The TAP controller used in this LLDRAM II is fully compliant to the 1149.1 convention.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary Scan Register cells at output
balls are used to apply a test vector, while those at input balls capture test results. Typically, the first test vector to be applied using
the EXTEST instruction will be shifted into the Boundary Scan Register using the PRELOAD instruction. Thus, during the
Update-IR state of EXTEST, the output driver is turned on, and the PRELOAD data is driven onto the output balls.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the
TAP controller is given a test logic reset state.
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
High-Z
The High-Z instruction places all LLDRAM II outputs into a High-Z state, and causes the bypass register to be connected between
TDI and TDO when the TAP Controller is in the Shift DR state.
CLAMP
When the CLAMP instruction is loaded into the instruction register, the data driven by the output balls are determined from the
values held in the Boundary Scan Register. Additionally, it causes the bypass register to be connected between TDI and TDO
when the TAP Controller is in the Shift DR state.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is captured in the Boundary Scan Register.
The user must be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while the LLDRAM II clock
operates significantly faster. Because there is a large difference between the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results
may not be possible.
To ensure that the Boundary Scan Register will capture the correct value of a signal, the LLDRAM II signal must be stabilized long
enough to meet the TAP controller’s capture setup plus hold time (tCS + tCH). The LLDRAM II clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the value of the CK and CK captured in the Boundary Scan Register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the Boundary
Scan Register between the TDI and TDO balls.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is
placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple
devices are connected together on a board.
Reserved for Future Use
The remaining instructions are not implemented but are reserved for future use. Do not use these instructions.
TAP Timing
T0
T1
T2
T3
T4
T5
tTLTH
tTHTL
tMVTH
tDVTH
tTHTH
Test Clock (TCK)
Test Mode Select (TMS)
Test Data-In (TDI)
tTHMX
tTHDX
tTLOX
tTLOV
Test Data-Out (TDO)
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
TAP Input AC Logic Levels
Description
Symbol
Min
+ 0.3
Max
Units
V
V
Input High (logic 1) Voltage
—
V
V
IH
REF
V
V
– 0.3
REF
Input Low (logic 0) Voltage
—
IL
TAP AC Electrical Characteristics
Description
Symbol
Min
Max
Units
Clock
Clock Cycle Time
Clock Frequency
Clock High Time
Clock Low Time
tTHTH
tTF
20
—
10
10
—
50
—
—
ns
MHz
ns
tTHTL
tTLTH
ns
TDI/TDO Times
TCK Low to TDO Unknown
TCK Low to TDO Valid
TDI Valid to TCK High
TCK High to TDI Invalid
tTLOX
tTLOV
tDVTH
tTHDX
0
—
10
—
—
ns
ns
ns
ns
—
5
5
Setup Times
TMS Setup
tMVTH
tCS
5
—
—
ns
ns
Capture Setup
5
Hold Times
TMS Setup
tTHMX
tCH
5
5
—
—
ns
ns
Capture Setup
Note:
tCS and tCH refer to the set up and hold time requirements of latching data from the Boundary Scan Register.
Rev: 1.04 11/2013
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
TAP DC Electrical Characteristics and Operating Conditions
Description
Condition
Symbol
Min
+ 0.15
Max
+ 0.3
Units
Notes
1, 2
V
V
V
Input High (logic 1) Voltage
Input High (logic 0) Voltage
—
—
V
V
IH
REF
DD
V
V
– 0.3
V
– 0.15
REF
1, 2
IL
SS
Output disabled,
I
Input Leakage Current
–5.0
5.0
—
LI
0 VV V
IN
DDQ
0 VV V
I
Output Leakage Current
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
–5.0
—
5.0
0.2
0.4
—
V
—
1
IN
DD
LO
I
= 100
V
V
V
1
2
1
OLC
OL
OL
I
= 2mA
—
V
1
OLT
I
= 100
V
– 0.2
V
1
OHC
OH
OH
DDQ
DDQ
I = 2mA
V
2
V
– 0.4
—
V
1
OHT
Notes:
1. All voltages referenced to V (GND).
SS
2. Overshoot = V
V + 0.7 V for t tTHTH/2; undershoot = V
– 0.5 V for t tTHTH/2; during normal operation, V must
DDQ
IH(AC)
DD
IL(AC)
not exceed V
DD.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
8
1
ID
32
113
Boundary Scan
JTAG TAP Instruction Codes
Instruction
Code
Description
Captures I/O ring contents; Places the Boundary Scan Register between TDI and TDO. Data
driven by output balls are determined from values held in the Boundary Scan Register.
EXTEST
0000 0000
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect LLDRAM II operations.
IDCODE
SAMPLE/PRELOAD
CLAMP
0010 0001
0000 0101
0000 0111
0000 0011
1111 1111
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. This
operation does not affect LLDRAM II operations.
Selects the bypass register to be connected between TDI and TDO. Data driven by output balls are
determined from values held in the Boundary Scan Register.
Selects the bypass register to be connected between TDI and TDO. All outputs are forced into
High-Z.
HIGH-Z
Places Bypass Register between TDI and TDO.This operation does not affect LLDRAM II
operations.
BYPASS
Rev: 1.04 11/2013
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Boundary Scan Exit Order
Bit #
1
Ball
K1
Bit #
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
Ball
R11
R11
P11
P11
P10
P10
N11
N11
N10
N10
P12
N12
M11
M10
M12
L12
L11
Bit #
77
Ball
C11
C11
C10
C10
B11
B11
B10
B10
B3
2
K2
78
3
L2
79
4
L1
80
5
M1
M3
M2
N1
P1
81
6
82
7
83
8
84
9
85
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
N3
N3
N2
N2
P3
86
B3
87
B2
88
B2
89
C3
C3
C2
C2
D3
D3
D2
D2
E2
90
P3
91
P2
92
P2
93
R2
R3
T2
K11
K12
J12
J11
94
95
96
T2
97
T3
H11
H12
G12
G10
G11
E12
F12
F10
F10
F11
F11
E10
E10
E11
E11
D11
D10
98
E2
T3
99
E3
U2
U2
U3
U3
V2
100
101
102
103
104
105
106
107
108
109
110
111
112
113
—
E3
F2
F2
F3
F3
U10
U10
U11
U11
T10
T10
T11
T11
R10
R10
E1
F1
G2
G3
G1
H1
H2
J2
J1
—
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
Rev: 1.04 11/2013
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Package Dimensions—144-Bump BGA (Package L)
A1
1
2
3
4
5
6 7 8 9 10 11 12
A
B
C
D
E
F
G
H
J
10.60 CTR.
10° TYP.
0.73±0.1
K
L
M
N
P
SEATING PLANE
0.012
A
A
R
T
U
V
8.80
Ø0.51 (144x)
A1
0.80 TYP.
0.49±0.05
12 11 10
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
18.1 CTR
K
L
M
N
P
R
T
U
V
1.20 MAX
0.8 TYP
0.34 MIN
8.8 CTR
11.00±0.10
Note: All dimensions in millimeters.
Rev: 1.04 11/2013
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Ordering Information for GSI LLDRAM IIs
Speed
(tCK/tRC)
1
2
Org
Type
Package
Part Number
T
64M x 9
64M x 9
64M x 9
64M x 9
32M x 18
32M x 18
32M x 18
32M x 18
16M x 36
16M x 36
16M x 36
16M x 36
64M x 9
64M x 9
64M x 9
64M x 9
32M x 18
32M x 18
32M x 18
32M x 18
16M x 36
16M x 36
16M x 36
16M x 36
64M x 9
64M x 9
64M x 9
GS4576C09L-18
GS4576C09L-24
GS4576C09L-25
GS4576C09L-33
GS4576C18L-18
GS4576C18L-24
GS4576C18L-25
GS4576C18L-33
GS4576C36L-18
GS4576C36L-24
GS4576C36L-25
GS4576C36L-33
GS4576C09GL-18
GS4576C09GL-24
GS4576C09GL-25
GS4576C09GL-33
GS4576C18GL-18
GS4576C18GL-24
GS4576C18GL-25
GS4576C18GL-33
GS4576C36GL-18
GS4576C36GL-24
GS4576C36GL-25
GS4576C36GL-33
GS4576C09L-18I
GS4576C09L-24I
GS4576C09L-25I
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
144-ball BGA
144-ball BGA
533/15
400/15
400/20
300/20
533/15
400/15
400/20
300/20
533/15
400/15
400/20
300/20
533/15
400/15
400/20
300/20
533/15
400/15
400/20
300/20
533/15
400/15
400/20
300/20
533/15
400/15
400/20
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
144-ball BGA
144-ball BGA
144-ball BGA
144-ball BGA
144-ball BGA
144-ball BGA
144-ball BGA
144-ball BGA
144-ball BGA
144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
144-ball BGA
144-ball BGA
I
144-ball BGA
I
Note:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS4576C09-533T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.04 11/2013
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Ordering Information for GSI LLDRAM IIs (Continued)
Speed
(tCK/tRC)
1
2
Org
Type
Package
Part Number
T
64M x 9
32M x 18
32M x 18
32M x 18
32M x 18
16M x 36
16M x 36
16M x 36
16M x 36
64M x 9
GS4576C09L-33I
GS4576C18L-18I
GS4576C18L-24I
GS4576C18L-25I
GS4576C18L-33I
GS4576C36L-18I
GS4576C36L-24I
GS4576C36L-25I
GS4576C36L-33I
GS4576C09GL-18I
GS4576C09GL-24I
GS4576C09GL-25I
GS4576C09GL-33I
GS4576C18GL-18I
GS4576C18GL-24
GS4576C18GL-25I
GS4576C18GL-33I
GS4576C36GL-18I
GS4576C36GL-24I
GS4576C36GL-25I
GS4576C36GL-33I
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
CIO LLDRAM II
144-ball BGA
144-ball BGA
300/20
533/15
400/15
400/20
300/20
533/15
400/15
400/20
300/20
533/15
400/15
400/20
300/20
533/15
400/15
400/20
300/20
533/15
400/15
400/20
300/20
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
144-ball BGA
144-ball BGA
144-ball BGA
144-ball BGA
144-ball BGA
144-ball BGA
144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
RoHS-compliant 144-ball BGA
64M x 9
64M x 9
64M x 9
32M x 18
32M x 18
32M x 18
32M x 18
16M x 36
16M x 36
16M x 36
16M x 36
Note:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS4576C09-533T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.04 11/2013
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
576Mb LLDRAM II Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
• Revised Timing Diagrams
4576Cxx_r1
• Modified Cycle Time and Read/Write Latency tables (pg. 19,
4576Cxx_r1.00a
31.)
• Updated Operating Conditions (pg. 46), AC Electrical
Characteristics (pg. 48)
• Changed FBGA references to BGA (including diagrams)
4576Cxx_r1.00b
4576Cxx_r1.01
• Various changes to prepare for public release
• Added IDD Op Conditions
• (Rev1.02b: corrected mechanical drawing)
• (Rev1.02c: Editorial updates)
• (Rev1.02d: Updated NOP commands from 3000 to 2048)
• (Rev1.02e: Added Termal Impedance numbers for 4-layer
substrate)
4576Cxx_r1.02
• (Rev1.02f: Changed all V
references to V
)
SSQ
SS
• Changed DLL Reset to 1024 cycles (page 10)
• Corrected typos/wording errors in TAP section
• (Rev1.03a: Changed NOP time from 2048 to 1024)
4576Cxx_r1.03
4576Cxx_r1.04
• Updated to reflect MP status
Rev: 1.04 11/2013
62/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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