首页 |元器件品牌

GS71116AJ-6T [GSI]

Standard SRAM, 64KX16, 6ns, CMOS, PDSO44, 0.400 INCH, SOJ-44;
GS71116AJ-6T
型号： GS71116AJ-6T
厂家： GSI TECHNOLOGY    GSI TECHNOLOGY
描述：

Standard SRAM, 64KX16, 6ns, CMOS, PDSO44, 0.400 INCH, SOJ-44

静态存储器 光电二极管 内存集成电路
文件： 总15页 (文件大小：468K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
GS71116ATP/J/U  
6, 8, 10, 12 ns  
SOJ, TSOP, FP-BGA  
Commercial Temp  
Industrial Temp  
64K x 16  
3.3 V V  
DD  
Center V and V  
DD  
SS  
1Mb Asynchronous SRAM  
SOJ 64K x 16-Pin Configuration  
Features  
• Fast access time: 6, 8, 10, 12 ns  
• CMOS low power operation: 165/125/100/85 mA at  
minimum cycle time  
• Single 3.3 V power supply  
• All inputs and outputs are TTL-compatible  
• Byte control  
• Fully static operation  
• Industrial Temperature Option: –40° to 85°C  
• Package line up  
A4  
1
A5  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A3  
A6  
2
A2  
A7  
3
A1  
OE  
4
Top view  
A0  
UB  
5
CE  
LB  
6
DQ1  
DQ2  
DQ3  
DQ4  
DQ16  
DQ15  
DQ14  
7
8
9
10  
11  
12  
13  
14  
15  
DQ13  
J: 400 mil, 44-pin SOJ package  
TP: 400 mil, 44-pin TSOP Type II package  
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package  
44-pin  
SOJ  
V
DD  
V
V
SS  
V
SS  
DD  
DQ5  
DQ6  
DQ7  
DQ8  
WE  
DQ12  
DQ11  
DQ10  
DQ9  
NC  
Description  
16  
17  
18  
The GS71116A is a high speed CMOS static RAM organized  
as 65,536-words by 16-bits. Static design eliminates the need  
for external clocks or timing strobes. Operating on a single  
3.3 V power supply and all inputs and outputs are TTL-  
compatible. The GS71116A is available in a 6 mm x 8 mm  
Fine Pitch BGA package, as well as in 400 mil SOJ and 400  
mil TSOP Type-II packages.  
A15  
A14  
A13  
A12  
NC  
A8  
A9  
19  
20  
21  
22  
A10  
A11  
NC  
Package J  
Pin Descriptions  
Fine Pitch BGA 64K x 16-Bump Configuration  
Symbol  
A0–A15  
Description  
Address input  
1
2
3
4
5
6
DQ1–DQ16  
Data input/output  
Chip enable input  
CE  
A
B
C
LB  
OE  
A0  
A3  
A1  
A4  
A6  
A2  
NC  
Lower byte enable input  
(DQ1 to DQ8)  
LB  
DQ16 UB  
CE  
DQ1  
Upper byte enable input  
(DQ9 to DQ16)  
DQ14 DQ15 A5  
DQ2 DQ3  
UB  
VSS  
VDD  
VDD  
VSS  
D
E
DQ13 NC  
DQ12 NC  
A7  
DQ4  
WE  
OE  
Write enable input  
Output enable input  
+3.3 V power supply  
NC DQ5  
VDD  
F
G
H
DQ11 DQ10 A8  
A9  
DQ7 DQ6  
WE DQ8  
VSS  
NC  
Ground  
DQ9 NC  
NC A12  
A10  
A13  
A11  
A14  
No connect  
A15  
NC  
6 mm x 8 mm, 0.75 mm Bump Pitch (Package U)  
© 2001, Giga Semiconductor, Inc.  
Rev: 1.03 3/2002  
1/15  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
Top View  
TSOP-II 64K x 16-Pin Configuration  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
1
A4  
A3  
A5  
2
A6  
3
A2  
A7  
4
A1  
OE  
Top view  
5
A0  
UB  
6
CE  
LB  
7
DQ1  
DQ2  
DQ3  
DQ4  
DQ16  
DQ15  
DQ14  
8
9
10  
11  
12  
13  
14  
15  
DQ13  
44-pin  
V
DD  
V
V
SS  
DD  
V
SS  
TSOP II  
DQ5  
DQ6  
DQ7  
DQ8  
WE  
DQ12  
DQ11  
DQ10  
DQ9  
NC  
16  
17  
18  
19  
20  
21  
22  
A15  
A14  
A13  
A12  
NC  
A8  
A9  
A10  
A11  
NC  
Package TP  
Block Diagram  
A0  
Row  
Decoder  
Memory Array  
Address  
Input  
Buffer  
Column  
Decoder  
A15  
CE  
WE  
OE  
UB  
LB  
I/O Buffer  
Control  
_____  
_____  
DQ16  
DQ1  
Rev: 1.03 3/2002  
2/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
Truth Table  
V
Current  
CE  
OE  
WE  
LB  
UB  
DQ1 to DQ8  
DQ9 to DQ16  
DD  
H
X
X
X
L
X
L
Not Selected  
Read  
Not Selected  
Read  
ISB1, ISB2  
L
L
L
H
L
L
H
L
Read  
High Z  
H
L
High Z  
Read  
L
Write  
Write  
IDD  
X
L
H
L
Write  
Not Write, High Z  
Write  
H
X
H
Not Write, High Z  
High Z  
L
L
H
X
H
X
X
H
High Z  
High Z  
High Z  
Note: X: “H” or “L”  
Absolute Maximum Ratings  
Parameter  
Symbol  
Rating  
Unit  
Supply Voltage  
VDD  
–0.5 to +4.6  
V
–0.5 to VDD +0.5  
(£ 4.6 V max.)  
Input Voltage  
VIN  
V
V
–0.5 to VDD +0.5  
(£ 4.6 V max.)  
Output Voltage  
VOUT  
Allowable power dissipation  
Storage temperature  
PD  
0.7  
W
oC  
TSTG  
–55 to 150  
Note:  
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec-  
ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device  
reliability.  
Rev: 1.03 3/2002  
3/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
Recommended Operating Conditions  
Parameter  
Supply Voltage for -8/-10/-12  
Supply Voltage for -6  
Input High Voltage  
Symbol  
VDD  
Min  
3.0  
Typ  
3.3  
3.3  
—
Max  
3.6  
Unit  
V
V
V
V
VDD  
3.135  
2.0  
3.6  
VDD +0.3  
0.8  
VIH  
VIL  
Input Low Voltage  
–0.3  
—
Ambient Temperature,  
Commercial Range  
oC  
oC  
TAc  
TAI  
0
—
—
70  
85  
Ambient Temperature,  
Industrial Range  
–40  
Notes:  
1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.  
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.  
Capacitance  
Parameter  
Input Capacitance  
Output Capacitance  
Symbol  
CIN  
Test Condition  
VIN = 0 V  
Max  
Unit  
pF  
5
7
COUT  
VOUT = 0 V  
pF  
Notes:  
1. Tested at TA = 25°C, f = 1 MHz  
2. These parameters are sampled and are not 100% tested.  
DC I/O Pin Characteristics  
Parameter  
Symbol  
Test Conditions  
Min  
Max  
VIN = 0 to VDD  
Input Leakage Current  
IIL  
–1 uA  
–1 uA  
2.4  
1uA  
Output High Z  
VOUT = 0 to VDD  
Output Leakage  
Current  
ILO  
1uA  
Output High Voltage  
Output Low Voltage  
VOH  
VOL  
IOH = –4 mA  
ILO = +4 mA  
0.4V  
Rev: 1.03 3/2002  
4/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
Power Supply Currents  
0 to 70°C  
8 ns 10 ns 12 ns  
–40 to 85°C  
Parameter  
Symbol  
Test Conditions  
6 ns  
6 ns  
8 ns  
10 ns 12 ns  
CE £ VIL  
Operating  
Supply  
Current  
All other inputs  
³ VIH or £ VIL  
Min. cycle time  
IOUT = 0 mA  
IDD  
165 mA 125 mA 100 mA 85 mA 170 mA 130 mA 105 mA 90 mA  
CE ³ VIH  
Standby  
Current  
All other inputs  
³ VIH or £VIL  
Min. cycle time  
ISB1  
ISB2  
25 mA 20 mA 20 mA 15 mA 30 mA  
25 mA 25 mA 20 mA  
CE ³ VDD – 0.2 V  
All other inputs  
³ VDD – 0.2 V or £ 0.2 V  
Standby  
Current  
2 mA  
5 mA  
Rev: 1.03 3/2002  
5/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
AC Test Conditions  
Output Load 1  
Parameter  
Input high level  
Input low level  
Conditions  
VIH = 2.4 V  
VI L= 0.4 V  
tr = 1V/ns  
tf = 1 V/ns  
1.4 V  
DQ  
30pF1  
50W  
Input rise time  
VT = 1.4 V  
Input fall time  
Input reference level  
Output reference level  
Output load  
Output Load 2  
1.4 V  
3.3 V  
Fig. 1& 2  
589W  
434W  
DQ  
Notes:  
5pF1  
1. Include scope and jig capacitance.  
2. Test conditions as specified with output loading as shown in Fig. 1  
unless otherwise noted.  
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ  
Rev: 1.03 3/2002  
6/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
AC Characteristics  
Read Cycle  
-6  
-8  
-10  
-12  
Parameter  
Symbol  
Unit  
Min  
6
Max  
—
Min  
8
Max  
—
Min  
10  
—
—
—
—
3
Max  
—
10  
10  
4
Min  
12  
—
—
—
—
3
Max  
—
12  
12  
5
Read cycle time  
tRC  
tAA  
tAC  
tAB  
tOE  
tOH  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address access time  
—
—
—
—
3
6
—
—
—
—
3
8
Chip enable access time (CE)  
Byte enable access time (UB, LB)  
Output enable to output valid (OE)  
Output hold from address change  
Chip enable to output in low Z (CE)  
6
8
3.0  
3.0  
—
3.5  
3.5  
—
4
5
—
—
—
—
*
3
—
3
—
3
3
tLZ  
*
Output enable to output in low Z (OE)  
Byte enable to output in low Z (UB, LB)  
Chip disable to output in High Z (CE)  
Output disable to output in High Z (OE)  
Byte disable to output in High Z (UB, LB)  
0
—
—
0
—
—
0
—
—
5
0
0
—
—
6
ns  
ns  
ns  
ns  
—
tOLZ  
*
0
0
0
tBLZ  
*
—
—
—
3
—
—
—
4
—
—
—
—
—
—
tHZ  
*
3.0  
3.0  
3.5  
3.5  
4
5
tOHZ  
*
4
5
tBHZ  
* These parameters are sampled and are not 100% tested.  
Read Cycle 1: CE = OE = V , WE = V , UB and, or LB = V  
IL  
IH  
IL  
tRC  
Address  
tAA  
tOH  
Data Out  
Previous Data  
Data valid  
Rev: 1.03 3/2002  
7/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
Read Cycle 2: WE = V  
IH  
tRC  
Address  
CE  
tAA  
tAC  
tHZ  
tLZ  
tAB  
UB, LB  
OE  
tBHZ  
tOHZ  
tBLZ  
tOLZ  
tOE  
Data valid  
Data Out  
High impedance  
Write Cycle  
-6  
-8  
-10  
-12  
Parameter  
Symbol  
Unit  
Min  
6
Max  
—
—
—
—
—
—
—
—
—
—
—
Min  
8
Max  
—
—
—
—
—
—
—
—
—
—
—
Min  
10  
7
Max  
—
—
—
—
—
—
—
—
—
—
—
Min  
Max  
—
—
—
—
—
—
—
—
—
—
—
Write cycle time  
tWC  
tAW  
tCW  
tBW  
tDW  
tDH  
12  
8
8
8
6
0
8
0
0
0
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address valid to end of write  
Chip enable to end of write  
Byte enable to end of write  
Data set up time  
5.0  
5.0  
5.0  
3.0  
0
5.5  
5.5  
5.5  
4
7
7
5
Data hold time  
0
0
Write pulse width  
tWP  
tAS  
5.0  
0
5.5  
0
7
Address set up time  
0
Write recovery time (WE)  
Write recovery time (CE)  
Output Low Z from end of write  
tWR  
tWR1  
0
0
0
0
0
0
tWLZ*  
tWHZ*  
3
3
3
Write to output in High Z  
—
3.0  
—
3.5  
—
4
—
5
ns  
* These parameters are sampled and are not 100% tested.  
Rev: 1.03 3/2002  
8/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
Write Cycle 1: WE control  
tWC  
Address  
tAW  
tWR  
OE  
CE  
tCW  
tBW  
UB, LB  
WE  
tAS  
tWP  
tDW  
tDH  
Data valid  
Data In  
tWHZ  
tWLZ  
High impedance  
Data Out  
Write Cycle 2: CE control  
tWC  
Address  
OE  
tAW  
tWR1  
tAS  
tCW  
tBW  
CE  
UB, LB  
WE  
tWP  
tDW  
tDH  
Data valid  
Data In  
Data Out  
High impedance  
Rev: 1.03 3/2002  
9/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
Write Cycle 3: UB, LB control  
tWC  
Address  
tAW  
tWR1  
OE  
CE  
tAS  
tCW  
tBW  
UB, LB  
WE  
tWP  
tDW  
tDH  
Data valid  
Data In  
Data Out  
High impedance  
Rev: 1.03 3/2002  
10/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
44-Pin, 400 mil SOJ  
Dimension in inch  
min nom max  
Dimension in mm  
Symbol  
min  
—
nom  
—
max  
3.759  
—
L
D
A
A1  
A2  
B
—
—
—
0.148  
—
c
44  
23  
22  
0.025  
0.635  
—
0.105 0.110 0.115 2.667  
0.018  
0.026 0.028 0.032 0.660  
0.008  
1.120 1.125 1.130 28.44  
2.794  
0.457  
0.711  
0.203  
28.58  
2.921  
—
—
—
—
B1  
c
0.813  
—
—
—
—
1
D
28.70  
e
A
E
0.395 0.400 0.405 10.033 10.160 10.287  
0.05 1.27  
0.435 0.440 0.445 11.049 11.176 11.303  
e
—
—
—
—
HE  
GE  
L
B
y
0.360 0.370 0.380 9.144  
0.082 0.087 0.106 2.083  
9.398  
2.210  
—
9.652  
2.70  
B1  
Q
Detail A  
y
—
0o  
—
—
0.004  
7o  
—
0o  
0.102  
7o  
Q
—
Notes:  
1. Dimension D& E do not include interlead flash.  
2. Dimension B1 does not include dambar protrusion/intrusion.  
3. Controlling dimension: inches  
Rev: 1.03 3/2002  
11/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
44 Pin, 400 mil TSOP-II  
Dimension in inch  
Dimension in mm  
Symbol  
min  
—
nom max  
min  
—
nom max  
D
c
44  
23  
22  
A
A1  
A2  
B
—
—
0.047  
—
—
1.20  
—
0.002  
0.05  
—
0.037 0.039 0.041 0.95  
0.01 0.014 0.018 0.25  
1.00  
0.35  
0.15  
1.05  
0.45  
—
A
c
—
0.006  
—
—
D
0.721 0.725 0.729 18.31 18.41 18.51  
0.396 0.400 0.404 10.06 10.16 10.26  
1
E
e
B
e
—
0.031  
—
—
0.80  
—
HE  
L
0.455 0.463 0.471 11.56 11.76 11.96  
0.016 0.020 0.024 0.40  
0.50  
0.80  
—
0.60  
—
y
L1  
y
—
—
0.031  
—
—
—
—
0.004  
0.10  
0o  
5o  
0o  
5o  
Q
—
—
Q
Detail A  
Notes:  
1. Dimension D& E do not include interlead flash.  
2. Dimension B does not include dambar protrusion/intrusion.  
3. Controlling dimension: mm  
Rev: 1.03 3/2002  
12/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
6 mm x 8 mm Fine Pitch BGA  
0 1 . 0 ± 0 0 . 8  
0.10  
5 2 . 5  
Rev: 1.03 3/2002  
13/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
Ordering Information  
*
Package  
Access Time  
Temp. Range  
Status  
Part Number  
GS71116ATP-6  
GS71116ATP-8  
GS71116ATP-10  
GS71116ATP-12  
GS71116ATP-6I  
GS71116ATP-8I  
GS71116ATP-10I  
GS71116ATP-12I  
GS71116AJ-6  
400 mil TSOP-II  
400 mil TSOP-II  
6 ns  
8 ns  
Commercial  
Commercial  
Commercial  
Commercial  
Industrial  
400 mil TSOP-II  
10 ns  
12 ns  
6 ns  
400 mil TSOP-II  
400 mil TSOP-II  
400 mil TSOP-II  
8 ns  
Industrial  
400 mil TSOP-II  
10 ns  
12 ns  
6 ns  
Industrial  
400 mil TSOP-II  
Industrial  
400 mil SOJ  
Commercial  
Commercial  
Commercial  
Commercial  
Industrial  
GS71116AJ-8  
400 mil SOJ  
8 ns  
GS71116AJ-10  
GS71116AJ-12  
GS71116AJ-6I  
GS71116AJ-8I  
GS71116AJ-10I  
GS71116AJ-12I  
GS71116AU-6  
GS71116AU-8  
GS71116AU-10  
GS71116AU-12  
GS71116AU-6I  
GS71116AU-8I  
GS71116AU-10I  
GS71116AU-12I  
400 mil SOJ  
10 ns  
12 ns  
6 ns  
400 mil SOJ  
400 mil SOJ  
400 mil SOJ  
8 ns  
Industrial  
400 mil SOJ  
10 ns  
12 ns  
6 ns  
Industrial  
400 mil SOJ  
Industrial  
6 mm x 8 mm Fine Pitch BGA  
6 mm x 8 mm Fine Pitch BGA  
6 mm x 8 mm Fine Pitch BGA  
6 mm x 8 mm Fine Pitch BGA  
6 mm x 8 mm Fine Pitch BGA  
6 mm x 8 mm Fine Pitch BGA  
6 mm x 8 mm Fine Pitch BGA  
6 mm x 8 mm Fine Pitch BGA  
Commercial  
Commercial  
Commercial  
Commercial  
Industrial  
8 ns  
10 ns  
12 ns  
6 ns  
8 ns  
Industrial  
10 ns  
12 ns  
Industrial  
Industrial  
* Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:  
GS71116ATP-10T  
Rev: 1.03 3/2002  
14/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS71116ATP/J/U  
1Mb Asynchronous Datasheet Revision History  
Rev. Code: Old;  
New  
Types of Changes  
Format or Content  
Page #/Revisions/Reason  
• Creation of new datasheet  
71116A_r1  
• Added 6 ns speed bin to entire document  
71116A_r1; 71116_r1_01  
Content  
Content  
• Updated all power numbers  
• Changed 6 mm x 10 mm FPBGA package designator from U to X  
71116A_r1_01; 71116A  
_r1_02  
• Updated Recommended Operating Conditions table on page 4  
• Changed FPBGA package from 6 x 10 to 6 x 8 (package U)  
• Updated Read Cycle AC Characteristics table  
71116A_r1_02; 71116A  
_r1_03  
Content  
Rev: 1.03 3/2002  
15/15  
© 2001, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

相关型号：

GS71116AJ-7

 1Mb Asynchronous SRAM
ETC

GS71116AJ-7I

 1Mb Asynchronous SRAM
ETC

GS71116AJ-7IT

 Standard SRAM, 64KX16, 7ns, CMOS, PDSO44, 0.400 INCH, SOJ-44
GSI

GS71116AJ-7T

 Standard SRAM, 64KX16, 7ns, CMOS, PDSO44, 0.400 INCH, SOJ-44
GSI

GS71116AJ-8

 1Mb Asynchronous SRAM
ETC

GS71116AJ-8I

 1Mb Asynchronous SRAM
ETC

GS71116AJ-8IT

 Standard SRAM, 64KX16, 8ns, CMOS, PDSO44, 0.400 INCH, SOJ-44
GSI

GS71116ATJ

 1Mb Asynchronous SRAM
ETC

GS71116ATP

 1Mb Asynchronous SRAM
ETC

GS71116ATP-10

 Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44
GSI

GS71116ATP-10I

 Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44
GSI

GS71116ATP-10T

 Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44
GSI
©2020 ICPDF网 联系我们和版权申明