GS71208TP-8 [GSI]
128K x 8 1Mb Asynchronous SRAM; 128K ×8 1Mb的SRAM的异步
| 型号： | GS71208TP-8 |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | 128K x 8 1Mb Asynchronous SRAM |
| 文件： | 总11页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS71208TP
8 ns
TSOP
Commercial Temp
Industrial Temp
128K x 8
3.3 V V
DD
1Mb Asynchronous SRAM
Center V and V
DD
SS
TSOP-II 128K x 8-Pin Configuration
Features
• Fast access time: 8 ns
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
A3
A4
• CMOS low power operation: 150 mA at minimum cycle time
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
2
A2
A5
3
A1
A6
4
A0
A7
5
CE
DQ1
DQ2
OE
DQ8
DQ7
32-pin
6
7
400 mil TSOP II
TP: 400 mil, 32-pin TSOP Type II package
8
V
V
V
V
DD
SS
SS
9
DD
10
11
12
13
14
15
16
DQ3
DQ4
WE
A16
A15
A14
A13
DQ6
DQ5
A8
Description
The GS71208 is a high speed CMOS Static RAM organized as
131,072 words by 8 bits. Static design eliminates the need for
external clocks or timing strobes. The GS operates on a single
3.3 V power supply and all inputs and outputs are TTL-com-
patible. The GS71208 is available in a 400 mil TSOP Type-II
package.
A9
A10
A11
A12
Pin Descriptions
Symbol
A0–A16
DQ1–DQ8
CE
Description
Address input
Data input/output
Chip enable input
Write enable input
Output enable input
+3.3 V power supply
WE
OE
VDD
VSS
NC
Ground
No connect
Rev: 1.03 10/2001
1/11
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71208TP
Block Diagram
A0
Row
Decoder
Memory Array
Address
Input
Buffer
Column
Decoder
A16
CE
WE
OE
I/O Buffer
Control
DQ8
DQ1
Truth Table
V
Current
CE
OE
WE
DQ1 to DQ8
DD
H
L
L
L
X
L
X
H
L
Not Selected
Read
ISB1, ISB2
X
H
Write
IDD
H
High Z
Note: X: “H” or “L”
Rev: 1.03 10/2001
2/11
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71208TP
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
VDD
–0.5 to +4.6
V
–0.5 to VDD +0.5
(£ 4.6 V max.)
Input Voltage
VIN
V
V
–0.5 to VDD +0.5
(£ 4.6 V max.)
Output Voltage
VOUT
Allowable power dissipation
Storage temperature
PD
0.7
W
oC
TSTG
–55 to 150
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec-
ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Recommended Operating Conditions
Parameter
Supply Voltage for -8
Input High Voltage
Input Low Voltage
Symbol
Min
3.135
2.0
Typ
3.3
—
Max
3.6
Unit
VDD
V
V
V
VDD +0.3
0.8
VIH
VIL
–0.3
—
Ambient Temperature,
Commercial Range
oC
oC
TAc
TAI
0
—
—
70
85
Ambient Temperature,
Industrial Range
–40
Note:
1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Capacitance
Parameter
Symbol
CIN
Test Condition
VIN = 0 V
Max
Unit
pF
Input Capacitance
Output Capacitance
5
7
COUT
VOUT = 0 V
pF
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
Rev: 1.03 10/2001
3/11
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71208TP
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage
Current
VIN = 0 to VDD
IIL
–1 uA
1 uA
Output High Z
VOUT = 0 to VDD
Output Leakage
Current
ILO
–1 uA
1 uA
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = –4mA
2.4
—
ILO = +4mA
—
0.4 V
Power Supply Currents
0 to 70°C
8 ns
–40 to 85°C
Parameter
Symbol
Test Conditions
8 ns
CE £ VIL
Operating
Supply
Current
All other inputs
³ VIH or £ VIL
Min. cycle time
IOUT = 0 mA
IDD (max)
150 mA
160 mA
CE ³ VIH
Standby
Current
All other inputs
³ VIH or £VIL
Min. cycle time
ISB1 (max)
ISB2 (max)
55 mA
15 mA
65 mA
25 mA
CE ³ VDD – 0.2 V
All other inputs
³ VDD – 0.2 V or £ 0.2 V
Standby
Current
Rev: 1.03 10/2001
4/11
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71208TP
AC Test Conditions
Output Load 1
Parameter
Input high level
Input low level
Conditions
VIH = 2.4 V
VIL = 0.4 V
tr = 1 V/ns
tf = 1 V/ns
1.4 V
DQ
30pF1
50W
Input rise time
VT = 1.4 V
Input fall time
Input reference level
Output reference level
Output load
Output Load 2
1.4 V
3.3 V
Fig. 1& 2
589W
434W
DQ
Note:
5pF1
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
AC Characteristics
Read Cycle
-8
Parameter
Symbol
Unit
Min
8
Max
Read cycle time
tRC
tAA
tAC
tOE
tOH
—
8
ns
ns
ns
ns
ns
ns
Address access time
—
—
—
3
Chip enable access time (CE)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
8
3.5
—
—
*
3
tLZ
*
Output enable to output in low Z (OE)
Chip disable to output in High Z (CE)
0
—
4
ns
ns
ns
tOLZ
*
—
—
tHZ
*
Output disable to output in High Z (OE)
3.5
tOHZ
* These parameters are sampled and are not 100% tested
Rev: 1.03 10/2001
5/11
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71208TP
Read Cycle 1: CE = OE = V , WE = V
IL
IH
tRC
Address
Data Out
tAA
tOH
Previous Data
Data valid
Read Cycle 2: WE = V
IH
tRC
Address
CE
tAA
tAC
tHZ
tLZ
OE
tOE
tOHZ
tOLZ
DATA VALID
Data Out
High impedance
Rev: 1.03 10/2001
6/11
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71208TP
Write Cycle
-8
Parameter
Symbol
Unit
Min
8
Max
—
—
—
—
—
—
—
—
—
—
Write cycle time
Address valid to end of write
Chip enable to end of write
Data set up time
tWC
tAW
tCW
tDW
tDH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
5.5
4
Data hold time
0
Write pulse width
tWP
tAS
5.5
0
Address set up time
Write recovery time (WE)
Write recovery time (CE)
Output Low Z from end of write
tWR
tWR1
0
0
tWLZ*
tWHZ*
3
Write to output in High Z
—
3.5
ns
* These parameters are sampled and are not 100% tested
Rev: 1.03 10/2001
7/11
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71208TP
Write Cycle 1: WE control
tWC
Address
tAW
tWR
OE
tCW
CE
tAS
tWP
WE
tDW
tDH
DATA VALID
Data In
Data Out
tWHZ
tWLZ
HIGH IMPEDANCE
Write Cycle 2: CE control
tWC
Address
tAW
tWR1
OE
CE
tAS
tCW
tWP
WE
tDW
tDH
DATA VALID
Data In
Data Out
HIGH IMPEDANCE
Rev: 1.03 10/2001
8/11
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71208TP
32-Pin TSOP-II, 400mil
Dimension in inch
Dimension in mm
D
c
Symbol
32
min
nom
—
max
min
—
nom
—
max
1.27
0.15
1.14
0.45
0.16
A
A1
A2
b
0.039
0.002
0.037
0.012
0.05
0.006
0.045
0.018
—
0.01
0.90
0.30
—
A
0.040
0.016
1.02
0.40
0.13
c
0.0047 0.0051 0.0062 0.12
1
ZD
D
0.820
—
0.825
0.037
0.463
0.400
0.05
0.020
0.031
—
0.830 20.82 20.95 21.08
0.95
e
b
ZD
E
—
—
—
0.455
0.395
—
0.471 11.56 11.76 11.96
0.405 10.03 10.16 10.29
E1
e
y
—
—
1.27
0.50
0.80
—
—
L
0.017
0.024
0.00
0.023
0.039
0.003
0.40
0.60
0.00
0.60
1.00
0.76
L1
y
Q
Detail A
0o
5o
0o
5o
Q
—
—
Note:
1.Dimension D includes mold flash, protrusions or gate burrs.
2. Dimension E does not include interlead flash.
3. Controlling dimension: mm
Rev: 1.03 10/2001
9/11
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71208TP
Ordering Information
*
Package
Access Time
Temp. Range
Status
Part Number
GS71208TP-8
400 mil TSOP-II
8 ns
Commercial
* Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:
GS71208TP-8T
Rev: 1.03 10/2001
10/11
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71208TP
Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content
Page #/Revisions/Reason
1. Added TP package to 71208
1.00 12/1999/1.01 12/1999
Content
• GSI LogoAdded Dimension D to 32 pin 400 ml TSOP II Package.
GS71208Rev1.01 12/1999KRev
1.01 2/2000L
Format/Content
• Updated format to comply with Technical Publications standard
• Specifically noted that numbers in Power Supply Currents table are worst
case scenario
71208_r1_01; 71208_r1_02
71208_r1_02; 71208_r1_03
Format/Content
Content
• Removed all references to other parts except 71208TP-8
Rev: 1.03 10/2001
11/11
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
相关型号：
©2020 ICPDF网 联系我们和版权申明