GS72116AGP-8I [GSI]
Standard SRAM, 128KX16, 8ns, CMOS, PDSO44, 0.400 INCH, ROHS COMPLIANT, TSOP2-44;
| 型号： | GS72116AGP-8I |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Standard SRAM, 128KX16, 8ns, CMOS, PDSO44, 0.400 INCH, ROHS COMPLIANT, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总13页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS72116AGP/U
7, 8, 10, 12 ns
TSOP, FP-BGA
Commercial Temp
Industrial Temp
128K x 16
2Mb Asynchronous SRAM
3.3 V V
DD
Center V and V
DD
SS
Features
Fine Pitch BGA 128K x 16-Bump Configuration
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
1
2
3
4
5
6
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
A
B
C
D
E
F
LB
OE
A0
A3
A1
A4
A6
A7
A2
NC
DQ16 UB
CE DQ1
DQ2 DQ3
DQ14 DQ15 A5
VSS
VDD
VDD
VSS
DQ13 NC
DQ12 NC
DQ4
GP: RoHS-compliant 400 mil, 44-pin TSOP Type II
package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
GU: RoHS-compliant 6 mm x 8 mm Fine Pitch Ball Grid
Array package
A16 DQ5
DQ11 DQ10 A8
A9
DQ7 DQ6
WE DQ8
G
H
DQ9 NC
NC A12
A10
A13
A11
A14
Description
A15
NC
The GS72116A is a high speed CMOS Static RAM organized
as 131,072 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS72116A is available in a 6 mm x 8 mm
Fine Pitch BGA and 400 mil TSOP Type-II packages.
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Package U
TSOP-II 128K x 16-Pin Configuration
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A4
A3
A5
Pin Descriptions
2
A6
3
A2
A7
Symbol
A0–A16
Description
Address input
4
A1
OE
Top view
5
A0
UB
6
CE
LB
DQ1–DQ16
CE
Data input/output
Chip enable input
7
DQ1
DQ2
DQ3
DQ4
VDD
DQ16
DQ15
DQ14
8
9
Lower byte enable input
(DQ1 to DQ8)
10
11
12
13
14
15
LB
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
44-pin
Upper byte enable input
(DQ9 to DQ16)
VSS
UB
TSOP II
DQ5
DQ6
DQ7
DQ8
WE
WE
OE
Write enable input
Output enable input
+3.3 V power supply
16
17
18
V
DD
A15
A14
A13
A12
A16
A8
V
Ground
19
20
21
22
SS
A9
A10
A11
NC
No connect
NC
Package TP
Rev: 1.11 1/2013
1/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116AGP/U
Block Diagram
A0
Row
Decoder
Memory Array
Address
Input
Buffer
Column
Decoder
A16
CE
WE
OE
I/O Buffer
Control
_____
UB
DQ16
DQ1
Truth Table
CE
OE
WE
LB
X
L
UB
X
DQ1 to DQ8
DQ9 to DQ16
Not Selected
Read
VDD Current
H
X
X
Not Selected
Read
ISB1, ISB2
L
L
L
L
H
L
L
H
L
Read
High Z
H
L
High Z
Read
L
Write
Write
IDD
X
L
H
L
Write
Not Write, High Z
Write
H
X
H
Not Write, High Z
High Z
L
L
H
X
H
X
X
High Z
H
High Z
High Z
Note:
X: “H” or “L”
Rev: 1.11 1/2013
2/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116AGP/U
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
VDD
–0.5 to +4.6
V
–0.5 to V +0.5
DD
Input Voltage
VIN
V
(≤ 4.6 V max.)
–0.5 to V +0.5
DD
Output Voltage
VOUT
V
(≤ 4.6 V max.)
Allowable power dissipation
Storage temperature
PD
0.7
W
o
TSTG
–55 to 150
C
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage for -7/-8/-10/12
Input High Voltage
Symbol
Min
3.0
Typ
3.3
—
Max
Unit
V
3.6
V
V
V
DD
V
+0.3
VIH
VIL
2.0
DD
Input Low Voltage
–0.3
—
0.8
Ambient Temperature,
Commercial Range
o
TAc
TAI
0
—
—
70
85
C
Ambient Temperature,
Industrial Range
o
–40
C
Notes:
1. Input overshoot voltage should be less than V +2 V and not exceed 20 ns.
DD
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Capacitance
Parameter
Input Capacitance
Output Capacitance
Symbol
CIN
Test Condition
Max
Unit
pF
VIN = 0 V
5
7
COUT
VOUT = 0 V
pF
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
Rev: 1.11 1/2013
3/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116AGP/U
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
VIN = 0 to V
DD
Input Leakage Current
IIL
– 1 uA
1 uA
Output High Z
Output Leakage Current
ILO
–1 uA
1 uA
VOUT = 0 to V
DD
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = –4mA
2.4
—
ILO = +4mA
—
0.4 V
Power Supply Currents
0 to 70°C
–40 to 85°C
Parameter
Symbol
Test Conditions
7 ns
8 ns
10 ns
12 ns
7 ns
8 ns
10 ns
12 ns
CE ≤ VIL
Operating
Supply
Current
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
IOUT = 0 mA
IDD (max)
145 mA
125 mA
100 mA
85 mA
150 mA
30 mA
130 mA
25 mA
105 mA
90 mA
CE ≥ VIH
Standby
Current
All other inputs
≥ VIH or ≤VIL
Min. cycle time
ISB1 (max)
ISB2 (max)
25 mA
20 mA
20 mA
15 mA
25 mA
20 mA
CE ≥ VDD – 0.2 V
All other inputs
≥ VDD – 0.2 V or
Standby
Current
5 mA
10 mA
≤ 0.2 V
Rev: 1.11 1/2013
4/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116AGP/U
AC Test Conditions
Output Load 1
Parameter
Input high level
Input low level
Conditions
VIH = 2.4 V
VIL = 0.4 V
tr = 1 V/ns
tf = 1 V/ns
1.4 V
DQ
1
30pF
50Ω
Input rise time
VT = 1.4 V
Input fall time
Input reference level
Output reference level
Output load
Output Load 2
1.4 V
3.3 V
Fig. 1& 2
589Ω
434Ω
DQ
Notes:
1
1. Include scope and jig capacitance.
5pF
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
Rev: 1.11 1/2013
5/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116AGP/U
AC Characteristics
Read Cycle
-7
-8
-10
-12
Parameter
Symbol
Unit
Min
7
Max
—
7
Min
8
Max
—
8
Min
10
—
—
—
—
3
Max
—
10
10
4
Min
Max
—
12
12
5
Read cycle time
tRC
tAA
tAC
tAB
tOE
tOH
12
—
—
—
—
3
ns
ns
ns
ns
ns
ns
ns
Address access time
—
—
—
—
3
—
—
—
—
3
Chip enable access time (CE)
Byte enable access time (UB, LB)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
7
8
3
3.5
3.5
—
—
3
4
5
—
—
—
—
—
—
*
3
3
3
3
tLZ
*
Output enable to output in low Z (OE)
Byte enable to output in low Z (UB, LB)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
Byte disable to output in High Z (UB, LB)
0
—
—
3.5
3
0
—
—
4
0
—
—
5
0
—
—
6
ns
ns
ns
ns
ns
tOLZ
*
0
0
0
0
tBLZ
*
—
—
—
—
—
—
—
—
—
—
—
—
tHZ
*
3.5
3.5
4
5
tOHZ
*
3
4
5
tBHZ
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = V , WE = V , UB and, or LB = V
IL
IL
IH
tRC
Address
Data Out
tAA
tOH
Previous Data
Data valid
Rev: 1.11 1/2013
6/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116AGP/U
Read Cycle 2: WE = V
IH
tRC
Address
CE
tAA
tAC
tHZ
tLZ
tAB
UB, LB
OE
tBHZ
tOHZ
tBLZ
tOE
tOLZ
Data valid
Data Out
High impedance
Write Cycle
-7
-8
-10
-12
Parameter
Symbol
Unit
Max
Min
7
Max
—
—
—
—
—
—
—
—
—
—
—
Min
8
Max
Min
10
7
Max
—
—
—
—
—
—
—
—
—
—
—
Min
12
8
Write cycle time
Address valid to end of write
Chip enable to end of write
Byte enable to end of write
Data set up time
tWC
tAW
tCW
tBW
tDW
tDH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5.5
5.5
5.5
4
5
7
8
5
7
8
3.5
0
5
6
Data hold time
0
0
0
Write pulse width
tWP
tAS
5
5.5
0
7
8
Address set up time
0
0
0
Write recovery time (WE)
Write recovery time (CE)
Output Low Z from end of write
tWR
tWR1
0
0
0
0
0
0
0
0
*
3
3
3
3
tWLZ
tWHZ
*
Write to output in High Z
—
3
—
3.5
—
4
—
5
ns
* These parameters are sampled and are not 100% tested.
Rev: 1.11 1/2013
7/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116AGP/U
Write Cycle 1: WE control
tWC
Address
OE
tAW
tCW
tBW
tWR
CE
UB, LB
WE
tAS
tWP
tDW
tDH
Data valid
Data In
tWHZ
tWLZ
High impedance
Data Out
Write Cycle 2: CE control
tWC
Address
OE
tAW
tWR1
tAS
tCW
tBW
CE
UB, LB
WE
tWP
tDW
tDH
Data valid
Data In
Data Out
High impedance
Rev: 1.11 1/2013
8/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116AGP/U
Write Cycle 3: UB, LB control
tWC
Address
OE
tAW
tWR1
tAS
tCW
tBW
CE
UB, LB
WE
tWP
tDW
tDH
Data valid
Data In
Data Out
High impedance
Rev: 1.11 1/2013
9/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116AGP/U
44-Pin, 400 mil TSOP-II
D
Dimension in inch
Dimension in mm
c
44
23
22
Symbol
min
—
nom max
min
nom max
A
A1
A2
B
—
—
0.047
—
—
—
1.20
—
0.002
—
0.05
A
0.037 0.039 0.041 0.95
0.01 0.014 0.018 0.25
1.00
0.35
0.15
1.05
0.45
—
c
—
0.006
—
—
1
D
0.721 0.725 0.729 18.31 18.41 18.51
0.396 0.400 0.404 10.06 10.16 10.26
e
B
E
e
—
0.031
—
—
0.80
—
HE
L
0.455 0.463 0.471 11.56 11.76 11.96
y
0.016 0.020 0.024 0.40
0.50
0.80
—
0.60
—
L1
y
—
—
0.031
—
—
—
—
0.004
0.10
Q
Detail A
o
o
o
o
Q
—
—
0
5
0
5
Notes:
1. Dimension D& E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Controlling dimension: mm
Rev: 1.11 1/2013
10/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116AGP/U
6 mm x 8 mm Fine Pitch BG
8 . 0 0 ± 0 . 1 0
0.10
5 . 2 5
Rev: 1.11 1/2013
11/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116AGP/U
Ordering Information
*
Package
Access Time
Temp. Range
Part Number
GS72116AGP-7
GS72116AGP-8
GS72116AGP-10
GS72116AGP-12
GS72116AGP-7I
GS72116AGP-8I
GS72116AGP-10I
GS72116AGP-12I
GS72116AU-7
RoHS-compliant 400 mil TSOP-II
RoHS-compliant 400 mil TSOP-II
7 ns
8 ns
Commercial
Commercial
Commercial
Commercial
Industrial
RoHS-compliant 400 mil TSOP-II
10 ns
12 ns
7 ns
RoHS-compliant 400 mil TSOP-II
RoHS-compliant 400 mil TSOP-II
RoHS-compliant 400 mil TSOP-II
8 ns
Industrial
RoHS-compliant 400 mil TSOP-II
10 ns
12 ns
7 ns
Industrial
RoHS-compliant 400 mil TSOP-II
Industrial
6 mm x 8 mm Fine Pitch BGA
Commercial
Commercial
Commercial
Commercial
Industrial
GS72116AU-8
6 mm x 8 mm Fine Pitch BGA
8 ns
GS72116AU-10
GS72116AU-12
GS72116AU-7I
GS72116AU-8I
GS72116AU-10I
GS72116AU-12I
GS72116AGU-7
GS72116AGU-8
GS72116AGU-10
GS72116AGU-12
GS72116AGU-7I
GS72116AGU-8I
GS72116AGU-10I
6 mm x 8 mm Fine Pitch BGA
10 ns
12 ns
7 ns
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
8 ns
Industrial
6 mm x 8 mm Fine Pitch BGA
10 ns
12 ns
7 ns
Industrial
6 mm x 8 mm Fine Pitch BGA
Industrial
RoHS-compliant 6 mm x 8 mm Fine Pitch BGA
RoHS-compliant 6 mm x 8 mm Fine Pitch BGA
RoHS-compliant 6 mm x 8 mm Fine Pitch BGA
RoHS-compliant 6 mm x 8 mm Fine Pitch BGA
RoHS-compliant 6 mm x 8 mm Fine Pitch BGA
RoHS-compliant 6 mm x 8 mm Fine Pitch BGA
RoHS-compliant 6 mm x 8 mm Fine Pitch BGA
RoHS-compliant 6 mm x 8 mm Fine Pitch BGA
Commercial
Commercial
Commercial
Commercial
Industrial
8 ns
10 ns
12 ns
7 ns
8 ns
Industrial
10 ns
12 ns
Industrial
GS72116AGU-12I
Industrial
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS72116GP-8T.
Rev: 1.11 1/2013
12/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116AGP/U
2Mb Asynchronous Datasheet Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content
Revisions
• Creation of new datasheet
72116A_r1
• Added 6 ns speed bin to entire document
• Updated all power numbers
72116A_r1; 72116A_r1_01
Content
Content
72116A_r1_01; 72116A_r1_02
• Changed 6 mm x 10 mm FP_BGA package designator from U to X
• Updated Recommended Operating Conditions table on page 5
• Removed 15 ns bin
72116A_r1_02; 72116A_r1_03
Content
• Changed FPBGA package from 6 x 10 to 6 x 8 (package U)
• Removed 6 ns speed bin from entire document
• Added 7 ns speed bin to entire document
72116A_r1_03; 72116A_r1_04
72116A_r1_04; 72116A_r1_05
72116A_r1_05; 72116A_r1_06
Content
Content
• Corrected title of 6 x 8 FPBGA mechanical drawing
• Updated format
• Added RoHS-compliant information for TSOP-II package
Content/Format
• Added RoHS-compliant information for TQFP and FP-BGA packages
• Added RoHS-compliant 400 mil SOJ
72116A_r1_06; 72116A_r1_07
72116A_r1_07; 72116A_r1_08
Content
Content
• Updated to MP in ordering information table
• Removed Status Column from Ordering Information table, removed
references to SOJ
72116A_r1_08; 72116A_r1_09
Content
• Removed TQFP refereneces (part is EOL)
72116A_r1_09; 72116A_r1_10
72116A_r1_10; 72116A_r1_11
Content
Content
• Removed 5/6-RoHS TSOP-II refereneces (part is EOL)
Rev: 1.11 1/2013
13/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
相关型号：
GS72116AGU-10
Standard SRAM, 128KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 0.75 MM PITCH, ROHS COMPLIANT, FBGA-48
GSI
GS72116AGU-10IT
Standard SRAM, 128KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 0.75 MM PITCH, ROHS COMPLIANT, FBGA-48
GSI
GS72116AGU-10T
Standard SRAM, 128KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 0.75 MM PITCH, ROHS COMPLIANT, FBGA-48
GSI
©2020 ICPDF网 联系我们和版权申明