GS72116AU-12I [GSI]
128K x 16 2Mb Asynchronous SRAM; 128K ×16的2Mb SRAM的异步
| 型号： | GS72116AU-12I |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | 128K x 16 2Mb Asynchronous SRAM |
| 文件： | 总18页 (文件大小：491K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS72116ATP/J/T/U
SOJ, TSOP, FP-BGA, TQFP
Commercial Temp
7, 8, 10, 12 ns
3.3 V VDD
128K x 16
Industrial Temp
2Mb Asynchronous SRAM
Center VDD and VSS
Features
SOJ 128K x 16-Pin Configuration
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
A4
A3
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A6
2
• Single 3.3 V power supply
A2
A7
3
• All inputs and outputs are TTL-compatible
• Byte control
A1
OE
4
Top view
A0
UB
5
• Fully static operation
CE
LB
6
• Industrial Temperature Option: –40° to 85°C
• Package line up
DQ1
DQ2
DQ3
DQ4
VDD
DQ16
DQ15
DQ14
7
8
J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
T: 10 mm x 10 mm, 44-pin TQFP
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
9
10
11
12
13
14
15
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
44-pin
SOJ
VSS
DQ5
DQ6
DQ7
DQ8
WE
Description
16
17
18
The GS72116A is a high speed CMOS Static RAM organized
as 131,072 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a sin-
gle 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS72116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as
well as in 400 mil SOJ and 400 mil TSOP Type-II packages.
A15
A14
A13
A12
A16
A8
A9
19
20
21
22
A10
A11
NC
Package J
Pin Descriptions
Symbol
A0–A16
Description
Address input
DQ1–DQ16
CE
Data input/output
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
LB
Upper byte enable input
(DQ9 to DQ16)
UB
WE
OE
Write enable input
Output enable input
+3.3 V power supply
V
DD
V
Ground
SS
NC
No connect
Rev: 1.04a 10/2002
1/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin TQFP 128K x 16-Pin Configuration
A16 A15 A14 A13 A12 A11 A10 A9 OE UB LB
44 43 42 41 40 39 38 37 36 35 34
CE
DQ1
DQ2
DQ3
DQ4
VDD
DQ16
DQ15
DQ14
DQ13
VSS
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
VDD
6
VSS
7
DQ12
DQ11
DQ10
DQ9
NC
DQ5
DQ6
DQ7
DQ8
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
WE A0 A1 A2 A3 A4 NC A5 A6 A7 A8
Package T
Fine Pitch BGA 128K x 16-Bump Configuration
1
2
3
4
5
6
A
B
C
D
E
F
LB
OE
A0
A3
A1
A4
A6
A7
A2
NC
DQ16 UB
CE DQ1
DQ2 DQ3
DQ14 DQ15 A5
VSS
VDD
VDD
VSS
DQ13 NC
DQ12 NC
DQ4
A16 DQ5
DQ11 DQ10 A8
A9
DQ7 DQ6
WE DQ8
G
H
DQ9 NC
NC A12
A10
A13
A11
A14
A15
NC
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Package U
Rev: 1.04a 10/2002
2/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
TSOP-II 128K x 16-Pin Configuration
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A4
A3
A5
2
A6
3
A2
A7
4
A1
OE
Top view
5
A0
UB
6
CE
LB
7
DQ1
DQ2
DQ3
DQ4
VDD
DQ16
DQ15
DQ14
8
9
10
11
12
13
14
15
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
44-pin
VSS
TSOP II
DQ5
DQ6
DQ7
DQ8
WE
16
17
18
A15
A14
A13
A12
A16
A8
19
20
21
22
A9
A10
A11
NC
Package TP
Block Diagram
A0
Row
Decoder
Memory Array
Address
Input
Buffer
Column
Decoder
A16
CE
WE
OE
UB
LB
I/O Buffer
Control
_____
_____
DQ16
DQ1
Rev: 1.04a 10/2002
3/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Truth Table
CE
OE
WE
LB
X
L
UB
X
DQ1 to DQ8
Not Selected
Read
DQ9 to DQ16
Not Selected
Read
VDD Current
H
X
X
ISB1, ISB2
L
L
L
L
H
L
L
H
L
Read
High Z
H
L
High Z
Read
L
Write
Write
IDD
X
L
H
L
Write
Not Write, High Z
Write
H
X
H
Not Write, High Z
High Z
L
L
H
X
H
X
X
High Z
H
High Z
High Z
Note: X: “H” or “L”
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
VDD
–0.5 to +4.6
V
–0.5 to V +0.5
DD
Input Voltage
VIN
V
(≤ 4.6 V max.)
–0.5 to V +0.5
DD
Output Voltage
VOUT
V
(≤ 4.6 V max.)
Allowable power dissipation
Storage temperature
PD
0.7
W
o
TSTG
–55 to 150
C
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec-
ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Rev: 1.04a 10/2002
4/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Recommended Operating Conditions
Parameter
Supply Voltage for -7/-8/-10/12
Input High Voltage
Symbol
Min
3.0
Typ
3.3
—
Max
Unit
V
3.6
V
V
V
DD
V
+0.3
VIH
VIL
2.0
DD
Input Low Voltage
–0.3
—
0.8
Ambient Temperature,
Commercial Range
o
TAc
0
—
—
70
85
C
Ambient Temperature,
Industrial Range
o
TAI
–40
C
Note:
1. Input overshoot voltage should be less than V +2 V and not exceed 20 ns.
DD
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Capacitance
Parameter
Input Capacitance
Output Capacitance
Symbol
CIN
Test Condition
VIN = 0 V
Max
Unit
pF
5
7
COUT
VOUT = 0 V
pF
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage
Current
VIN = 0 to V
DD
IIL
– 1 uA
–1 uA
1 uA
1 uA
Output High Z
Output Leakage
Current
ILO
VOUT = 0 to V
DD
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = –4mA
2.4
—
ILO = +4mA
—
0.4 V
Rev: 1.04a 10/2002
5/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Power Supply Currents
0 to 70°C
8 ns 10 ns 12 ns
–40 to 85°C
8 ns 10 ns
Parameter Symbol Test Conditions
7 ns
7 ns
12 ns
CE ≤ VIL
Operating
Supply
Current
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
IOUT = 0 mA
IDD (max)
145 mA 125 mA 100 mA 85 mA 150 mA 130 mA 105 mA 90 mA
CE ≥ VIH
Standby
Current
ISB1
(max)
All other inputs
≥ VIH or ≤VIL
Min. cycle time
25 mA
20 mA
20 mA
15 mA
30 mA
25 mA
25 mA
20 mA
CE ≥ VDD – 0.2 V
Standby
Current
ISB2
(max)
All other inputs
5 mA
10 mA
≥ VDD – 0.2 V or
≤ 0.2 V
AC Test Conditions
Output Load 1
Parameter
Input high level
Input low level
Input rise time
Input fall time
Conditions
VIH = 2.4 V
VIL = 0.4 V
tr = 1 V/ns
tf = 1 V/ns
1.4 V
DQ
1
30pF
50Ω
VT = 1.4 V
Input reference level
Output reference level
Output load
Output Load 2
1.4 V
3.3 V
Fig. 1& 2
589Ω
434Ω
DQ
Note:
1. Include scope and jig capacitance.
1
5pF
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
Rev: 1.04a 10/2002
6/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
AC Characteristics
Read Cycle
-7
-8
-10
-12
Parameter
Symbol
Unit
Min
7
Max
—
7
Min
8
Max
—
8
Min
10
—
—
—
—
3
Max
—
10
10
4
Min
12
—
—
—
—
3
Max
—
12
12
5
Read cycle time
tRC
tAA
tAC
tAB
tOE
tOH
ns
ns
ns
ns
ns
ns
ns
Address access time
—
—
—
—
3
—
—
—
—
3
Chip enable access time (CE)
Byte enable access time (UB, LB)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
7
8
3
3.5
3.5
—
—
3
4
5
—
—
—
—
—
—
*
3
3
3
3
tLZ
*
Output enable to output in low Z (OE)
Byte enable to output in low Z (UB, LB)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
Byte disable to output in High Z (UB, LB)
0
—
—
3.5
3
0
—
—
4
0
—
—
5
0
—
—
6
ns
ns
ns
ns
ns
tOLZ
*
0
0
0
0
tBLZ
*
—
—
—
—
—
—
—
—
—
—
—
—
tHZ
*
3.5
3.5
4
5
tOHZ
*
3
4
5
tBHZ
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = V , WE = V , UB and, or LB = V
IL
IH
IL
tRC
Address
tAA
tOH
Data Out
Previous Data
Data valid
Rev: 1.04a 10/2002
7/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Read Cycle 2: WE = V
IH
tRC
Address
CE
tAA
tAC
tHZ
tLZ
tAB
UB, LB
OE
tBHZ
tOHZ
tBLZ
tOLZ
tOE
Data valid
Data Out
High impedance
Write Cycle
-7
-8
-10
-12
Parameter
Symbol
Unit
Min
7
Max
Min
Max
—
—
—
—
—
—
—
—
—
—
—
Min
10
7
Max
—
—
—
—
—
—
—
—
—
—
—
Min
12
8
Max
—
—
—
—
—
—
—
—
—
—
—
Write cycle time
tWC
tAW
tCW
tBW
tDW
tDH
—
8
5.5
5.5
5.5
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to end of write
Chip enable to end of write
Byte enable to end of write
Data set up time
5
—
—
—
—
—
—
—
—
—
—
5
7
8
5
7
8
3.5
0
5
6
Data hold time
0
0
0
Write pulse width
tWP
tAS
5
5.5
0
7
8
Address set up time
0
0
0
Write recovery time (WE)
Write recovery time (CE)
Output Low Z from end of write
tWR
tWR1
0
0
0
0
0
0
0
0
*
3
3
3
3
tWLZ
tWHZ
*
Write to output in High Z
—
3
—
3.5
—
4
—
5
ns
* These parameters are sampled and are not 100% tested.
Rev: 1.04a 10/2002
8/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Write Cycle 1: WE control
tWC
Address
tAW
tWR
OE
CE
tCW
tBW
UB, LB
WE
tAS
tWP
tDW
tDH
Data valid
Data In
tWHZ
tWLZ
High impedance
Data Out
Write Cycle 2: CE control
tWC
Address
OE
tAW
tWR1
tAS
tCW
tBW
CE
UB, LB
WE
tWP
tDW
tDH
Data valid
Data In
Data Out
High impedance
Rev: 1.04a 10/2002
9/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Write Cycle 3: UB, LB control
tWC
Address
tAW
tWR1
OE
CE
tAS
tCW
tBW
UB, LB
WE
tWP
tDW
tDH
Data valid
Data In
Data Out
High impedance
Rev: 1.04a 10/2002
10/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin, 400 mil SOJ
Dimension in inch
min nom max
Dimension in mm
Symbol
min
nom
max
3.759
—
L
D
A
A1
A2
B
—
0.025
—
—
0.148
—
0.635
—
—
c
44
23
22
—
0.105 0.110 0.115 2.667 2.794 2.921
0.018 0.457
0.026 0.028 0.032 0.660 0.711 0.813
0.008 0.203
—
—
—
—
B1
c
—
—
—
—
1
D
1.120 1.125 1.130 28.44 28.58 28.70
e
A
E
0.395 0.400 0.405 10.033 10.160 10.287
e
—
0.05
—
—
1.27
—
HE
GE
L
0.435 0.440 0.445 11.049 11.176 11.303
B
B1
y
0.360 0.370 0.380 9.144 9.398 9.652
Q
0.082 0.087 0.106 2.083 2.210
2.70
Detail A
y
—
—
—
0.004
—
—
—
0.102
o
o
o
o
Q
0
7
0
7
Note:
1. Dimension D& E do not include interlead flash.
2. Dimension B1 does not include dambar protrusion/intrusion.
3. Controlling dimension: inches
Rev: 1.04a 10/2002
11/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin, 400 mil TSOP-II
Dimension in inch
Dimension in mm
Symbol
min
nom max
min
nom max
D
c
44
23
22
A
A1
A2
B
—
0.002
—
—
0.047
—
0.05
—
—
1.20
—
—
0.037 0.039 0.041 0.95
0.01 0.014 0.018 0.25
1.00
0.35
0.15
1.05
0.45
—
A
c
—
0.006
—
—
D
0.721 0.725 0.729 18.31 18.41 18.51
1
E
0.396 0.400 0.404 10.06 10.16 10.26
e
B
e
—
0.031
—
—
0.80
—
HE
L
0.455 0.463 0.471 11.56 11.76 11.96
0.016 0.020 0.024 0.40
0.50
0.80
—
0.60
—
y
L1
y
—
—
0.031
—
—
0.004
—
—
0.10
o
o
o
o
Q
—
—
0
5
0
5
Q
Detail A
Note:
1. Dimension D& E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Controlling dimension: mm
Rev: 1.04a 10/2002
12/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44-Pin TQFP (LQFP) Package
D1
A2
A1
E1
L1
C
e
b
Body Size
Standoff
Body Thickness
Lead Length
Lead Width
Lead Thickness
Lead Pitch
Lead Count
E1
D1
A1
A2
L1
b
c
e
10
10
44
0.1
1.4
1.0
0.3
0.127
0.8
Units: mm
Rev: 1.04a 10/2002
13/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
44 Pin TQFP (LQFP) Package
D1
A2
A1
E1
L1
C
e
b
Body Size
E1 D1
Standoff Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch
Lead Count
A1
A2
L1
b
c
e
10
10
44
0.1
1.4
1.0
0.3
0.127
0.8
Units: mm
Rev: 1.04a 10/2002
14/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
6 mm x 10 mm Fine Pitch BGA
8 . 0 0 ± 0 . 1 0
0.10
5 . 2 5
Rev: 1.04a 10/2002
15/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Ordering Information
*
Package
Access Time
Temp. Range
Status
Part Number
GS72116ATP-7
GS72116ATP-8
GS72116ATP-10
GS72116ATP-12
GS72116ATP-7I
GS72116ATP-8I
GS72116ATP-10I
GS72116ATP-12I
GS72116AJ-7
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil SOJ
7 ns
8 ns
Commercial
Commercial
Commercial
Commercial
Industrial
10 ns
12 ns
7 ns
8 ns
Industrial
10 ns
12 ns
7 ns
Industrial
Industrial
Commercial
Commercial
Commercial
Commercial
Industrial
GS72116AJ-8
400 mil SOJ
8 ns
GS72116AJ-10
GS72116AJ-12
GS72116AJ-7I
GS72116AJ-8I
GS72116AJ-10I
GS72116AJ-12I
GS72116AT-7
400 mil SOJ
10 ns
12 ns
7 ns
400 mil SOJ
400 mil SOJ
400 mil SOJ
8 ns
Industrial
400 mil SOJ
10 ns
12 ns
7 ns
Industrial
400 mil SOJ
Industrial
44-pin TQFP
44-pin TQFP
44-pin TQFP
44-pin TQFP
44-pin TQFP
44-pin TQFP
44-pin TQFP
44-pin TQFP
Commercial
Commercial
Commercial
Commercial
Industrial
GS72116AT-8
8 ns
GS72116AT-10
GS72116AT-12
GS72116AT-7I
GS72116AT-8I
GS72116AT-10I
GS72116AT-12I
10 ns
12 ns
7 ns
8 ns
Industrial
10 ns
12 ns
Industrial
Industrial
Rev: 1.04a 10/2002
16/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
Ordering Information
*
Package
Access Time
Temp. Range
Status
Part Number
GS72116AU-7
GS72116AU-8
GS72116AU-10
GS72116AU-12
GS72116AU-7I
GS72116AU-8I
GS72116AU-10I
GS72116AU-12I
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
7 ns
8 ns
Commercial
Commercial
Commercial
Commercial
Industrial
10 ns
12 ns
7 ns
8 ns
Industrial
10 ns
12 ns
Industrial
Industrial
*
Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:
GS72116ATP-8T
Rev: 1.04a 10/2002
17/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS72116ATP/J/T/U
2Mb Asynchronous Datasheet Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content
Page #/Revisions/Reason
• Creation of new datasheet
72116A_r1
• Added 6 ns speed bin to entire document
72116A_r1; 72116A_r1_01
Content
Content
• Updated all power numbers
• Changed 6 mm x 10 mm FP_BGA package designator from U to X
72116A_r1_01; 72116A_r1_02
• Updated Recommended Operating Conditions table on page 5
• Removed 15 ns bin
• Changed FPBGA package from 6 x 10 to 6 x 8 (package U)
72116A_r1_02; 72116A_r1_03
72116A_r1_03; 72116A_r1_04
Content
Content
• Removed 6 ns speed bin from entire document
• Added 7 ns speed bin to entire document
Rev: 1.04a 10/2002
18/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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