GS74108ATP-7I [GSI]
Standard SRAM, 512KX8, 7ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44;型号: | GS74108ATP-7I |
厂家: | GSI TECHNOLOGY |
描述: | Standard SRAM, 512KX8, 7ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
文件: | 总13页 (文件大小:404K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
GS74108ATP/J/X
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
7, 8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
512K x 8
4Mb Asynchronous SRAM
SOJ 512K x 8-Pin Configuration
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 135/120/95/85 mA at minimum
cycle time
36
1
A4
NC
35
A5
2
A3
34
A6
3
A2
• Single 3.3 V power supply
33
A7
4
A1
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
32
A8
5
A0
31
6
CE
OE
30
7
DQ1
DQ2
VDD
VSS
DQ3
DQ4
WE
A17
A16
A15
A14
A13
DQ8
J: 400 mil, 36-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
X: 6 mm x 10 mm Fine Pitch Ball Grid Array
package
29
8
DQ7
36-pin
400 mil SOJ
28
9
VSS
27
26
25
24
23
22
21
20
19
10
11
12
13
14
15
16
17
18
VDD
DQ6
DQ5
A9
Description
The GS74108A is a high speed CMOS Static RAM organized
as 524,288 words by 8 bits. Static design eliminates the need
for external clocks or timing strobes. The GS74108A operates
on a single 3.3 V power supply and all inputs and outputs are
TTL-compatible. The GS74108A is available in 400 mil SOJ,
400 mil TSOP Type-II, and 6 mm x 10 mm FP-BGA packages.
A10
A11
A12
A18
NC
FP-BGA 512K x 8 Bump Configuration (Package X)
Pin Descriptions
1
2
3
4
5
6
Symbol
A0–A18
DQ1–DQ8
CE
Description
Address input
A
B
C
D
E
F
NC
OE
A2
A1
A6
A5
A7
NC
Data input/output
Chip enable input
Write enable input
Output enable input
+3.3 V power supply
DQ1 NC
DQ2 NC
CE DQ8
NC DQ7
WE
A0
A4
OE
VSS
VDD
NC
NC
A18
A17
A13
A14
A15
A3
NC
NC
VDD
VSS
V
DD
A9
V
Ground
SS
DQ3 NC
DQ4 NC
A10
A11
A12
NC DQ6
WE DQ5
NC
No connect
G
H
NC
A16
A8
NC
6 x 10 mm
Rev: 1.03a 10/2002
1/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108ATP/J/X
TSOP-II 512K x 8-Pin Configuration
NC
NC
A4
1
44
NC
NC
NC
A5
2
43
42
3
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
4
A3
5
A2
A6
6
A1
A7
7
A0
A8
8
CE
OE
DQ8
DQ7
VSS
VDD
DQ6
DQ5
A9
9
DQ1
DQ2
VDD
VSS
DQ3
DQ4
WE
A17
A16
10
11
12
13
14
15
16
17
18
44-pin
400 mil TSOP II
A10
A11
A12
A18
NC
A15
A14
19
20
21
22
A13
NC
NC
24
23
NC
NC
Block Diagram
A0
Row
Decoder
Memory Array
Address
Input
Buffer
Column
Decoder
A18
CE
WE
OE
I/O Buffer
Control
DQ8
DQ1
Rev: 1.03a 10/2002
2/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108ATP/J/X
Truth Table
CE
V
Current
OE
WE
DQ1 to DQ8
DD
H
L
L
L
X
L
X
H
L
Not Selected
Read
ISB1, ISB2
X
H
Write
IDD
H
High Z
Note: X: “H” or “L”
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
VDD
–0.5 to +4.6
V
–0.5 to V +0.5
DD
Input Voltage
VIN
V
(≤ 4.6 V max.)
–0.5 to V +0.5
DD
Output Voltage
VOUT
V
(≤ 4.6 V max.)
Allowable power dissipation
Storage temperature
PD
0.7
W
o
TSTG
–55 to 150
C
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec-
ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Rev: 1.03a 10/2002
3/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108ATP/J/X
Recommended Operating Conditions
Parameter
Supply Voltage for -7/-8/-10/-12
Input High Voltage
Symbol
Min
3.0
Typ
3.3
—
Max
Unit
V
3.6
V
V
V
DD
V
+0.3
VIH
VIL
2.0
DD
Input Low Voltage
–0.3
—
0.8
Ambient Temperature,
Commercial Range
o
TAc
0
—
—
70
85
C
Ambient Temperature,
Industrial Range
o
TAI
–40
C
Note:
1. Input overshoot voltage should be less than V +2 V and not exceed 20 ns.
DD
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Capacitance
Parameter
Input Capacitance
Output Capacitance
Symbol
CIN
Test Condition
VIN = 0 V
Max
Unit
pF
5
7
COUT
VOUT = 0 V
pF
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage
Current
VIN = 0 to V
DD
IIL
– 1 uA
–1 uA
1 uA
1 uA
Output High Z
Output Leakage
Current
ILO
VOUT = 0 to V
DD
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = –4 mA
ILO = +4 mA
2.4
—
—
0.4 V
Rev: 1.03a 10/2002
4/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108ATP/J/X
Power Supply Currents
0 to 70°C
–40 to 85°C
8 ns 10 ns
Parameter
Symbol
Test Conditions
7 ns
8 ns
10 ns
12 ns
7 ns
12 ns
CE ≤ VIL
Operating
Supply
Current
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
IOUT = 0 mA
IDD
135 mA 120 mA
95 mA
85 mA
145 mA 130 mA 105 mA
95 mA
CE ≥ VIH
Standby
Current
All other inputs
≥ VIH or ≤VIL
Min. cycle time
ISB1
35 mA
30 mA
25 mA
22 mA
45 mA
40 mA
35 mA
32 mA
CE ≥ VDD - 0.2V
All other inputs
≥ VDD - 0.2V or ≤
0.2V
Standby
Current
ISB2
10 mA
20 mA
AC Test Conditions
Output Load 1
Parameter
Input high level
Input low level
Input rise time
Input fall time
Conditions
VIH = 2.4 V
VIL = 0.4 V
tr = 1 V/ns
tf = 1 V/ns
1.4 V
DQ
1
30pF
50Ω
VT = 1.4 V
Input reference level
Output reference level
Output load
Output Load 2
1.4 V
3.3 V
Fig. 1& 2
589Ω
434Ω
DQ
Note:
1. Include scope and jig capacitance.
1
5pF
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
Rev: 1.03a 10/2002
5/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108ATP/J/X
AC Characteristics
Read Cycle
-7
-8
-10
-12
Parameter
Symbol
Unit
Min Max Min
Max
—
8
Min
10
—
—
—
3
Max
—
Min
12
—
—
—
3
Max
—
Read cycle time
tRC
tAA
tAC
tOE
tOH
7
—
—
—
3
—
7
8
—
—
—
3
ns
ns
ns
ns
ns
ns
Address access time
10
10
4
12
12
5
Chip enable access time (CE)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
7
8
3
3.5
—
—
—
—
—
—
*
3
3
3
—
3
—
tLZ
*
Output enable to output in low Z (OE)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
0
—
3.5
3
0
—
4
0
—
5
0
—
6
ns
ns
ns
tOLZ
*
—
—
—
—
—
—
—
—
tHZ
*
3.5
4
5
tOHZ
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = V , WE = V
IL
IH
tRC
Address
Data Out
tAA
tOH
Previous Data
Data valid
Rev: 1.03a 10/2002
6/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108ATP/J/X
Read Cycle 2: WE = V
IH
tRC
Address
CE
tAA
tAC
tHZ
tLZ
OE
tOE
tOHZ
tOLZ
DATA VALID
Data Out
High impedance
Write Cycle
-7
-8
-10
-12
Parameter
Symbol
Unit
Min Max
Min
8
Max
—
—
—
—
—
—
—
—
—
—
Min
10
7
Max
—
—
—
—
—
—
—
—
—
—
Min
12
8
Max
—
—
—
—
—
—
—
—
—
—
Write cycle time
Address valid to end of write
Chip enable to end of write
Data set up time
tWC
tAW
tCW
tDW
tDH
7
5
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
5.5
4
5
7
8
3.5
0
5
6
Data hold time
0
0
0
Write pulse width
tWP
tAS
5
5.5
0
7
8
Address set up time
0
0
0
Write recovery time (WE)
Write recovery time (CE)
Output Low Z from end of write
tWR
tWR1
0
0
0
0
0
0
0
0
*
3
3
3
3
tWLZ
*
Write to output in High Z
—
3
—
3.5
—
4
—
5
ns
tWHZ
* These parameters are sampled and are not 100% tested.
Rev: 1.03a 10/2002
7/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108ATP/J/X
Write Cycle 1: WE control
tWC
Address
tAW
tWR
OE
tCW
CE
tAS
tWP
WE
tDW
tDH
DATA VALID
Data In
Data Out
tWHZ
tWLZ
HIGH IMPEDANCE
Write Cycle 2: CE control
tWC
Address
tAW
tWR1
OE
CE
tAS
tCW
tWP
WE
tDW
tDH
DATA VALID
Data In
Data Out
HIGH IMPEDANCE
Rev: 1.03a 10/2002
8/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108ATP/J/X
36-Pin SOJ, 400 mil
Dimension in inch
Dimension in mm
Symbol
min
nom
—
max
min
—
nom
—
max
3.70
—
A
A1
A2
B
—
0.146
—
L
0.026
—
0.66
2.67
0.33
0.61
0.15
—
D
c
0.105 0.110 0.115
0.013 0.017 0.021
0.024 0.028 0.032
0.006 0.008 0.012
2.80
0.43
0.71
0.20
2.92
0.53
0.81
0.30
B1
c
1
e
D
0.920 0.924 0.929 23.37 23.47 23.60
0.395 0.400 0.405 10.04 10.16 10.28
A
E
e
—
0.05
—
—
1.27
—
HE
GE
L
0.430 0.435 0.440 10.93 11.05 11.17
B
B1
y
0.354 0.366 0.378
9.00
2.08
—
9.30
—
9.60
—
Q
Detail A
0.082
—
—
—
—
—
y
0.004
—
0.10
o
o
o
o
Q
—
0
10
0
10
Notes:
1. Dimension D& E do not include interlead flash.
2. Dimension B1 does not include dambar protrusion/intrusion.
3. Controlling dimension: inches
Rev: 1.03a 10/2002
9/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108ATP/J/X
44-Pin, 400 mil TSOP-II
Dimension in inch Dimension in mm
min nom max min nom max
D
Symbol
c
44
23
22
A
—
—
—
0.047
—
—
—
1.20
—
A1
0.002
0.05
—
A2
0.037 0.039 0.041 0.95
0.01 0.014 0.018 0.25
1.00
0.35
0.15
1.05
0.45
—
A
B
c
—
0.006
—
—
D
0.721 0.725 0.729 18.31 18.41 18.51
0.396 0.400 0.404 10.06 10.16 10.26
1
e
E
B
e
—
0.031
—
—
0.80
—
HE
0.455 0.463 0.471 11.56 11.76 11.96
L
L1
0.016 0.020 0.024 0.40
0.50
0.80
—
0.60
—
y
—
—
0.031
—
—
—
—
y
0.004
0.10
o
o
o
o
Q
Q
—
—
0
5
0
5
Detail A
Notes:
1. Dimension D& E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Controlling dimension: mm
Rev: 1.03a 10/2002
10/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108ATP/J/X
6 mm x 10 mm FP-BGA
Symbol
Unit: mm
D
A
1.10±0.10
0.20~0.30
f0.30~0.40
0.36(TYP)
10.0±0.05
5.25
A1
fb
c
E
D
Pin A1
D1
E
Index
6.0±0.05
3.75
E1
e
0.75(TYP)
0.10
Top View
aaa
A
c
Side View
A1
aaa
E1
Pin A1
A B C D E F G H
fb Solder Ball
Index
1
2
3
4
5
6
e
e
D1
Bottom View
Rev: 1.03a 10/2002
11/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108ATP/J/X
Ordering Information
*
Package
Access Time
Temp. Range
Status
Part Number
GS74108ATP-7
GS74108ATP-8
GS74108ATP-10
GS74108ATP-12
GS74108ATP-7I
GS74108ATP-8I
GS74108ATP-10I
GS74108ATP-12I
GS74108AJ-7
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil SOJ
7 ns
8 ns
Commercial
Commercial
Commercial
Commercial
Industrial
10 ns
12 ns
7 ns
8 ns
Industrial
10 ns
12 ns
7 ns
Industrial
Industrial
Commercial
Commercial
Commercial
Commercial
Industrial
GS74108AJ-8
400 mil SOJ
8 ns
GS74108AJ-10
GS74108AJ-12
GS74108AJ-7I
GS74108AJ-8I
GS74108AJ-10I
GS74108AJ-12I
GS74108AX-7
GS74108AX-8
GS74108AX-10
GS74108AX-12
GS74108AX-7I
GS74108AX-8I
GS74108AX-10I
GS74108AX-12I
400 mil SOJ
10 ns
12 ns
7 ns
400 mil SOJ
400 mil SOJ
400 mil SOJ
8 ns
Industrial
400 mil SOJ
10 ns
12 ns
7 ns
Industrial
400 mil SOJ
Industrial
6 mm x 10 mm FP-BGA
6 mm x 10 mm FP-BGA
6 mm x 10 mm FP-BGA
6 mm x 10 mm FP-BGA
6 mm x 10 mm FP-BGA
6 mm x 10 mm FP-BGA
6 mm x 10 mm FP-BGA
6 mm x 10 mm FP-BGA
Commercial
Commercial
Commercial
Commercial
Industrial
8 ns
10 ns
12 ns
7 ns
8 ns
Industrial
10 ns
12 ns
Industrial
Industrial
*
Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:
GS74108ATP-8T
Rev: 1.03a 10/2002
12/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74108ATP/J/X
4M Asynchronous Datasheet Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content
Page #/Revisions/Reason
• Creation of new datasheet
74108A_r1
Format/Content
• Added 6 ns speed bin
• Updated all power numbers
74108A_r1; 74108A_r1_01
74108A_r1_01; 74108A_r1_02
74108A_r1_02; 74108A_r1_03
Content
• Updated Recommended Operating Conditions table on page 4
• Added 7 ns bin to entire document
• Added X package
Content
Content
• Removed 6 ns speed bin from entire document
• Corrected “X” package pinout
Rev: 1.03a 10/2002
13/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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