GS74116TP-12I [GSI]
256K x 16 4Mb Asynchronous SRAM; 256K ×16的4Mb SRAM的异步
| 型号： | GS74116TP-12I |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | 256K x 16 4Mb Asynchronous SRAM |
| 文件： | 总14页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS74116TP/J/U
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
8, 10, 12, 15ns
3.3V VDD
Center VDD & VSS
256K x 16
4Mb Asynchronous SRAM
SOJ 256K x 16 Pin Configuration
Features
• Fast access time: 8, 10, 12, 15ns
• CMOS low power operation: 170/145/130/110 mA at min.cycle time.
• Single 3.3V ± 0.3V power supply
• All inputs and outputs are TTL compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: -40° to 85°C
• Package line up
A4
A3
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A6
2
A2
A7
3
A1
OE
4
Top view
A0
UB
5
CE
LB
6
DQ1
DQ2
DQ3
DQ4
VDD
DQ16
DQ15
DQ14
7
8
9
J: 400mil, 44 pin SOJ package
TP: 400mil, 44 pin TSOP Type II package
U: 7.20mm x 11.65mm Fine Pitch Ball Grid Array package
10
11
12
13
14
15
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
44 pin
SOJ
VSS
DQ5
DQ6
DQ7
DQ8
WE
Description
The GS74116 is a high speed CMOS static RAM organized as
262,144-words by 16-bits. Static design eliminates the need for exter-
nal clocks or timing strobes. Operating on a single 3.3V power supply
and all inputs and outputs are TTL compatible. The GS74116 is avail-
able in a 7.2x11.65 mm Fine Pitch BGA package, 400 mil SOJ and
400 mil TSOP Type-II packages.
16
17
18
A15
A8
A14
A9
19
20
21
22
A13
A10
A11
A12
A16
A17
Pin Descriptions
Fine Pitch BGA 256K x 16 Bump Configuration
Symbol
A0 to A17
Description
Address input
1
2
3
4
5
6
DQ1 to DQ16
CE
Data input/output
Chip enable input
A
B
C
D
E
F
LB
OE
A0
A3
A1
A4
A6
A7
A2
NC
Lower byte enable input
(DQ1 to DQ8)
LB
DQ16 UB
CE
DQ1
Upper byte enable input
(DQ9 to DQ16)
DQ14 DQ15 A5
VSS DQ13 A17
VDD DQ12 NC
DQ11 DQ10 A8
DQ2 DQ3
DQ4 VDD
UB
WE
OE
VDD
VSS
NC
Write enable input
Output enable input
+3.3V power supply
Ground
A16 DQ5 VSS
A9
DQ7 DQ6
WE DQ8
G
H
DQ9
NC
NC
A10
A13
A11
A14
No connect
A12
A15
NC
7.2x11.65mm 0.75mm Bump Pitch
Top View
Rev: 2.02 3/2000
1/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
TSOP-II 256K x 16 Pin Configuration
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A4
A3
A5
2
A6
3
A2
A7
4
A1
OE
Top view
5
A0
UB
6
CE
LB
7
DQ1
DQ2
DQ3
DQ4
VDD
DQ16
DQ15
DQ14
8
9
10
11
12
13
14
15
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
44 pin
VSS
DQ5
DQ6
DQ7
DQ8
WE
TSOP II
16
17
18
A15
A8
19
20
21
22
A14
A13
A9
A10
A11
A12
A16
A17
Block Diagram
A0
Row
Decoder
Memory Array
Address
Input
Buffer
Column
Decoder
A17
CE
WE
OE
I/O Buffer
Control
_____
UB
_____
LB
DQ16
DQ1
Rev: 2.02 3/2000
2/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Truth Table
CE
OE
WE
LB
X
L
UB
X
DQ1 to DQ8
Not Selected
Read
DQ9 to DQ16
Not Selected
Read
VDD Current
H
X
X
ISB1, ISB2
L
L
L
L
H
L
L
H
L
Read
High Z
H
L
High Z
Read
L
Write
Write
IDD
X
L
H
L
Write
Not Write, High Z
Write
H
X
H
Not Write, High Z
High Z
L
L
H
X
H
X
X
High Z
H
High Z
High Z
Note: X: “H” or “L”
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
VDD
-0.5 to +4.6
V
-0.5 to VDD+0.5
(£ 4.6V max.)
Input Voltage
VIN
V
-0.5 to VDD+0.5
(£ 4.6V max.)
Output Voltage
VOUT
V
Allowable power dissipation
Storage temperature
PD
0.7
W
o
TSTG
-55 to 150
C
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 2.02 3/2000
3/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Recommended Operating Conditions
Parameter
Supply Voltage for -10/12/15
Supply Voltage for -8
Input High Voltage
Symbol
VDD
Min
3.0
Typ
3.3
3.3
-
Max
3.6
Unit
V
VDD
3.135
2.0
3.6
V
VIH
VDD+0.3
0.8
V
Input Low Voltage
VIL
-0.3
-
V
Ambient Temperature,
Commercial Range
o
TAc
TAI
0
-
-
70
85
C
Ambient Temperature,
Industrial Range
o
-40
C
Note:
1. Input overshoot voltage should be less than VDD+2V and not exceed 20ns.
2. Input undershoot voltage should be greater than -2V and not exceed 20ns.
Capacitance
Parameter
Symbol
CIN
Test Condition
VIN=0V
Max
Unit
pF
Input Capacitance
Output Capacitance
5
7
COUT
VOUT=0V
pF
Notes:
1. Tested at TA=25°C, f=1MHz
2. These parameters are sampled and are not 100% tested
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage
Current
IIL
VIN = 0 to VDD
-1uA
1uA
1uA
Output Leakage
Current
Output High Z
VOUT = 0 to VDD
ILO
-1uA
2.4
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = - 4mA
ILO = + 4mA
0.4V
Rev: 2.02 3/2000
4/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Power Supply Currents
0 to 70°C
-40 to 85°C
Parameter Symbol Test Conditions
8ns 10ns 12ns 15ns 10ns 12ns 15ns
CE £ VIL
Operating
Supply
Current
All other inputs
³ VIH or £ VIL
Min. cycle time
IOUT = 0 mA
IDD
170mA 145mA 130mA 110mA 155mA 140mA 120mA
CE ³ VIH
Standby
Current
All other inputs
³ VIH or £VIL
Min. cycle time
ISB1
ISB2
70mA 65mA 60mA 55mA 75mA 70mA 65mA
CE ³ VDD - 0.2V
All other inputs
³ VDD - 0.2V or £ 0.2V
Standby
Current
30mA
40mA
AC Test Conditions
Output Load 1
Parameter
Input high level
Input low level
Conditions
DQ
VIH=2.4V
VIL=0.4V
tr=1V/ns
tf=1V/ns
1.4V
1
30pF
50W
Input rise time
VT=1.4V
Input fall time
Input reference level
Output reference level
Output load
Output Load 2
1.4V
3.3V
Fig. 1& 2
589W
434W
DQ
Note:
1
1. Include scope and jig capacitance.
5pF
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ.
Rev: 2.02 3/2000
5/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
AC Characteristics
Read Cycle
-8
-10
-12
-15
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max
Read cycle time
tRC
tAA
tAC
tAB
tOE
tOH
8
---
8
10
---
---
---
---
3
---
10
10
4
12
---
---
---
---
3
---
12
12
5
15
---
---
---
---
3
---
15
15
6
ns
ns
ns
ns
ns
ns
ns
Address access time
---
---
---
---
3
Chip enable access time (CE)
Byte enable access time (UB, LB)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
8
3.5
3.5
---
---
4
5
6
---
---
---
---
---
---
*
3
3
3
3
tLZ
*
Output enable to output in low Z (OE)
Byte enable to output in low Z (UB, LB)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
Byte disable to output in High Z (UB, LB)
0
---
---
0
---
---
5
0
---
---
6
0
---
---
7
ns
ns
ns
ns
ns
tOLZ
*
0
0
0
0
tBLZ
*
---
---
---
4
---
---
---
---
---
---
---
---
---
tHZ
*
3.5
3.5
4
5
6
tOHZ
*
4
5
6
tBHZ
* These parameters are sampled and are not 100% tested
Read Cycle 1: CE = OE = V , WE = V , UB and, or LB = V
IL
IH
IL
tRC
Address
tAA
tOH
Data Out
Previous Data
Data valid
Rev: 2.02 3/2000
6/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Read Cycle 2: WE = V
IH
tRC
Address
CE
tAA
tAC
tHZ
tLZ
tAB
UB, LB
OE
tBHZ
tOHZ
tBLZ
tOLZ
tOE
Data valid
Data Out
High impedance
Write Cycle
-8
-10
-12
-15
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max
Write cycle time
Address valid to end of write
Chip enable to end of write
Byte enable to end of write
Data set up time
tWC
tAW
tCW
tBW
tDW
tDH
8
5.5
5.5
5.5
4
---
---
---
---
---
---
---
---
---
---
---
10
7
7
7
5
0
7
0
0
0
3
---
---
---
---
---
---
---
---
---
---
---
12
8
8
8
6
0
8
0
0
0
3
---
---
---
---
---
---
---
---
---
---
---
15
10
10
10
7
---
---
---
---
---
---
---
---
---
---
---
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data hold time
0
0
Write pulse width
tWP
tAS
5.5
0
10
0
Address set up time
Write recovery time (WE)
Write recovery time (CE)
Output Low Z from end of write
tWR
tWR1
0
0
0
0
*
3
3
tWLZ
*
Write to output in High Z
---
3.5
---
4
---
5
---
6
ns
tWHZ
* These parameters are sampled and are not 100% tested
Rev: 2.02 3/2000
7/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Write Cycle 1: WE control
tWC
Address
tAW
tWR
OE
CE
tCW
tBW
UB, LB
WE
tAS
tWP
tDW
tDH
Data valid
Data In
tWHZ
tWLZ
High impedance
Data Out
Write Cycle 2: CE control
tWC
Address
OE
tAW
tWR1
tAS
tCW
tBW
CE
UB, LB
WE
tWP
tDW
tDH
Data valid
Data In
Data Out
High impedance
Rev: 2.02 3/2000
8/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Write Cycle 3: UB, LB control
tWC
Address
tAW
tWR1
OE
CE
tAS
tCW
tBW
UB, LB
WE
tWP
tDW
tDH
Data valid
Data In
Data Out
High impedance
Rev: 2.02 3/2000
9/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
44 Pin, 400 mil SOJ
Dimension in inch Dimension in mm
Symbol
L
min nom max min nom max
D
c
44
23
22
A
A1
A2
B
-
-
-
0.148
-
-
-
-
3.759
-
0.025
0.635
0.105 0.110 0.115 2.667 2.794 2.921
0.018 0.457
0.026 0.028 0.032 0.660 0.711 0.813
0.008 0.203
-
-
-
-
B1
c
-
-
-
-
1
e
D
1.120 1.125 1.130 28.44 28.58 28.70
0.395 0.400 0.405 10.033 10.160 10.287
A
E
e
-
0.05
-
-
1.27
-
HE
GE
L
0.435 0.440 0.445 11.049 11.176 11.303
0.360 0.370 0.380 9.144 9.398 9.652
B
y
B1
Q
0.082 0.087 0.106 2.083 2.210
2.70
Detail A
y
-
-
-
0.004
-
-
-
0.102
o
o
o
o
Q
0
7
0
7
Note:
1. Dimension D& E do not include interlead flash
2. Dimension B1 does not include dambar protrusion / intrusion
Rev: 2.02 3/2000
10/14
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
N
GS74116TP/J/U
44 Pin, 400 mil TSOP-II
Dimension in inch Dimension in mm
D
Symbol
min nom max min nom max
c
44
23
22
A
A1
A2
B
-
-
-
0.047
-
-
-
-
1.20
-
0.002
0.05
0.037 0.039 0.041 0.95 1.00 1.05
0.01 0.014 0.018 0.25 0.35 0.45
A
c
-
0.006
-
-
0.15
-
D
0.721 0.725 0.729 18.31 18.41 18.51
0.396 0.400 0.404 10.06 10.16 10.26
1
e
E
B
e
-
0.031
-
-
0.80
-
HE
L
0.455 0.463 0.471 11.56 11.76 11.96
0.016 0.020 0.024 0.40 0.50 0.60
y
L1
y
-
-
0.031
-
-
-
0.80
-
-
-
0.004
-
-
0.10
o
o
o
o
Q
Q
0
5
0
5
Detail A
Note:
1. Dimension D& E do not include interlead flash
2. Dimension B does not include dambar protrusion / intrusion
3. Controlling dimension: mm
Rev: 2.02 3/2000
11/14
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
N
GS74116TP/J/U
7.2mmx11.65mm FP-BGA
Symbol
Unit: mm
D
A
1.10±0.10
·
A1
f b
c
0.22±0.05
f 0.35
0.36(TYP)
11.65±0.10
5.25
E
D
Pin A1
Index
D1
E
7.20±0.10
3.75
E1
e
0.75(TYP)
0.10
Top View
aaa
A
c
Side View
A1
aaa
E1
Pin A1
A B C D E F G H
f b Solder Ball
Index
1
2
3
4
5
6
e
e
D1
Bottom View
Rev: 2.02 3/2000
12/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Ordering Information
*
Package
Access Time
Temp. Range
Status
Part Number
GS74116TP-8
GS74116TP-10
GS74116TP-12
GS74116TP-15
GS74116TP-8I
GS74116TP-10I
GS74116TP-12I
GS74116TP-15I
GS74116J-8
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil SOJ
8 ns
10 ns
12 ns
15 ns
8 ns
Commercial
Commercial
Commercial
Commercial
Industrial
10 ns
12 ns
15 ns
8 ns
Industrial
Industrial
Industrial
Commercial
Commercial
Commercial
Commercial
Industrial
GS74116J-10
GS74116J-12
GS74116J-15
GS74116J-8I
400 mil SOJ
10 ns
12 ns
15 ns
8 ns
400 mil SOJ
400 mil SOJ
400 mil SOJ
GS74116J-10I
GS74116J-12I
GS74116J-15I
GS74116U-8
400 mil SOJ
10 ns
12 ns
15 ns
8 ns
Industrial
400 mil SOJ
Industrial
400 mil SOJ
Industrial
Fine Pitch BGA
Fine Pitch BGA
Fine Pitch BGA
Fine Pitch BGA
Fine Pitch BGA
Fine Pitch BGA
Fine Pitch BGA
Fine Pitch BGA
Commercial
Commercial
Commercial
Commercial
Industrial
GS74116U-10
GS74116U-12
GS74116U-15
GS74116U-8I
GS74116U-10I
GS74116U-12I
GS74116U-15I
10 ns
12 ns
15 ns
8 ns
10 ns
12 ns
15 ns
Industrial
Industrial
Industrial
*
Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS74116TP-10T
Rev: 2.02 3/2000
13/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74116TP/J/U
Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content
Page #/Revisions/Reason
Format/Typos
Content
Document/Changed format of subscripts on pins to small caps.
13/Changed Tape and Reel Note at end of Ordering info./Enhancement
None
Rev1.03c 3/1999;
1.04d 6/1999
Format/Typos
1.04d 6/1999;
2.00 8/1999
1. Added Fine Pitch BGA package to datasheet.
2. 10/Added Dimension “D” to SOJ package diagram/Was missing
3. 11/Added Dimension “D” to TSOP package diagram/Was missing
Content
1. GSI Logo
2.
GS741Rev2.01KRev 21 2/2000L
Format/Content
Content
1. Changed Pin A17 from 3E to 3D.
GS74116 Rev2.01 2/2000L; Rev
2.02 3/2000N
Rev: 2.02 3/2000
14/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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