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GS81314LD37GK-933I [GSI]

Burst of 4 Single-Bank ECCRAM;
GS81314LD37GK-933I
型号： GS81314LD37GK-933I
厂家： GSI TECHNOLOGY    GSI TECHNOLOGY
描述：

Burst of 4 Single-Bank ECCRAM
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GS81314LD19/37GK-933/800  
Up to 933 MHz  
260-Pin BGA  
Com & Ind Temp  
HSTL I/O  
144Mb SigmaQuad-IVe™  
Burst of 4 Single-Bank ECCRAM™  
1.2V ~ 1.3V V  
DD  
1.2V ~ 1.3V V  
DDQ  
Features  
Clocking and Addressing Schemes  
• 4Mb x 36 and 8Mb x 18 organizations available  
• Organized as a single logical memory bank  
• 933 MHz maximum operating frequency  
• 933 MT/s peak transaction rate (in millions per second)  
• 134 Gb/s peak data bandwidth (in x36 devices)  
• Separate I/O DDR Data Buses  
The GS81314LD19/37GK SigmaQuad-IVe ECCRAMs are  
synchronous devices. They employ three pairs of positive and  
negative input clocks; one pair of master clocks, CK and CK,  
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All  
six input clocks are single-ended; that is, each is received by a  
dedicated input buffer.  
• Non-multiplexed SDR Address Bus  
CK and CK are used to latch address and control inputs, and to  
control all output timing. KD[1:0] and KD[1:0] are used solely  
to latch data inputs.  
• One operation - Read or Write - per clock cycle  
• No address/bank restrictions on Read and Write ops  
• Burst of 4 Read and Write operations  
• 5 cycle Read Latency  
• On-chip ECC with virtually zero SER  
• Loopback signal timing training capability  
• 1.2V ~ 1.3V nominal core voltage  
Each internal read and write operation in a SigmaQuad-IVe B4  
ECCRAM is four times wider than the device I/O bus. An  
input data bus de-multiplexer is used to accumulate incoming  
data before it is simultaneously written to the memory array.  
An output data multiplexer is used to capture the data produced  
from a single memory array read and then route it to the  
appropriate output drivers as needed. Therefore, the address  
field of a SigmaQuad-IVe B4 ECCRAM is always two address  
pins less than the advertised index depth (e.g. the 8M x 18 has  
2M addressable index).  
• 1.2V ~ 1.3V HSTL I/O interface  
• Configuration registers  
• Configurable ODT (on-die termination)  
• ZQ pin for programmable driver impedance  
• ZT pin for programmable ODT impedance  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-  
compliant BGA package  
On-Chip Error Correction Code  
GSI's ECCRAMs implement an ECC algorithm that detects  
and corrects all single-bit memory errors, including those  
induced by SER events such as cosmic rays, alpha particles,  
etc. The resulting Soft Error Rate of these devices is  
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude  
improvement over comparable SRAMs with no on-chip ECC,  
which typically have an SER of 200 FITs/Mb or more.  
SigmaQuad-IVe™ Family Overview  
SigmaQuad-IVe ECCRAMs are the Separate I/O half of the  
SigmaQuad-IVe/SigmaDDR-IVe family of high performance  
ECCRAMs. Although similar to GSI's third generation of  
networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe  
family), these fourth generation devices offer several new  
features that help enable significantly higher performance.  
All quoted SER values are at sea level in New York City.  
Parameter Synopsis  
V
Speed Grade  
Max Operating Frequency  
Read Latency  
DD  
-933  
-800  
933 MHz  
800 MHz  
5 cycles  
5 cycles  
1.25V to 1.35V  
1.15V to 1.35V  
Rev: 1.02 3/2016  
1/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
8M x 18 Pinout (Top View)  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
NC  
(RSVD)  
MCH  
(CFG)  
MRW  
V
V
V
V
V
V
V
V
V
V
DD  
ZQ  
PZT1  
PZT0  
A
B
C
D
E
F
DD  
DDQ  
DD  
DDQ  
DDQ  
DD  
DDQ  
MCH  
(B4M)  
NC  
(RSVD)  
MCH  
(SIOM)  
V
NU  
V
NU  
V
V
SS  
MCL  
D0  
Q0  
SS  
O
SS  
I
SS  
V
V
V
V
V
NU  
V
NU  
Q17  
D17  
SA13  
SA14  
DDQ  
DDQ  
SS  
DD  
SS  
DDQ  
I
DDQ  
O
NC  
(288 Mb)  
V
NU  
V
NU  
V
V
V
V
SA19  
SA20  
D1  
Q1  
SS  
O
SS  
I
DDQ  
DDQ  
SS  
SS  
V
V
V
V
V
NU  
V
NU  
V
Q16  
D16  
SA11  
SA12  
DDQ  
DD  
SS  
SS  
SS  
DD  
I
DDQ  
O
V
NU  
V
NU  
V
V
V
V
SA17  
SA18  
D2  
Q2  
SS  
O
O
SS  
I
DD  
DDQ  
DD  
SS  
SS  
NU  
NU  
V
V
NU  
NU  
NU  
V
Q15  
Q14  
D15  
D14  
SA9  
MZT1  
W
SA10  
D3  
Q3  
G
H
J
I
SS  
SS  
I
O
O
V
V
V
V
V
NU  
V
DDQ  
SA15  
SA16  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
I
V
NU  
V
NU  
V
V
V
V
SA7  
SA8  
D4  
Q4  
SS  
O
SS  
I
SS  
SS  
SS  
SS  
SS  
V
V
V
V
V
V
V
V
DDQ  
CQ1  
CQ1  
KD1  
KD1  
CK  
CK  
KD0  
KD0  
CQ0  
CQ0  
K
L
DDQ  
REF  
DD  
DD  
DD  
DD  
REF  
V
V
V
V
V
V
SS  
QVLD1  
QVLD0  
SS  
ss  
DDQ  
DDQ  
SS  
V
V
V
V
V
NU  
V
NU  
V
Q13  
D13  
SA5  
SA6  
M
N
P
R
T
SS  
SS  
SS  
SS  
SS  
I
SS  
O
SS  
NU  
V
NU  
V
V
V
V
V
DDQ  
PLL  
R
MCL  
D5  
D6  
Q5  
Q6  
O
DDQ  
I
DDQ  
DDQ  
DDQ  
DDQ  
NU  
NU  
V
V
NU  
NU  
Q12  
D12  
SA3  
MZT0  
SA4  
O
I
SS  
SS  
I
O
O
V
V
V
V
V
NU  
V
NU  
V
Q11  
D11  
MCH  
RST  
SS  
SS  
DD  
DDQ  
DD  
I
SS  
SS  
NU  
V
NU  
V
V
V
V
V
V
V
V
SA1  
SA2  
D7  
Q7  
O
DDQ  
I
DD  
SS  
SS  
SS  
DD  
DDQ  
NC  
(576 Mb)  
NC  
(RSVD)  
NC  
(1152 Mb)  
V
V
V
V
NU  
V
NU  
V
Q10  
D10  
U
V
W
Y
SS  
SS  
DDQ  
DDQ  
I
SS  
O
SS  
SA21  
(x18)  
NU  
I
(B2)  
NU  
V
NU  
V
V
V
V
V
DDQ  
D8  
Q8  
O
DDQ  
I
DDQ  
SS  
DD  
SS  
DDQ  
V
V
NU  
V
NU  
V
Q9  
D9  
TCK  
TDO  
MCL  
ZT  
RCS  
MCL  
TMS  
TDI  
SS  
SS  
I
SS  
O
SS  
NC  
(RSVD)  
V
V
V
V
V
V
V
MCL  
DD  
DDQ  
DD  
DDQ  
DDQ  
DD  
DDQ  
DD  
Notes:  
1. Pins 5B, 6W, 8W, 8Y, and 9N must be tied Low in this device.  
2. Pin 5R must be tied High in this device.  
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.  
4. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration.  
5. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.  
6. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.  
7. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low.  
8. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.  
9. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.  
10. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.  
Rev: 1.02 3/2016  
2/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
4M x 36 Pinout (Top View)  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
NC  
(RSVD)  
MCL  
(CFG)  
MRW  
V
V
V
V
V
V
V
V
DD  
ZQ  
PZT1  
PZT0  
A
B
C
D
E
F
DD  
DDQ  
DD  
DDQ  
DDQ  
DD  
DDQ  
MCH  
(B4M)  
NC  
(RSVD)  
MCH  
(SIOM)  
V
V
V
V
SS  
Q35  
D35  
MCL  
D0  
Q0  
SS  
SS  
SS  
V
V
V
V
V
V
V
DDQ  
Q26  
D26  
SA13  
SA14  
D9  
Q9  
DDQ  
DDQ  
SS  
DD  
SS  
DDQ  
NC  
(288 Mb)  
V
V
V
V
V
V
SS  
Q34  
D34  
SA19  
SA20  
D1  
Q1  
SS  
SS  
DDQ  
DDQ  
SS  
V
V
V
V
V
V
V
DDQ  
Q25  
D25  
SA11  
SA12  
D10  
Q10  
DDQ  
DD  
SS  
SS  
SS  
DD  
V
V
V
V
V
V
V
Q33  
D33  
D32  
SA17  
SA18  
D2  
Q2  
SS  
SS  
DD  
DDQ  
DD  
SS  
SS  
V
V
Q24  
Q23  
Q32  
D24  
D23  
SA9  
MZT1  
W
SA10  
D3  
D11  
D12  
Q3  
Q11  
Q12  
G
H
J
SS  
SS  
V
V
V
V
V
V
DDQ  
SA15  
SA16  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
V
V
V
V
V
V
V
Q31  
D31  
SA7  
SA8  
D4  
Q4  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
V
V
V
V
V
V
V
V
DDQ  
CQ1  
CQ1  
KD1  
KD1  
CK  
CK  
KD0  
KD0  
CQ0  
CQ0  
K
L
DDQ  
REF  
DD  
DD  
DD  
DD  
REF  
V
V
V
V
V
V
SS  
QVLD1  
QVLD0  
SS  
SS  
DDQ  
DDQ  
SS  
V
V
V
V
V
V
V
Q22  
D22  
SA5  
SA6  
D13  
Q13  
M
N
P
R
T
SS  
SS  
SS  
SS  
SS  
SS  
SS  
V
V
V
V
V
V
DDQ  
Q30  
Q29  
D30  
D29  
PLL  
R
MCL  
D5  
D6  
Q5  
Q6  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
V
V
Q21  
D21  
SA3  
MZT0  
SA4  
D14  
Q14  
SS  
SS  
V
V
V
V
V
V
V
Q20  
D20  
MCH  
RST  
D15  
Q15  
SS  
SS  
DD  
DDQ  
DD  
SS  
SS  
V
V
V
V
V
V
V
DDQ  
Q28  
D28  
SA1  
SA2  
D7  
Q7  
DDQ  
DD  
SS  
SS  
SS  
DD  
NC  
(576 Mb)  
NC  
(RSVD)  
NC  
(1152 Mb)  
V
V
V
V
V
V
Q19  
D19  
D16  
Q16  
U
V
W
Y
SS  
SS  
DDQ  
DDQ  
SS  
SS  
NU  
(x18)  
NU  
I
(B2)  
I
V
V
V
V
V
V
V
DDQ  
Q27  
D27  
D8  
Q8  
DDQ  
DDQ  
SS  
DD  
SS  
DDQ  
V
V
V
V
Q18  
D18  
TCK  
TDO  
MCL  
RCS  
MCL  
TMS  
TDI  
D17  
Q17  
SS  
SS  
SS  
SS  
NC  
(RSVD)  
V
V
V
V
V
V
V
V
ZT  
MCL  
DD  
DDQ  
DD  
DDQ  
DDQ  
DD  
DDQ  
DD  
Notes:  
1. Pins 5B, 6W, 8W, 8Y, and 9N must be tied Low in this device.  
2. Pin 5R must be tied High in this device.  
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.  
4. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration.  
5. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.  
6. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.  
7. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low.  
8. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.  
9. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.  
10. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.  
Rev: 1.02 3/2016  
3/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
Pin Description  
Symbol  
Description  
Type  
SA[21:1]  
Address — Read or write address is registered on CK.  
Input  
Write Data — Registered on KD and KD during Write operations.  
D[17:0] - x18 and x36.  
D[35:0]  
Q[35:0]  
Input  
D[35:18] - x36 only.  
Read Data — Aligned with CQ and CQ during Read operations.  
Q[17:0] - x18 and x36.  
Output  
Output  
Q[35:18] - x36 only.  
QVLD[1:0]  
CK, CK  
Read Data Valid — Driven high one half cycle before valid read data.  
Primary Input Clocks — Dual single-ended. Used for latching address and control inputs, for internal timing  
control, and for output timing control.  
Input  
Input  
Write Data Input Clocks — Dual single-ended. Used for latching write data inputs.  
KD0, KD0: latch D[17:0] in x36, and D[8:0] in x18.  
KD[1:0],  
KD[1:0]  
KD1, KD1: latch D[35:18] in x36, and D[17:9] in x18.  
Read Data Output Clocks — Free-running output (echo) clocks, tightly aligned with read data outputs.  
Facilitate source-synchronous operation.  
CQ[1:0],  
CQ[1:0]  
Output  
CQ0, CQ0: align with Q[17:0] in x36, and Q[8:0] in x18.  
CQ1, CQ1: align with Q[35:18] in x36, and Q[17:9] in x18.  
R
Read Enable — Registered on CK. See the Clock Truth Table for functionality.  
Write Enable — Registered on CK. See the Clock Truth Table for functionality.  
Input  
Input  
W
Mode Register Write — Registered onCK. Can be used synchronously or asynchronously to enable Reg-  
ister Write Mode. See the State and Clock Truth Tables for functionality.  
MRW  
PLL  
Input  
Input  
PLL Enable — Weakly pulled High internally.  
PLL = 0: disables internal PLL.  
PLL = 1: enables internal PLL.  
Reset — Holds the device inactive and resets the device to its initial power-on state when asserted High.  
Weakly pulled Low internally.  
RST  
ZQ  
Input  
Input  
Input  
Input  
Driver Impedance Control Resistor Input — Must be connected to V through an external resistor RQ to  
SS  
program driver impedance.  
ODT Impedance Control Resistor Input — Must be connected to V through an external resistor RT to  
SS  
ZT  
program ODT impedance.  
Current Source Resistor Input — Must be connected to V through an external 2Kresistor to provide  
SS  
RCS  
an accurate current source for the PLL.  
Rev: 1.02 3/2016  
4/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
Symbol  
Description  
Type  
ODT Mode Select — Set the default ODT state globally for all input groups during power-up and reset. Must  
be tied High or Low.  
MZT[1:0] = 00: disables ODT on all input groups, regardless of PZT[1:0].  
MZT[1:0] = 01: enables strong ODT on select input groups, as specified by PZT[1:0].  
MZT[1:0] = 10: enables weak ODT on select input groups, as specified by PZT[1:0].  
MZT[1:0] = 11: reserved.  
MZT[1:0]  
Input  
Input  
Note: The ODT state for each input group can be changed at any time via the Configuration Registers.  
ODT Configuration Select — Set the default ODT state for various combinations of input groups during  
power-up and reset, when MZT[1:0] = 01 or 10. Must be tied High or Low.  
PZT[1:0] = 00: enables ODT on write data only.  
PZT[1:0]  
PZT[1:0] = 01: enables ODT on write data and input clocks.  
PZT[1:0] = 10: enables ODT on write data, address, and control.  
PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control.  
Note: The ODT state for each input group can be changed at any time via the Configuration Registers.  
V
Core Power Supply  
—
—
—
DD  
V
I/O Power Supply  
DDQ  
V
Input Reference Voltage — Input buffer reference voltage.  
REF  
V
Ground  
—
SS  
TCK  
TMS  
TDI  
JTAG Clock — Weakly pulled Low internally.  
JTAG Mode Select — Weakly pulled High internally.  
JTAG Data Input — Weakly pulled High internally.  
JTAG Data Output  
Input  
Input  
Input  
Output  
Input  
TDO  
MCH  
Must Connect High — May be tied to V  
directly or via a 1kresistor.  
DDQ  
Must Connect Low — May be tied to V directly or via a 1kresistor.  
MCL  
NC  
Input  
—
SS  
No Connect — There is no internal chip connection to these pins. They may be left unconnected, or tied/  
driven High or Low.  
Not Used Input — There is an internal chip connection to these input pins, but they are unused by the  
device. They are pulled Low internally. They may be left unconnected or tied/driven Low. They should not be  
tied/driven High.  
NU  
Input  
I
Not Used Output — There is an internal chip connection to these output pins, but they are unused by the  
device. The drivers are tri-stated internally. They should be left unconnected.  
NU  
Output  
O
Rev: 1.02 3/2016  
5/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
Initialization Summary  
Prior to functional use, these devices must first be initialized and configured. The steps described below will ensure that the  
internal logic has been properly reset, and that functional timing parameters have been configured appropriately.  
Flow Chart  
Notes:  
1. MZT[1:0] and PZT[1:0] mode pins are used to set the default ODT state of all  
Power-Up  
input groups at power-up, and whenever RST is asserted High. The ODT state  
for each input group can be changed any time thereafter using Register Write  
Mode to program certain bits in the Configuration Registers.  
Reset SRAM  
2. Calibrations are performed for driver impedance, ODT impedance, and the PLL  
current source immediately after RST is de-asserted Low. The calibrations can  
take up to 384K cycles total. See the Power-Up and Reset Requirements section  
for more information.  
Wait for Calibrations  
3. The PLL can be enabled by the PLL pin, or by the PLL Enable (PLE) bit in the  
Configuration Registers. See the PLL Operation section for more information.  
Enable PLL,  
Wait for Lock  
4. If the PLE register bit is used to enable the PLL, then Register Write Mode will  
likely have to be utilized in the “Asynchronous, Pre-Input Training” method in  
order to change the state of the bit, since Address / Control Input Training has  
not yet been performed. See the Configuration Registers section for more infor-  
No  
Training  
Required?  
mation.  
Yes  
5. It can take up to 64K cycles for the PLL to lock after it has been enabled.  
6. Special Loopback Modes are available in these devices to perform Address /  
Control Input Training; they are selected and enabled via the Loopback Mode  
Select (LBK[1:0]) and Loopback Mode Enable (LBKE) bits in the Configuration  
Registers.  
Address / Control  
Input Training  
Read Data  
7. If Loopback Modes are used to perform Address / Control Input Training, then  
Register Write Mode will likely have to be utilized in the “Asynchronous,  
Pre-Input Training” method in order to change the states of the LBK[1:0] and  
LBKE register bits.  
Output Training  
Write Data  
Input Training  
8. Loopback Modes can also be used for Read Data Output Training, if desired.  
See the Signal Timing Training and Loopback Mode sections for more informa-  
tion.  
Additional  
Configuration  
9. “Additional Configuration” includes programming the Read Latency to 5 cycles  
(which is required by these devices), and any other configuration changes  
required by the system. Since this step is performed after Address / Control Input  
Training, Register Write Mode can be utilized in the “Asynchronous, Post-Input  
Training” method (or perhaps the “Synchronous” method, if the synchronous tim-  
ing requirements can be met at the particular operating frequency).  
Normal Operation  
Yes  
No  
Train  
Again?  
10. It is up to the system to determine if/when re-training is necessary.  
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Power-Up and Reset Requirements  
For reliability purposes, power supplies must power up simultaneously, or in the following sequence:  
, V , V , V and inputs.  
V
SS  
DD  
DDQ  
REF  
Power supplies must power down simultaneously, or in the reverse sequence.  
After power supplies power up, the following start-up sequence must be followed.  
Step 1: Assert RST High for at least 1ms.  
While RST is asserted high:  
• The PLL is disabled.  
• The states of R, W, and MRW control inputs are ignored.  
Note: If possible, RST should be asserted High before input clocks begin toggling, and remain asserted High until input clocks are  
stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing trouble in the SRAM.  
Step 2: Begin toggling input clocks.  
After input clocks begin toggling, but not necessarily within specification:  
• Q are placed in the non-Read state, and remain so until the first Read operation.  
• QVLD are driven Low, and remain so until the first Read operation.  
• CQ, CQ begin toggling, but not necessarily within specification.  
Step 3: Wait until input clocks are stable and toggling within specification.  
Step 4: De-assert RST Low.  
Step 5: Wait at least 384K (393,216) cycles.  
During this time:  
• Driver and ODT impedances are calibrated. Can take up to 320K cycles.  
• The current source for the PLL is calibrated (based on RCS pin). Can take up to 64K cycles.  
Step 6: Enable the PLL.  
Step 7: Wait at least 64K (65,536) cycles for the PLL to lock.  
After the PLL has locked:  
• CQ, CQ begin toggling within specification.  
Step 8: Continue initialization (see the Initialization Flow Chart).  
Reset Usage  
Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence  
described above, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently de-asserted  
Low, as in step 4 above, steps 5~7 above must be followed before normal operation is resumed. It is up the system to determine  
whether further re-initialization beyond step 7 (as outlined in the Initialization Flow Chart) is required before normal operation is  
resumed.  
Note: Memory array content may be perturbed/corrupted when RST is asserted High.  
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PLL Operation  
A PLL is implemented in these devices to control all output timing. It uses the CK input clock as a source, and is enabled when all  
of the following conditions are met:  
1. RST is de-asserted Low, and  
2. Either the PLL Enable pin (PLL) or the PLL Enable register bit (PLE) is asserted High, and  
3. CK cycle time t  
(max), as specified in the AC Timing Specifications section.  
KHKH  
Once enabled, the PLL requires 64K stable clock cycles in order to lock/synchronize properly.  
When the PLL is enabled, it aligns output clocks and read data to input clocks (with some fixed delay), and it generates all  
mid-cycle output timing. See the Output Timing section for more information.  
The PLL can tolerate changes in input clock frequency due to clock jitter (i.e. such jitter will not cause the PLL to lose lock/  
synchronization), provided the cycle-to-cycle jitter does not exceed 200ps (see “t  
” in the AC Timing Specifications section  
KJITcc  
for more information). However, the PLL must be resynchronized (i.e. disabled and then re-enabled) whenever the nominal input  
clock frequency is changed.  
The PLL is disabled when any of the following conditions are met:  
1. RST is asserted High, or  
2. Both the PLL Enable pin (PLL) and the PLL Enable register bit (PLE) are deasserted Low, or  
3. CK is stopped for at least 30ns, or CK cycle time 30ns.  
On-Chip Error Correction  
These devices implement a single-error correct, single-error detect (SEC-SED) ECC algorithm (specifically, a Hamming Code) on  
each 18-bit data word transmitted in DDR fashion on each 9-bit data bus (i.e., transmitted on D/Q[8:0], D/Q[17:9], D/Q[26:18],  
and D/Q[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible to the  
user). As such, these devices actually comprise 184Mb of memory, of which 144Mb are visible to the user.  
The ECC algorithm cannot detect multi-bit errors. However, these devices are architected in such a way that a single SER event  
very rarely causes a multi-bit error across any given “transmitted data unit”, where a “transmitted data unit” represents the data  
transmitted as the result of a single read or write operation to a particular address. The extreme rarity of multi-bit errors results in  
the SER mentioned previously (i.e., <0.002 FITs/Mb, measured at sea level).  
Not only does the on-chip ECC significantly improve SER performance, but it can also free up the entire memory array for data  
storage. Very often SRAM applications allocate 1/9th of the memory array (i.e., one “error bit” per eight “data bits”, in any 9-bit  
“data byte”) for error detection (either simple parity error detection, or system-level ECC error detection and correction).  
Depending on the application, such error-bit allocation may be unnecessary in these devices, in which case the entire memory array  
can be utilized for data storage, effectively providing 12.5% greater storage capacity compared to SRAMs of the same density not  
equipped with on-chip ECC.  
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Configuration Registers  
These devices utilize a set of registers for device configuration. The configuration registers are written via Register Write Mode,  
which is initiated by asserting MRW High and R Low. When Register Write Mode is utilized, up to sixteen distinct 6-bit registers  
can be programmed using SDR timing on the SA[10:1] address input pins. The D data input pins are not used.  
Note: Register Write Mode only provides the ability to write the configuration registers. The ability to read the configuration regis-  
ters is provided via a private JTAG instruction and register. Please contact GSI for more information.  
Register Write Mode can be utilized in two ways:  
1. Asynchronous Method: MRW is driven asynchronously, such that is does not meet setup and hold time specs to CK.  
2. Synchronous Method: MRW is driven synchronously, such that is meets setup and hold time specs to CK.  
Regardless how Register Write Mode is utilized, at least 16 NOPs must be initiated before beginning a Register Write sequence, to  
ensure any previous Read and Write operations are completed before the sequence begins. And, at least 16 NOPs must be initiated  
after completing a Register Write sequence and before initiating Read and Write operations, and before utilizing Loopback Mode,  
to allow sufficient time for the newly programmed register settings to take effect.  
Register Write Mode Utilization - Asynchronous Method  
Register Write Mode can be utilized asynchronously up to the full operating speed of the device. When Register Write Mode is uti-  
lized asynchronously, there are two cases to consider:  
1. Pre Input Training: SA[10:1], R, W are driven such that they do not meet setup and hold time specs to CK.  
2. Post Input Training: SA[10:1], R, W are driven such that they meet setup and hold time specs to CK.  
Each case is examined separately below.  
Pre Input Training Requirements  
In this case, MRW, R, W, and SA[10:1] are all driven asynchronously. When Register Write Mode is utilized in this manner, only  
one register can be programmed during any particular instance that MRW is asserted High.  
The requirements for this usage case are as follows:  
• At least 16 NOPs must be initiated before and after the Register Write sequence.  
• MRW High must meet minimum pulse width requirements (tMRWPW).  
• R Low and SA[10:1] Valid must meet minimum setup time requirements (tMRWS) to MRW High.  
• R Low and SA[10:1] Valid must meet minimum hold time requirements (tMRWH) from MRW Low.  
• W High must also meet minimum setup time requirements (tMRWS) to MRW High, if inadvertent memory writes are to be pre-  
vented during the Register Write process. Otherwise, W state is “don’t care”.  
• W High must also meet minimum hold time requirements (tMRWH) from MRW Low, if inadvertent memory writes are to be  
prevented during the Register Write process. Otherwise, W state is “don’t care”.  
Note: tMRWPW = tMRWS = tMRWH = 4 cycles (minimum).  
Note: Inadvertent memory reads will occur while MRW and R are Low during the Register Write process. The memory reads are  
harmless, and can be ignored.  
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Post Input Training Requirements  
In this case, MRW is driven asynchronously, whereas R, W, and SA[10:1] are all driven synchronously (i.e. they all meet setup and  
hold time specs to CK). When Register Write Mode is utilized in this manner, multiple registers can be programmed during any  
particular instance that MRW is asserted High. The timing diagrams below arbitrarily show four registers programmed while MRW  
is asserted High, but in practice it can be any number greater than or equal to one.  
The requirements for this usage case are as follows:  
• At least 16 NOPs must be initiated before and after the Register Write(s).  
• MRW High must meet minimum setup time requirements (tMRWS) to the CK that generates the first Register Write.  
• MRW High must meet minimum hold time requirements (tMRWH) from the CK that generates the first NOP after the last Reg-  
ister Write.  
• R must be driven Low (synchronously) and SA[10:1] must be driven Valid (synchronously) for each Register Write.  
• W state is a “don’t care” (synchronously) for each Register Write.  
Note: tMRWS = tMRWH = 4 cycles (minimum).  
Asynchronous Register Write Timing Diagram - Pre Input Training  
16 NOPs  
Register Write Mode  
16 NOPs  
CK  
t
t
t
MRWH  
MRWS  
MRWPW  
SA[10:1]  
W
Register #n  
Must be “high” to prevent memory write; “don’t care” otherwise  
R
MRW  
Asynchronous Register Write Timing Diagram - Post Input Training  
Read / Write  
16 NOPs  
Register Write Mode  
16 NOPs  
Read / Write  
CK  
tIVKH tKHIX  
V
V
V
V
V
V
V
V
V
SA[10:1]  
Reg #a  
X
Reg #b  
Reg #c  
X
Reg #d  
X
X
W
R
t
t
MRWH  
MRWS  
MRW  
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Register Write Mode Utilization - Synchronous Method  
Register Write Mode can also be utilized synchronously up to the full operating speed of the device. However, MRW cannot be  
trained using Loopback Mode, so the ability to use it synchronously may be limited to slower operating frequencies where the lack  
of training capability is less problematic for the user.  
In this case, MRW, R, W, and SA[10:1] are all driven synchronously (i.e. they all meet setup and hold time specs to CK). When  
Register Write Mode is utilized in this manner, multiple registers can be programmed in successive cycles. The timing diagrams  
below arbitrarily show four registers programmed in successive cycles, but in practice it can be any number greater than or equal to  
one.  
The requirements for this usage case are as follows:  
• At least 16 NOPs must be initiated before and after the Register Write(s).  
• MRW must be driven High (synchronously), R must be driven Low (synchronously), and SA[10:1] must be driven Valid (syn-  
chronously) for each Register Write.  
• W state is a “don’t care” (synchronously) for each Register Write.  
Synchronous Register Write Timing Diagram  
Read / Write  
16 NOPs  
Register Write Mode  
16 NOPs  
Read / Write  
CK  
tIVKH tKHIX  
V
V
V
V
V
V
V
V
V
SA[10:1]  
Reg #a  
X
Reg #b  
Reg #c  
X
Reg #d  
X
X
W
R
tRVKH tKHRX  
MRW  
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Register Description  
As described previously, Register Write Mode provides the ability to program up to sixteen distinct 6-bit configuration registers us-  
ing SDR timing on the SA[10:1] address input pins. Specifically, SA[4:1] are used to select one of the sixteen distinct registers, and  
SA[10:5] are used to program the six data bits of the selected register.  
The registers are defined as follows:  
Address  
Pin  
SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1  
8G  
6G  
8J  
6J  
8M  
6M  
8P  
6P  
8T  
6T  
Reg #  
Bit Usage  
Register Data Bits  
Register Select Bits  
Active  
Active  
Active  
Active  
Active  
Unused  
Active  
RLM  
PLE  
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
RSVD[2:0]  
1
LBK[1:0]  
LBKE  
2
3
DZT[1:0]  
KDZT[1:0]  
CZT[1:0]  
CKZT[1:0]  
AZT[1:0]  
4
All Others except “111X”  
5 ~ 13  
14 ~ 15  
Reserved for GSI Internal Use Only  
1
1
1
X
Notes:  
1. Unused/unlabeled register bits should be written to “0”.  
2. The RSVD[2:0] bits in Register #1 should be written to “100”.  
3. Registers #14 and #15 are reserved for GSI internal use only. Users should not access these registers.  
Register Bit Definitions  
Read Latency Select  
PLL Enable  
RLM  
PLE  
0
1
1
Read Latency = 5 cycles  
reserved  
0
1
0
Disable PLL, if PLL pin = 0  
Enable PLL  
POR/RST Default  
POR/RST Default  
Note: The power-on / reset default value of the RLM register bit is “1”. Consequently, Register Write Mode must be used to set the  
RLM bit to “0”, to program RL=5 in these devices, prior to issuing Read operations.  
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Loopback Mode Enable  
Loopback Mode Select  
LBKE  
LBK[1:0]  
0
1
0
Disable Loopback Mode  
Enable Loopback Mode  
POR/RST Default  
0
0
1
1
0
0
1
0
1
0
XOR Loopback Mode, input group #1  
XOR Loopback Mode, input group #2  
INV Loopback Mode, input group #1  
INV Loopback Mode, input group #2  
POR/RST Default  
Note: In the ODT Control register bit definitions below, MZT[1:0] and PZT[1:0] pins set the default state of the register bits at pow-  
er-up and whenever RST is asserted High. The register bits can then be overwritten (via Register Write Mode), while RST is de-as-  
serted Low, to change the state of the feature controlled by the register bits.  
Input Clock ODT Control  
Address & Control ODT Control  
CKZT1  
CKZT0  
KDZT0  
AZT1  
AZT0  
CZT0  
KDZT1  
CZT1  
0
0
1
1
0
1
0
1
disabled  
0
0
1
1
0
1
0
1
disabled  
enabled: PU = PD = RT  
enabled: PU = PD = 2*RT  
reserved  
enabled: PU = PD = RT  
enabled: PU = PD = 2*RT  
reserved  
00, if MZT[1:0] = 00 or PZT0 = 0  
01, if MZT[1:0] = 01 and PZT0 = 1  
10, if MZT[1:0] = 10 and PZT0 = 1  
11, if MZT[1:0] = 11 and PZT0 = 1  
00, if MZT[1:0] = 00 or PZT1 = 0  
01, if MZT[1:0] = 01 and PZT1 = 1  
10, if MZT[1:0] = 10 and PZT1 = 1  
11, if MZT[1:0] = 11 and PZT1 = 1  
POR/RST Default  
POR/RST Default  
Write Data ODT Control  
DZT1  
DZT0  
0
0
1
1
0
disabled  
1
0
1
enabled: PU = PD = RT  
enabled: PU = PD = 2*RT  
reserved  
00, if MZT[1:0] = 00  
01, if MZT[1:0] = 01  
10, if MZT[1:0] = 10  
11, if MZT[1:0] = 11  
POR/RST Default  
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Signal Timing Training  
Signal timing training (aka “deskew”) is often required for reliable signal transmission between components at the I/O speeds  
supported by these devices. Typically, the timing training is performed in the following sequence:  
Step 1: Address / Control input training.  
These devices support a special Loopback Mode of operation to facilitate address / control input training.  
Step 2: Read Data output training.  
These devices support a special Loopback Mode of operation to facilitate read data output training.  
Alternatively, slow-frequency Memory Write operations can be used to store DDR data patterns in the memory array  
reliably (full-frequency Memory Write operations cannot be used because write data signals have not been trained yet),  
and full-frequency Memory Read operations can then be used to train the read data output signals.  
Step 3: Write Data input training.  
Since address, control, and read data signals have already been trained at this point, full-frequency Memory Write and  
Read operations can then be used to train the write data inputs.  
Loopback Mode  
These devices support two distinct Loopback Modes of operation, which can be used to:  
1. Perform per-pin training on the address (SA), control (R, W), and write data clock (KD, KD) inputs.  
2. Perform per-pin training on the read data (Q) outputs.  
In both cases, SA, R, W, KD, KD input pin values are sampled, logically manipulated, and looped back to Q output pins.  
Register bit LBKE is used to enable/disable Loopback Mode. When LBKE = 1 and MRW = 0, Loopback Mode is enabled, and  
Memory Read and Write operations are blocked regardless of the states of R and W. When LBKE = 0 or MRW = 1, Loopback  
Mode is disabled. See the State Truth Table for more information.  
Register bits LBK[1:0] are used to select between the two distinct Loopback Modes supported by the design (controlled by LBK1),  
and between the two groups of inputs used during the selected Loopback Mode (controlled by LBK0), as follows:  
• LBK[1:0] = 00: selects XOR LBK Mode using Input Group 1. Loopback Mode “00”.  
• LBK[1:0] = 01: selects XOR LBK Mode using Input Group 2. Loopback Mode “01”.  
• LBK[1:0] = 10: selects INV LBK Mode using Input Group 1. Loopback Mode “10”.  
• LBK[1:0] = 11: selects INV LBK Mode using Input Group 2. Loopback Mode “11”.  
Note: For convenience, KD clocks have been included in the group of inputs that can be trained via Loopback Mode. However,   
the timing requirement for KD clocks is that their edges be tightly aligned to CK clock edges, unlike the timing requirement for  
address/control signals, whose edges must be centered (approximately) between CK edges in order to optimize setup and hold  
times to those CK edges. Consequently, it is questionable whether Loopback Mode can be used to train KD clocks effectively.  
Loopback Latency  
Loopback Latency (“LBKL”) - i.e. the number of cycles from when the inputs are sampled to when the proper result appears on the  
output pins, is equal to 7 cycles.  
Enabling Loopback Mode  
Loopback Mode is enabled as follows:  
Step 1: Initiate a Register Write operation with SA[10:1] = “000ab1.0010” to select Register #2, set LBKE = 1 to enable  
Loopback Mode, and set LBK[1:0] to “ab” to select Loopback Mode “ab”.  
Step 2: Wait 16 cycles for new register settings to take effect.  
Loopback Mode “ab” is enabled after step 2 because MRW = 0, LBKE = 1, and LBK[1:0] = “ab”.  
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Changing Loopback Modes  
Once enabled, Loopback Mode can be changed as follows  
Step 1: Initiate a Register Write operation with SA[10:1] = “000cd1.0010” to select Register #2, keep LBKE = 1 to keep  
Loopback Mode enabled, and set LBK[1:0] to “cd” to select Loopback Mode “cd”.  
Step 2: Wait 16 cycles for new register settings to take effect.  
Loopback Mode “cd” is enabled after step 2 because MRW = 0, LBKE = 1, and LBK[1:0] = “cd”.  
Disabling Loopback Mode  
Loopback Mode is disabled as follows:  
Step 1: Initiate a Register Write operation with SA[10:1] = “000xx0.0010” to select Register #2 and set LBKE = 0 to disable  
Loopback Mode.  
Step 2: Wait 16 cycles for new register settings to take effect.  
Loopback Mode is disabled after step 2 because LBKE = 0.  
XOR LBK Mode  
XOR LBK Mode is for address/control input training. It is defined as follows:  
• Each input pin of the selected input group is sampled on CK and CK.  
• For each input sampled, the value sampled on CK is XORed with the value sampled on CK.  
• For each input sampled, the XOR result is subsequently driven out on its associated output pin (concurrently with CQ) for one  
full clock cycle, beginning “LBKL” cycles after the input is sampled.  
Consequently, the output data pattern is always SDR regardless of the input data pattern, and regardless whether the SRAM  
samples the inputs correctly or not. The SDR output data pattern enables address/control inputs to be trained before data outputs.  
XOR LBK Mode enables the controller to input various SDR and DDR data patterns on a particular input, and then determine  
whether the SRAM sampled them correctly or not by observing SDR data patterns on the associated output. Via multiple iterations  
of this process, the controller can adjust its output timing (in order to adjust the SRAM input timing) until optimum setup and hold  
margin at both SRAM input sample points is achieved, thereby individually “training” each address/control input pin.  
INV LBK Mode  
INV LBK Mode is primarily for read data output training. It is defined as follows:  
• Each input pin of the selected input group is sampled on CK and CK.  
• For each input sampled, the value sampled on CK is subsequently driven out on its associated output pin (concurrently with  
CQ) for half a clock cycle, beginning “LBKL” cycles after the input is sampled.  
• For each input sampled, the value sampled on CK is inverted and then subsequently driven out on its associated output pin (con-  
currently with CQ) for half a clock cycle, beginning “LBKL + 0.5” cycles after the input is sampled.  
Consequently, the output data pattern is DDR if the input data pattern is SDR (and vice versa), provided the SRAM samples the  
inputs correctly. Therefore, to ensure deterministic output behavior, address/control inputs should be trained before data outputs.  
INV LBK Mode enables the controller to input various SDR (or DDR) data patterns on a particular input, to generate deterministic  
DDR (or SDR) data patterns on a particular output. The controller latches the output as it would during a normal Read operation,  
and verifies whether it received the expected values or not. Via multiple iterations of this process, the controller can adjust its input  
timing until optimum setup and hold margin at both controller input sample points is achieved, thereby individually “training” each  
read data output pin.  
Note: INV LBK Mode can be used for address/control input training, if desired. However, such usage can be problematic because  
the output data pattern may be erroneous (i.e. it could be SDR or DDR regardless of the input pattern) if the SRAM samples the  
input incorrectly. In which case the controller may have difficulty detecting the erroneous behavior, and/or interpreting it.  
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Entering XOR LBK Mode  
16 NOPs Register Write Mode 16 NOPs  
(Enable XOR LBK)  
XOR LBK Mode  
(first 6 cycles of 11, for example)  
CK  
Input  
CQ  
Output  
NOP State  
Undefined  
Output begins reflecting XOR LBK result ...  
Exiting XOR LBK Mode  
XOR LBK Mode continued  
(last 5 cycles of 11, for example)  
Register Write Mode 16 NOPs  
(Disable XOR LBK)  
Read / Write  
CK  
Input  
CQ  
Output  
... after Loopback Latency  
Undefined  
NOP State  
Note: “Input” represents any loop-backed input pin. “Output” represents the output pin on which “Input” is looped back.  
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Entering INV LBK Mode  
16 NOPs Register Write Mode 16 NOPs  
(Enable INV LBK)  
INV LBK Mode  
(first 6 cycles of 11, for example)  
CK  
Input  
CQ  
Output  
NOP State  
Undefined  
Output begins reflecting INV LBK result ...  
Exiting INV LBK Mode  
INV LBK Mode continued  
(last 5 cycles of 11, for example)  
Register Write Mode 16 NOPs  
(Disable INV LBK)  
Read / Write  
CK  
Input  
CQ  
Output  
... after Loopback Latency  
Undefined  
NOP State  
Note: “Input” represents any loop-backed input pin. “Output” represents the output pin on which “Input” is looped back.  
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Loopback Mode Input Group Definition and Input-to-Output Pin Mapping  
Inputs are divided into 2 groups because there are up to 28 inputs to train (22 address, 2 control, and 4 KD clocks), but as few as 18  
outputs available to loop them back to (in x18 devices).  
There are 18 inputs per group - one per Q output in x18 devices, and one per two Q outputs in x36 devices.  
Input Pins  
Input Signals  
Output Pins  
Output Signals  
Bit #  
GP1  
GP2  
GP1  
GP2  
x18  
x36  
x18  
x36  
1
2
3
4
5
6
7
8P  
8M  
8J  
8V  
8T  
---  
SA4  
SA6  
NU  
SA2  
RSVD  
KD0  
KD0  
W
13V  
13T  
13P  
13N  
12J  
12G  
12F  
13V, 12W  
13T, 12U  
13P, 12R  
13N, 12P  
12J, 12M  
12G, 13H  
12F, 13G  
Q8  
Q7  
Q6  
Q5  
Q4  
Q3  
Q2  
Q8, Q17  
Q7, Q16  
Q6, Q15  
Q5, Q14  
Q4, Q13  
Q3, Q12  
Q2, Q11  
SA8  
9H  
8G  
9F  
8E  
9L  
9K  
7H  
---  
SA16  
SA10  
SA18  
SA12  
RSVD  
8
9D  
---  
SA20  
RSVD  
12D  
12D, 13E  
Q1  
Q1, Q10  
9
8C  
6T  
6P  
6M  
6J  
---  
---  
SA14  
SA1  
RSVD  
RSVD  
SA21  
RSVD  
R
12B  
2W  
2U  
2R  
2P  
12B, 13C  
2W, 1V  
2U, 1T  
2R, 1P  
2P, 1N  
2M, 2J  
1H, 2G  
1G, 2F  
1E, 2D  
1C, 2B  
Q0  
Q0, Q9  
10  
11  
12  
13  
14  
15  
16  
17  
18  
Q9  
Q18, Q27  
Q19, Q28  
Q20, Q29  
Q21, Q30  
Q22, Q31  
Q23, Q32  
Q24, Q33  
Q25, Q34  
Q26, Q35  
6V  
---  
SA3  
Q10  
Q11  
Q12  
Q13  
Q14  
Q15  
Q16  
Q17  
SA5  
7N  
5L  
5K  
---  
SA7  
5H  
6G  
5F  
6E  
5D  
SA15  
SA9  
KD1  
2M  
1H  
1G  
1E  
KD1  
SA17  
SA11  
SA19  
RSVD  
RSVD  
SA13  
---  
6C  
1C  
Notes:  
1. Blue shading indicates input pins that are unused (NU) in certain device configurations. During Loopback Mode, the associated  
output pins loop back the states of those input pins regardless whether they are used or unused.  
2. Gray shading indicates Group 2 inputs that are reserved (RSVD) for future use. During Loopback Mode, the associated output  
pins act as if they were looping back input pins tied Low.  
3. The 18 unused Q in x18 devices remain in their “NU” states during Loopback Mode.  
Rev: 1.02 3/2016  
18/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
Address Bus Utilization  
The address bus is a non-multiplexed SDR bus. One memory address may be loaded per cycle - a read address at CK or a write  
address at CK; consequently only one memory operation - a Read or a Write - may be initiated per clock cycle. The address bus is  
also sampled at CK during a Register Write operation.  
Address Bit Encoding  
SA Address Bits  
Addr  
Load  
Command  
Device  
21 20 19 18 17 16 15 14 13 12 11 10  
x36 NU Address  
Address  
Address  
Address  
9
8
7
6
5
4
3
2
1
0
NU  
NU  
NU  
NU  
NU  
NU  
Read  
Write  
CK  
CK  
CK  
x18  
x36 NU  
x18  
x36 NU  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register Data  
Register Data  
Register #  
Register #  
Register  
Write  
x18  
X
Read Latency  
Read Latency (i.e. the number of cycles from read command input to first read data output) is specified as follows:  
Read Latency  
Comment  
5 cycles  
First read data output 5 cycles after read command input  
Note: The RLM register bit must be written to “0” in these devices prior to initiating Read operations, to set Read Latency = 5 cycles.  
Write Latency  
Write Latency (i.e. the number of cycles from write command input to first write data input) is specified as follows:  
Write Latency  
Comment  
-1 cycle  
First write date input 1 cycle before write command input  
Read / Write Coherency  
These devices are fully coherent. That is, Read operations always return the most recently written data to a particular address, even  
when a Read operation to a particular address occurs one cycle after a Write operation to the same address.  
Rev: 1.02 3/2016  
19/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
State Truth Table  
RST MRW LBKE  
R
W
SA  
D
SRAM State  
Q
1
0
0
0
0
X
1
0
1
0
X
X
1
X
0
X
X
X
X
V
X
X
X
X
Reset  
NOP State  
Undefined  
Loopback  
Register Write Mode  
Loopback Mode  
X
1
X
0
Memory Mode  
(Read, Write, NOP)  
See Clock Truth  
Table  
See Clock Truth Table  
X
Note: 1 = High; 0 = Low; V = Valid; X = don’t care.  
Clock Truth Table  
Previous  
Operation  
Current  
Operation  
SA MRW  
R
W
D
Q
CK CK CK CK  
KD  
KD  
KD  
KD  
CQ  
(t  
CQ  
CQ  
(t  
CQ  
(t  
)
(t )  
n–1  
n
(t )  
(t )  
(t )  
(t )  
(t  
)
(t  
)
(t )  
(t  
)
)
(t  
)
)
(t  
)
n
n
n
n
n-1  
n-½  
n
n+½  
n+5  
n+5½  
n+6  
n+6½  
X
X
X
V
V
V
V
V
0
0
0
0
0
0
0
1
1
1
1
X
1
X
0
0
0
1
1
X
1
NOP  
Write  
Read  
NOP  
Read  
NOP  
Write  
NOP  
NOP  
NOP  
NOP  
X
X
—
—
—
0
0
—
—
—
—
—
D3  
X
D4  
X
NOP  
Q3  
Q4  
0
Write  
D1  
D1  
X
D2  
D2  
X
D3  
D3  
D4  
D4  
0
0
Write  
Q3  
Q1  
Q1  
Q4  
Q2  
Q2  
X
X
X
X
Read  
—
—
—
—
Q3  
Q3  
Q4  
Q4  
Read  
D3  
X
D4  
X
Register Write  
NOP  
Undefined  
0
Undefined  
—
X
X
Notes:  
1. 1 = High; 0 = Low; V = Valid; X = don’t care.  
2. D1, D2, D3, and D4 indicate the first, second, third, and fourth pieces of write data transferred during Write operations.  
3. Q1, Q2, Q3, and Q4 indicate the first, second, third, and fourth pieces of read data transferred during Read operations.  
4. Q pins are driven Low for one cycle in response to NOP and Write commands, 5 cycles after the command is sampled, except when pre-  
ceded by a Read command.  
Rev: 1.02 3/2016  
20/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
Input Timing  
These devices utilize three pairs of positive and negative input clocks, CK & CK and KD[1:0] & KD[1:0], to latch the various  
synchronous inputs. Specifically:  
During Memory Mode, CK latches address (SA) inputs, and CK latches control (R, W, MRW) inputs.  
During Register Write Mode, CK latches address and control inputs.  
During Loopback Mode, CK and CK latch address, control, and write data clock (KD, KD) inputs.  
During Memory Mode, KD[1:0] and KD[1:0] latch particular write data (D) inputs, as follows:  
• KD0 and KD0 latch D[17:0] in x36 devices, and D[8:0] in x18 devices.  
• KD1 and KD1 latch D[35:18] in x36 devices, and D[17:9] in x18 devices.  
Output Timing  
These devices provide two pairs of positive and negative output clocks (aka “echo clocks”), CQ[1:0] & CQ[1:0], whose timing is  
tightly aligned with read data in order to enable reliable source-synchronous data transmission.  
These devices utilize a PLL to control output timing. When the PLL is enabled, it generates 0and 180phase clocks from CK  
that control read data output clock (CQ, CQ), read data (Q), and read data valid (QVLD) output timing, as follows:  
• CK+0generates CQ[1:0], CQ[1:0], Q1 active, and Q2 inactive.  
• CK+180generates CQ[1:0], CQ[1:0], Q1 inactive, Q2 active, and QVLD active/inactive.  
Note: Q1 and Q2 indicate the first and second pieces of read data transferred in any given clock cycle during Read operations.  
When the PLL is enabled, CQ is aligned to an internally-delayed version of CK. See the AC Timing Specifications for more  
information.  
CQ[1:0] and CQ[1:0] align with particular Q and QVLD outputs, as follows:  
• CQ0 and CQ0 align with Q[17:0], QVLD0 in x36 devices, and Q[8:0], QVLD0 in x18 devices.  
• CQ1 and CQ1 align with Q[35:18], QVLD1 in x36 devices, and Q[17:9], QVLD0 in x18 devices.  
Rev: 1.02 3/2016  
21/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
Driver Impedance Control  
Programmable Driver Impedance is implemented on the following output signals:  
• CQ, CQ, Q, QVLD.  
Driver impedance is programmed by connecting an external resistor RQ between the ZQ pin and V  
.
SS  
Driver impedance is set to the programmed value within 320K cycles after input clocks are operating within specification and RST  
is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system.  
Output Signal  
Pull-Down Impedance (R  
)
Pull-Up Impedance (R  
)
OUTL  
OUTH  
CQ, CQ, Q, QVLD  
RQ*0.2 15%  
RQ*0.2 15%  
Notes:  
1.  
2. The mismatch between R  
R
and R  
apply when 175 RQ 225.  
OUTL  
OUTH  
and R  
is less than 10%, guaranteed by design.  
OUTL  
OUTH  
ODT Impedance Control  
Programmable ODT Impedance is implemented on the following input signals:  
• CK, CK, KD, KD, SA, R, W, MRW, D.  
ODT impedance is programmed by connecting an external resistor RT between the ZT pin and V  
.
SS  
ODT impedance is set to the programmed value within 320K cycles after input clocks are operating within specification and RST  
is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system.  
Input Signal  
Register Bits  
Pull-Down Impedance (R  
)
Pull-Up Impedance (R  
)
INL  
INH  
CKZT[1:0] = 00  
CKZT[1:0] = 01  
CKZT[1:0] = 10  
CKZT[1:0] = 11  
KDZT[1:0] = 00  
KDZT[1:0] = 01  
KDZT[1:0] = 10  
KDZT[1:0] = 11  
AZT[1:0] = 00  
AZT[1:0] = 01  
AZT[1:0] = 10  
AZT[1:0] = 11  
off  
off  
RT 15%  
RT*2 20%  
reserved  
off  
RT 15%  
RT*2 20%  
reserved  
off  
CK, CK  
RT 15%  
RT*2 20%  
reserved  
off  
RT 15%  
RT*2 20%  
reserved  
off  
KD, KD  
RT 15%  
RT*2 20%  
reserved  
RT 15%  
RT*2 20%  
reserved  
SA  
Rev: 1.02 3/2016  
22/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
Input Signal  
Register Bits  
Pull-Down Impedance (R  
)
Pull-Up Impedance (R  
)
INL  
INH  
CZT[1:0] = 00  
CZT[1:0] = 01  
CZT[1:0] = 10  
CZT[1:0] = 11  
DZT[1:0] = 00  
DZT[1:0] = 01  
DZT[1:0] = 10  
DZT[1:0] = 11  
off  
off  
RT 15%  
RT*2 20%  
reserved  
off  
RT 15%  
RT*2 20%  
reserved  
off  
R, W, MRW  
RT 15%  
RT*2 20%  
reserved  
RT 15%  
RT*2 20%  
reserved  
D
Notes:  
1.  
2. The mismatch between R and R is less than 10%, guaranteed by design.  
R
and R apply when 105 RT 135  
INH  
INL  
INL  
INH  
3. All ODT is disabled during JTAG EXTEST and SAMPLE-Z instructions.  
Note: When ODT impedance is enabled on a particular input, that input should always be driven High or Low; it should never be  
tri-stated (i.e., in a High- Z state). If the input is tri-stated, the ODT will pull the signal to V / 2 (i.e., to the switch point of the  
DDQ  
diff-amp receiver), which could cause the receiver to enter a meta-stable state and consume more power than it normally would.  
This could result in the device’s operating currents being higher.  
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
Absolute Maximum Ratings  
Parameter  
Symbol  
Rating  
Units Notes  
V
Core Supply Voltage  
I/O Supply Voltage  
-0.3 to +1.4  
V
V
DD  
V
-0.3 to V  
DDQ  
DD  
V
V
V
-0.3 to V  
+ 0.3  
DDQ  
IN1  
IN2  
IN3  
Input Voltage (HS)  
V
2
3
V
- 1.5 to +1.7  
DDQ  
-0.3 to V  
+ 0.3  
Input Voltage (LS)  
Junction Temperature  
Storage Temperature  
Notes:  
V
DDQ  
T
0 to 125  
-55 to 125  
C  
C  
J
T
STG  
1. Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recom-  
mended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions for an extended period of time  
may affect reliability of this component.  
2. Parameters apply to High Speed Inputs: CK, CK, KD, KD, SA, D, R, W, MRW. V and V must both be met.  
IN1  
IN2  
3. Parameters apply to Low Speed Inputs: RST, PLL, MZT, PZT.  
Recommended Operating Conditions  
Parameter  
Symbol  
Min  
Typ  
Max  
Units Notes  
V
V
Core Supply Voltage (-933 speed grade)  
Core Supply Voltage (-800 speed grade)  
I/O Supply Voltage  
1.25  
1.15  
1.15  
0
1.3  
1.2  
1.2  
—
1.35  
1.35  
V
V
DD  
DD  
V
V
V
DDQ  
DD  
T
Commercial Junction Temperature  
Industrial Junction Temperature  
85  
C  
C  
JC  
T
-40  
—
100  
JI  
Note: For reliability purposes, power supplies must power up simultaneously, or in the following sequence:  
, V , V , V , and Inputs.  
V
SS DD DDQ REF  
Power supplies must power down simultaneously, or in the reverse sequence.  
Thermal Impedances  
JA (C°/W)  
JA (C°/W)  
JA (C°/W)  
Package  
JB (C°/W)  
JC (C°/W)  
Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s  
FBGA  
13.67  
10.28  
9.31  
3.08  
0.13  
Rev: 1.02 3/2016  
24/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
I/O Capacitance  
Parameter  
Symbol  
Min  
Max  
Units Notes  
C
Input Capacitance  
Output Capacitance  
—
—
5.0  
5.5  
pF  
pF  
1, 3  
2, 3  
IN  
C
OUT  
Notes:  
1.  
V
= V /2.  
DDQ  
IN  
2.  
V
= V /2.  
OUT  
DDQ  
3. T = 25C, f = 1 MHz.  
A
Input Electrical Characteristics  
Parameter  
Symbol  
Min  
Typ  
Max  
Units Notes  
V
0.48 * V  
0.52 * V  
DDQ  
DC Input Reference Voltage  
DC Input High Voltage (HS)  
DC Input Low Voltage (HS)  
DC Input High Voltage (LS)  
DC Input Low Voltage (LS)  
AC Input Reference Voltage  
AC Input High Voltage (HS)  
AC Input Low Voltage (HS)  
AC Input High Voltage (LS)  
AC Input Low Voltage (LS)  
0.50 * V  
V
V
V
V
V
V
V
V
V
V
—
1, 6  
2, 6  
7
REFdc  
DDQ  
DDQ  
V
V
+ 0.08  
V
+ 0.15  
- 0.08  
+ 0.15  
0.80 * V  
0.20 * V  
V
IH1dc  
REF  
DDQ  
DDQ  
DDQ  
V
V
-0.15  
0.75 * V  
IL1dc  
REF  
V
V
IH2dc  
DDQ  
DDQ  
DDQ  
V
0.25 * V  
0.53 * V  
-0.15  
0
7
IL2dc  
DDQ  
DDQ  
V
0.47 * V  
0.50 * V  
3
REFac  
DDQ  
DDQ  
V
V
+ 0.15  
V
+ 0.25  
- 0.15  
+ 0.25  
0.80 * V  
0.20 * V  
V
1, 4~6  
2, 4~6  
4, 7  
4, 7  
IH1ac  
REF  
DDQ  
DDQ  
DDQ  
V
V
-0.25  
- 0.2  
IL1ac  
REF  
V
V
V
IH2ac  
DDQ  
DDQ  
DDQ  
V
-0.25  
0
0.2  
IL2ac  
Notes:  
1. “Typ” parameter applies when Controller R  
= 40and SRAM R = R = 120.  
INH INL  
OUTH  
2. “Typ” parameter applies when Controller R  
= 40and SRAM R = R = 120.  
INH INL  
OUTL  
3.  
4.  
V
V
is equal to V  
plus noise.  
REFdc  
REFac  
max and V min apply for pulse widths less than one-quarter of the cycle time.  
IH  
IL  
5. Input rise and fall times must be a minimum of 1V/ns, and within 10% of each other.  
6. Parameters apply to High Speed Inputs: CK, CK, KD, KD, SA, D, R, W, MRW.  
7. Parameters apply to Low Speed Inputs: RST, PLL, MZT, PZT.  
Rev: 1.02 3/2016  
25/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
Output Electrical Characteristics  
Parameter  
Symbol  
Min  
Typ  
Max  
Units Notes  
V
V
V
+ 0.15  
DDQ  
DC Output High Voltage  
DC Output Low Voltage  
AC Output High Voltage  
AC Output Low Voltage  
—
-0.15  
—
0.80 * V  
V
V
V
V
1, 3  
2, 3  
1, 3  
2, 3  
OHdc  
DDQ  
V
0.20 * V  
0.80 * V  
0.20 * V  
—
OLdc  
DDQ  
DDQ  
DDQ  
V
+ 0.25  
DDQ  
OHac  
V
-0.25  
—
OLac  
Note:  
1. “Typ” parameter applies when SRAM R  
= 40and Controller R = R = 120.  
INH INL  
OUTH  
OUTL  
2. “Typ” parameter applies when SRAM R  
= 40and Controller R = R = 120.  
INH INL  
3. Parameters apply to: CQ, CQ, Q, QVLD.  
Leakage Currents  
Parameter  
Symbol  
Min  
Max  
Units Notes  
I
-2  
-20  
-2  
2
2
uA  
uA  
uA  
uA  
1, 2  
1, 3  
1, 4  
5, 6  
LI1  
I
Input Leakage Current  
LI2  
I
20  
2
LI3  
I
Output Leakage Current  
-2  
LO  
Notes:  
1.  
V
= V to V  
.
DDQ  
IN  
SS  
2. Parameters apply to CK, CK, KD, KD, SA, D, R, W, MRW when ODT is disabled.  
Parameters apply to MZT, PZT.  
3. Parameters apply to PLL, TMS, TDI (weakly pulled up).  
4. Parameters apply to RST, TCK (weakly pulled down).  
5.  
V
= V to V  
.
DDQ  
OUT  
SS  
6. Parameters apply to CQ, CQ, Q, QVLD, TDO.  
Rev: 1.02 3/2016  
26/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
Operating Currents  
Parameter  
V
(nom)  
Symbol  
800 MHz  
933 MHz  
Units  
DD  
1.3V  
2050  
1800  
2700  
2450  
2250  
—
mA  
mA  
mA  
mA  
I
x18 Operating Current  
x36 Operating Current  
DD  
1.2V  
1.3V  
1.2V  
2950  
—
I
DD  
Notes:  
1.  
I
= 0 mA; V = V or V .  
IN IH IL  
OUT  
2. Applies at 100% alternating Reads and Writes.  
AC Test Conditions  
Parameter  
Symbol  
Conditions  
Units  
V
Core Supply Voltage (-933 speed grade)  
Core Supply Voltage (-800 speed grade)  
I/O Supply Voltage  
1.25 to 1.35  
1.15 to 1.35  
1.15 to 1.25  
0.6  
V
V
V
V
V
DD  
V
DD  
V
DDQ  
V
Input Reference Voltage  
REF  
V
Input High Level  
0.9  
IH  
V
Input Low Level  
0.3  
2.0  
0.6  
V
V/ns  
V
IL  
Input Rise and Fall Time  
—
—
Input and Output Reference Level  
Note: Output Load Conditions RQ = 200. Refer to figure below.  
AC Test Output Load  
50  
50  
Output  
V
/2  
DDQ  
5 pF  
Rev: 1.02 3/2016  
27/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
AC Timing Specifications (independent of device speed grade)  
Parameter  
Symbol  
Min  
Max  
Units Notes  
Input Clock Timing  
t
Clk High Pulse Width  
Clk Low Pulse Width  
0.45  
—
—
cycles  
cycles  
cycles  
ps  
1
1
KHKL  
t
0.45  
KLKH  
t
Clk High to Clk High  
0.45  
0.55  
+200  
60  
2
KHKH  
t
Clk High to Write Data Clk High  
Clk Cycle-to-Cycle Jitter  
PLL Lock Time  
-200  
3
KHKDH  
t
—
ps  
1,4,5  
6
KJITcc  
t
65,536  
—
cycles  
ns  
Klock  
t
Clk Static to PLL Reset  
30  
Output Timing  
+0.4  
—
7,12  
Kreset  
t
Clk High to Output Valid / Hold  
Clk High to Echo Clock High  
+1.2  
+1.2  
+75  
ns  
ns  
ps  
ps  
8
KHQV/X  
t
+0.4  
9
KHCQH  
t
Echo Clk High to Output Valid / Hold  
Echo Clk High to Echo Clock High  
-75  
10,12  
11,12  
CQHQV/X  
t
0.5*t  
(nom) - 25  
0.5*t  
(nom) + 25  
KHKH  
CQHCQH  
KHKH  
Notes:  
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal.  
1. Parameters apply to CK, CK, KD, KD.  
2. Parameter specifiesCK CK and KD KD requirements.  
3. Parameter specifies CK KD and CK KD requirements.  
4. Parameter specifies Cycle-to-Cycle (C2C) Jitter (i.e. the maximum variation from clock rising edge to the next clock rising edge).   
As such, it limits Period Jitter (i.e. the maximum variation in clock cycle time from nominal) to 30ps.   
And as such, it limits Absolute Jitter (i.e. the maximum variation in clock rising edge from its nominal position) to 15ps.  
5. The device can tolerated C2C Jitter greater than 60ps, up to a maximum of 200ps. However, when using a device from a particular speed  
grade, t (min) of that speed grade must be derated (increased) by half the difference between the actual C2C Jitter and 60ps. For  
KHKH  
example, if the actual C2C Jitter is 100ps, then t  
(min) for the -933 speed grade is derated to 1.09ns (1.07ns + 0.5*(100ps - 60ps)).  
KHKH  
6. VDD slew rate must be < 0.1V DC per 50ns for PLL lock retention. PLL lock time begins once VDD and input clock are stable.  
7. Parameter applies to CK.  
8. Parameters apply to Q, and are referenced to CK.  
9. Parameter specifies CK CQ timing.  
10. Parameters apply to Q, QVLD and are referenced to CQ & CQ.  
11. Parameter specifies CQ CQ timing. t  
(nom) is the nominal input clock cycle time applied to the device.  
KHKH  
12. Parameters are not tested. They are guaranteed by design, and verified through extensive corner-lot characterization.  
Rev: 1.02 3/2016  
28/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
AC Timing Specifications (variable with device speed grade)  
–933  
–800  
Parameter  
Symbol  
Units Notes  
Min  
Max  
Min  
Max  
Input Clock Timing  
t
Clk Cycle Time  
1.07  
6.0  
1.25  
6.0  
ns  
1
KHKH  
Input Setup & Hold Timing  
t
t
Input Valid to Clk High  
Clk High to Input Hold  
Input Pulse Width  
150  
150  
200  
150  
150  
—
—
—
—
—
150  
150  
200  
150  
150  
—
—
—
—
—
ps  
ps  
ps  
ps  
ps  
IVKH  
KHIX  
2
3
4
t
IPW  
t
t
MRW Valid to Clk High  
Clk High to MRW Hold  
RVKH  
KHRX  
Notes:  
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal.  
1. Parameters apply to CK, CK, KD, KD.  
2. Parameters apply to SA, and are referenced to CK (and to CK during Loopback Mode).  
Parameters apply to R, W, and are referenced to CK (and to CK during Loopback Mode).  
Parameters apply to D, and are referenced to KD & KD.  
Parameters apply to KD, KD, and are referenced to CK & CK during Loopback Mode.  
3. Parameter specifies the input pulse width requirements for each individual address, control, and data input. Per-pin deskew must be per-  
formed, to center the valid window of each individual input around the clock edge that latches it, in order for this parameter to be relevant  
to the application. The parameter is not tested; it is guaranteed by design and verified through extensive corner-lot characterization.  
4. Parameters apply to MRW, and are referenced to CK. Applicable when Register Write Mode is utilized synchronously.  
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
Memory Read and Write Timing Diagram  
Read  
Write  
Read  
NOP  
NOP  
Write  
Read  
Write  
Read  
Write  
NOP  
KD  
KD  
D
tKHKH  
tKHKL tKLKH tKHKH  
tIVKH  
tKHIX  
tIVKH  
tKHIX  
D21 D22 D23 D24  
D41 D42 D43 D44 D61 D62 D63 D64 D81 D82 D83 D84  
tKHKDH  
tKHKDH  
CK  
tKHKH  
tKHKL tKLKH tKHKH  
CK  
tIVKH tKHIX  
SA A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
tIVKH tKHIX  
R
W
tKHQV  
tKHQX  
Q11 Q12 Q13 Q14 Q31 Q32 Q33 Q34  
Q
QVLD  
tCQHQX  
tCQHQV  
tCQHQX  
tKHCQH  
tCQHQV  
CQ  
tCQHCQH  
CQ  
Note: MRW=0 (not shown).  
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© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
JTAG Test Mode Description  
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1  
functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller,  
etc.), ECCRAM, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, these devices  
contain a TAP Controller and multiple TAP Registers. The TAP Registers consist of one Instruction Register and multiple Data  
Registers.  
The TAP consists of the following four signals:  
Pin  
Pin Name  
I/O  
Description  
TCK  
Test Clock  
I
Induces (clocks) TAP Controller state transitions.  
Inputs commands to the TAP Controller.  
Sampled on the rising edge of TCK.  
TMS  
TDI  
Test Mode Select  
Test Data In  
I
I
Inputs data serially to the TAP Registers.  
Sampled on the rising edge of TCK.  
Outputs data serially from the TAP Registers.  
Driven from the falling edge of TCK.  
TDO  
Test Data Out  
O
Concurrent TAP and Normal ECCRAM Operation  
According to IEEE std. 1149.1, most public TAP Instructions do not disrupt normal device operation. In these devices, the only  
exceptions are EXTEST and SAMPLE-Z. See the Tap Registers section for more information.  
Disabling the TAP  
When JTAG is not used, TCK should be tied Low to prevent clocking the ECCRAM. TMS and TDI should either be tied High  
through a pull-up resistor or left unconnected. TDO should be left unconnected.  
JTAG DC Operating Conditions  
Parameter  
Symbol  
Min  
Max  
Units Notes  
V
0.75 * V  
V
+ 0.15  
DDQ  
JTAG Input High Voltage  
JTAG Input Low Voltage  
JTAG Output High Voltage  
JTAG Output Low Voltage  
V
V
V
V
1
TIH  
DDQ  
V
0.25 * V  
—
–0.15  
– 0.2  
1
TIL  
DDQ  
V
V
2, 3  
2, 4  
TOH  
DDQ  
V
—
0.2  
TOL  
Notes:  
1. Parameters apply to TCK, TMS, and TDI.  
2. Parameters apply to TDO.  
3.  
I
= –2.0 mA.  
TOH  
TOL  
4.  
I
= 2.0 mA.  
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© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
JTAG AC Timing Specifications  
Parameter  
Symbol  
Min  
Max  
Units  
t
TCK Cycle Time  
TCK High Pulse Width  
50  
20  
20  
10  
10  
10  
10  
10  
10  
—
0
—
—
—
—
—
—
—
—
—
10  
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
THTH  
t
THTL  
t
TCK Low Pulse Width  
TLTH  
t
TMS Setup Time  
MVTH  
t
TMS Hold Time  
THMX  
t
TDI Setup Time  
DVTH  
t
TDI Hold Time  
THDX  
t
Capture Setup Time (Address, Control, Data, Clock)  
Capture Hold Time (Address, Control, Data, Clock)  
TCK Low to TDO Valid  
CS  
t
CH  
t
TLQV  
t
TCK Low to TDO Hold  
TLQX  
JTAG Timing Diagram  
tTHTL  
tTLTH  
tTHTH  
TCK  
TMS  
TDI  
tMVTH tTHMX  
tDVTH tTHDX  
tTLQV  
tTLQX  
TDO  
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
TAP Controller  
The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations  
associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK.  
The TAP Controller enters the Test-Logic Reset state in one of two ways:  
1. At power up.  
2. When a logic 1 is applied to TMS for at least 5 consecutive rising edges of TCK.  
The TDI input receiver is sampled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.  
The TDO output driver is enabled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.  
TAP Controller State Diagram  
1
0
Test-Logic Reset  
0
1
1
1
Run-Test / Idle  
Select DR-Scan  
Select IR-Scan  
0
0
1
1
Capture-DR  
Capture-IR  
0
0
Shift-DR  
0
Shift-IR  
0
1
Exit1-DR  
0
1
Exit1-IR  
0
1
1
Pause-DR  
1
0
Pause-IR  
1
0
0
0
Exit2-DR  
1
Exit2-IR  
1
Update-DR  
Update-IR  
1
0
1
0
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GS81314LD19/37GK-933/800  
TAP Registers  
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output  
data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: Instruction Registers (IR), which are  
manipulated via the IR states in the TAP Controller, and Data Registers (DR), which are manipulated via the DR states in the TAP  
Controller.  
Instruction Register (IR - 3 bits)  
The Instruction Register stores the various TAP Instructions supported by ECCRAM. It is loaded with the IDCODE instruction  
(logic 001) at power-up, and when the TAP Controller is in the Test-Logic Reset and Capture-IR states. It is inserted between TDI  
and TDO when the TAP Controller is in the Shift-IR state, at which time it can be loaded with a new instruction. However, newly  
loaded instructions are not executed until the TAP Controller has reached the Update-IR state.  
The Instruction Register is 3 bits wide, and is encoded as follows:  
Code  
(2:0)  
Instruction  
Description  
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register  
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between  
TDI and TDO when the TAP Controller is in the Shift-DR state.  
Also transfers the contents of the Boundary Scan Register associated with output signals (Q, QVLD,  
CQ, CQ) directly to their corresponding output pins. However, newly loaded Boundary Scan Register  
contents do not appear at the output pins until the TAP Controller has reached the Update-DR state.  
Also disables all ODT.  
000  
EXTEST  
See the Boundary Scan Register description for more information.  
Loads a predefined device- and manufacturer-specific identification code into the ID Register when the  
TAP Controller is in the Capture-DR state, and inserts the ID Register between TDI and TDO when the  
TAP Controller is in the Shift-DR state.  
001  
010  
IDCODE  
See the ID Register description for more information.  
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register  
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between  
TDI and TDO when the TAP Controller is in the Shift-DR state.  
Also disables all ODT.  
SAMPLE-Z  
Also forces Q output drivers to a High-Z state.  
See the Boundary Scan Register description for more information.  
011  
100  
PRIVATE  
SAMPLE  
Reserved for manufacturer use only.  
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register  
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between  
TDI and TDO when the TAP Controller is in the Shift-DR state.  
See the Boundary Scan Register description for more information.  
101  
110  
PRIVATE  
PRIVATE  
Reserved for manufacturer use only.  
Reserved for manufacturer use only.  
Loads a logic 0 into the Bypass Register when the TAP Controller is in the Capture-DR state, and  
inserts the Bypass Register between TDI and TDO when the TAP Controller is in the Shift-DR state.  
See the Bypass Register description for more information.  
111  
BYPASS  
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Bypass Register (DR - 1 bit)  
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic  
0 when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the Capture-DR state. It is  
inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP  
Controller is in the Shift-DR state.  
ID Register (DR - 32 bits)  
The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE  
instruction has been loaded into the Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between  
TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the  
Shift-DR state.  
The ID Register is 32 bits wide, and is encoded as follows:  
See BSDL Model  
(31:12)  
GSI ID  
(11:1)  
Start Bit  
(0)  
XXXX XXXX XXXX XXXX XXXX  
0001 1011 001  
1
Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB,  
and the LSB serially shifts data out through TDO.  
Boundary Scan Register (DR - 129 bits)  
The Boundary Scan Register is equal in length to the number of active signal connections to the ECCRAM (excluding the TAP  
pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the logic states of all  
signals composing the ECCRAM’s I/O ring when the EXTEST, SAMPLE, or SAMPLE-Z instruction has been loaded into the  
Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between TDI and TDO when the EXTEST,  
SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the Shift-DR state.  
Additionally, the contents of the Boundary Scan Register associated with the ECCRAM outputs (Q, QVLD, CQ, CQ) are driven  
directly to the corresponding ECCRAM output pins when the EXTEST instruction is selected. However, after the EXTEST  
instruction has been selected, any new data loaded into Boundary Scan Register when the TAP Controller is in the Shift-DR state  
does not appear at the output pins until the TAP Controller has reached the Update-DR state.  
The value captured in the boundary scan register for NU pins is determined by the external pin state. The value captured in the  
boundary scan register for NC pins is 0 regardless of the external pin state. The value captured in the Internal Cell (Bit 129) is 1.  
Output Driver State During EXTEST  
EXTEST allows the Internal Cell (Bit 129) in the Boundary Scan Register to control the state of Q drivers. That is, when Bit 129 =  
1, Q drivers are enabled (i.e., driving High or Low), and when Bit 129 = 0, Q drivers are disabled (i.e., forced to High-Z state). See  
the Boundary Scan Register section for more information.  
ODT State During EXTEST and SAMPLE-Z  
ODT on all inputs is disabled during EXTEST and SAMPLE-Z.  
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GS81314LD19/37GK-933/800  
Boundary Scan Register Bit Order Assignment  
The table below depicts the order in which the bits are arranged in the Boundary Scan Register. Bit 1 is the LSB and Bit 129 is the  
MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out  
through TDO.  
Bit  
1
Pad  
7L  
Bit  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
Pad  
12F  
11G  
13G  
10G  
12G  
11H  
13H  
10J  
Bit  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
Pad  
12W  
10W  
8V  
Bit  
85  
Pad  
1T  
4R  
2R  
3P  
1P  
4P  
2P  
3N  
1N  
4M  
2M  
3L  
Bit  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
Pad  
1C  
2
7K  
86  
3C  
3
9L  
87  
2B  
4
9K  
9U  
8T  
88  
4B  
5
8J  
89  
5A  
6
7H  
9R  
8P  
90  
6A  
7
9H  
91  
6B  
8
7G  
8G  
9F  
9N  
8M  
6M  
7N  
5N  
7P  
92  
6C  
9
12J  
93  
5D  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
13K  
13L  
11L  
94  
6E  
8E  
95  
5F  
7D  
96  
6G  
5H  
9D  
12M  
10M  
13N  
11N  
12P  
10P  
13P  
11P  
12R  
10R  
13T  
11T  
12U  
10U  
13V  
11V  
97  
1L  
8C  
6P  
98  
1K  
2J  
6J  
7B  
5R  
6T  
99  
5K  
8B  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
4J  
5L  
9B  
7U  
5U  
6V  
1H  
3H  
2G  
4G  
1G  
3G  
2F  
4F  
1E  
3E  
2D  
4D  
Internal  
7A  
9A  
10B  
12B  
11C  
13C  
10D  
12D  
11E  
13E  
10F  
6W  
7Y  
4W  
2W  
3V  
1V  
4U  
2U  
3T  
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
260-Pin BGA Package Drawing (Package GK)  
C
Ø0.08 S  
Ø0.22 S C  
B S  
A S  
Ø0.50~Ø0.70(260x)  
PIN #1 CORNER  
13 12 11 10  
9 8 7 6 5 4 3  
2 1  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
13.20 0.05  
14.00 0.05  
B
1.00  
A
12.00  
0.05(4X)  
HEAT SPREADER  
4–R0.5 (MAX)  
C
SEATING PLANE  
Ball Pitch:  
1.00 Substrate Thickness: 0.51  
0.60 Mold Thickness:  
Ball Diameter:  
—
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
Ordering Information — GSI SigmaQuad-IVe ECCRAM  
Speed  
(MHz)  
T
Org  
Part Number  
Type  
Package  
A
8M x 18  
8M x 18  
8M x 18  
8M x 18  
4M x 36  
4M x 36  
4M x 36  
4M x 36  
GS81314LD19GK-933  
GS81314LD19GK-800  
GS81314LD19GK-933I  
GS81314LD19GK-800I  
GS81314LD37GK-933  
GS81314LD37GK-800  
GS81314LD37GK-933I  
GS81314LD37GK-800I  
SigmaQuad-IVe B4  
SigmaQuad-IVe B4  
SigmaQuad-IVe B4  
SigmaQuad-IVe B4  
SigmaQuad-IVe B4  
SigmaQuad-IVe B4  
SigmaQuad-IVe B4  
SigmaQuad-IVe B4  
ROHS-Compliant 260-Pin BGA  
ROHS-Compliant 260-Pin BGA  
ROHS-Compliant 260-Pin BGA  
ROHS-Compliant 260-Pin BGA  
ROHS-Compliant 260-Pin BGA  
ROHS-Compliant 260-Pin BGA  
ROHS-Compliant 260-Pin BGA  
ROHS-Compliant 260-Pin BGA  
933  
800  
933  
800  
933  
800  
933  
800  
C
C
I
I
C
C
I
I
Note: C = Commercial Temperature Range. I = Industrial Temperature Range.  
Rev: 1.02 3/2016  
38/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS81314LD19/37GK-933/800  
Revision History  
Rev. Code  
Types of Changes  
Format or Content  
Revisions  
GS81314LD1937GK_r1  
GS81314LD1937GK_r1.01  
GS81314LD1937GK_r1.02  
—
• Creation of new RL=5 -specific datasheet with no bank restrictions.  
• Changed -833 speed bin to -800, and reduced the V (min) spec to  
DD  
Content  
Content  
1.15V (in order to support 1.2V nominal).  
• Removed “Preliminary” from data sheets.  
•
Rev: 1.02 3/2016  
39/39  
© 2015, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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