GS815118T-150IT [GSI]
Standard SRAM, 1MX18, 10ns, CMOS, PQFP100;
| 型号： | GS815118T-150IT |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Standard SRAM, 1MX18, 10ns, CMOS, PQFP100 时钟 静态存储器 内存集成电路 |
| 文件： | 总32页 (文件大小：583K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS815118/36T-225/200/180/166/150/133
225 MHz–133 MHz
100-Pin TQFP
Commercial Temp
Industrial Temp
1M x 18, 512K x 36
16Mb Sync Burst SRAMs
3.3 V V
DD
2.5 V or 3.3 V I/O
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip read parity checking; even or odd selectable
• 3.3 V +10%/–5% core power supply
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
SCD Pipelined Reads
The GS815118/36T is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
-225 -200 -180 -166 -150 -133 Unit
Flow
Through
tCycle
tKQ
4.4 5.0 5.5 6.0 6.6 7.5 ns
2.5 3.0 3.2 3.5 3.8 4.0 ns
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
2-1-1-1 Curr (x18) 205 185 185 185 185 140 mA
Curr (x36) 240 210 210 210 210 160 mA
Pipeline
3-1-1-1
tKQ
tCycle
7.0 7.5 8.0 8.5 10.0 11.0 ns
8.5 10.0 10.0 10.0 10.0 15.0 ns
350 315 290 270 250 230 mA
410 370 340 315 290 260 mA
Curr (x18)
Curr (x36)
ByteSafe™ Parity Functions
The GS815118/36 features ByteSafe data security functions.
See detailed discussion following.
Functional Description
Sleep Mode
Applications
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
The GS815118/36T is a 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS815118/36T operates on a 3.3 V power supply. All
input are 3.3 V- and 2.5 V-compatible. Separate output power
(VDDQ) pins are used to decouple output noise from the
Controls
internal circuits and are 3.3 V- and 2.5 V-compatible.
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Rev: 1.01 11/2000
1/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Preliminary
GS815118/36T-225/200/180/166/150/133
GS815118 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A19
NC
NC
VDDQ
VSS
NC
DQA9
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
QE
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
VDDQ
4
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
FT
VDD
DP
VSS
DQB5
DQB6
VDDQ
5
6
7
8
9
1M X 18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Top View
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.01 11/2000
2/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
GS815136 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQB9
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
QE
VDD
DQC9
DQC8
DQC7
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
VDDQ
4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
DP
VSS
DQD1
DQD2
VDDQ
5
6
7
8
9
512K x 36
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
DQA9
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
DQD9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.01 11/2000
3/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
TQFP Pin Description
Typ
e
Pin Location
Symbol
Description
37, 36
A0, A1
A2–A18
A19
I
I
I
Address field LSBs and Address Counter preset Inputs
Address Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 92, 97
80
Address Inputs (x18 versions)
63, 62, 59, 58, 57, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8
I/O
Data Input and Output pins (x36 Version)
18, 19, 22, 23, 24, 25, 28, 29
DQA9, DQB9,
DQC9, DQD9
51, 80, 1, 30
I/O
I/O
Data Input and Output pins (x36 Version)
Data Input and Output pins (x18 Version)
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQA1–DQA9
DQB1–DQB9
51, 52, 53, 56, 57
75, 78, 79,
NC
—
No Connect (x18 Version)
1, 2, 3, 6, 7,
25, 28, 29, 30
16
66
DP
QE
I
O
I
Parity Input; 1 = Even, 0 = Odd
Parity Error Out; Open Drain Output
87
BW
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
93, 94
BA, BB
I
Byte Write Enable for DQC, DQD Data I/’s; active low
(x36 Version)
95, 96
BC, BD
I
95, 96
89
NC
—
No Connect (x18 Version)
Clock Input Signal; active high
CK
I
I
I
I
I
I
88
GW
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
98
E1
G
86
Output Enable; active low
83
ADV
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
84, 85
ADSP, ADSC
Rev: 1.01 11/2000
4/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
Typ
e
Pin Location
Symbol
Description
64
ZZ
TMS
TDI
I
I
Sleep Mode control; active high
Scan Test Mode Select
38
39
I
Scan Test Data In
42
TDO
TCK
FT
O
I
Scan Test Data Out
43
Scan Test Clock
14
31
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
LBO
VDD
I
15, 41, 65, 91
I
VSS
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
I
I
I/O and Core Ground
VDDQ
Output driver power supply
Rev: 1.01 11/2000
5/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
GS815118/36 Block Diagram
Register
A0–An
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
36
36
Register
D
Q
BB
BC
BD
4
4
Register
D
Q
Register
D
Q
Register
36
D
Q
36
36
32
Register
E1
D
Q
4
36
Parity
Encode
Register
D
Q
4
Parity
Compare
FT
G
36
1
Power Down
Control
DQx0–DQx9
QE
DP
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.01 11/2000
6/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
Mode Pin Functions
Mode Name
Pin
Name
State
Function
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Burst Order Control
Output Register Control
Power Down Control
LBO
H
L
FT
H or NC
L or NC
H
Active
ZZ
Standby, IDD = ISB
L
Check for Odd Parity
Check for Even Parity
ByteSafe Data Parity Control
DP
H or NC
Note:
There areis a pull-up devices on the DP and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.01 11/2000
7/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
BA
X
BB
X
BC
X
BD
X
Notes
1
Read
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
L
X
X
X
X
X
Note:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x36 version.
Rev: 1.01 11/2000
8/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
Synchronous Truth Table
Operation
State
3
4
Diagram
Address Used
E1
ADSP ADSC
ADV
W
DQ
5
Key
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
None
None
X
X
H
L
X
L
L
X
L
X
X
X
X
X
X
L
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
High-Z
None
X
L
L
H
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
R
L
L
X
H
X
H
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
Notes:
1. X = Don’t Care, H = High, L = Low
2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.01 11/2000
9/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CR
CW
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.01 11/2000
10/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.01 11/2000
11/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS
)
Symbol
VDD
Description
Value
Unit
Voltage on VDD Pins
–0.5 to 4.6
–0.5 to VDD
V
V
V
VDDQ
VCK
Voltage in VDDQ Pins
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 6
VI/O
–0.5 to VDDQ +0.5 (£ 4.6 V max.)
V
V
VIN
–0.5 to VDD +0.5 (£ 4.6 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
IIN
+/–20
+/–20
mA
mA
W
IOUT
PD
1.5
oC
oC
TSTG
–55 to 125
–55 to 125
TBIAS
Temperature Under Bias
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
VDD
VDDQ
VIH
Min.
3.135
2.375
1.7
Typ.
3.3
2.5
—
Max.
3.6
Unit
V
Notes
VDD
I/O Supply Voltage
V
1
2
2
3
3
VDD +0.3
Input High Voltage
V
VIL
Input Low Voltage
–0.3
0
—
0.8
70
85
V
TA
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
25
°C
°C
TA
–40
25
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V £ VDDQ £ 2.375 V
(i.e., 2.5 V I/O) and 3.6 V £ VDDQ £ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC.
Rev: 1.01 11/2000
12/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 2.0 V
VSS
50%
VDD
50%
VSS – 2.0 V
20% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Symbol
Test conditions
Typ.
4
Max.
5
Unit
CIN
VIN = 0 V
Input Capacitance
pF
6 (x36)
12 (x18) 12 (x18)
7 (x36)
CI/O
VOUT = 0 V
Input/Output Capacitance
pF
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
RQJA
Max
40
Unit
°C/W
°C/W
°C/W
Notes
1,2
single
four
—
RQJA
24
1,2
RQJC
9
3
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.01 11/2000
13/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
AC Test Conditions
Parameter
Input high level
Input low level
Conditions
2.3 V
0.2 V
Input slew rate
1 V/ns
Input reference level
Output reference level
Output load
1.25 V
1.25 V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225W
225W
DQ
30pF*
50W
5pF*
VT = 1.25 V
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
VDD ³ VIN ³ VIH
0 V £ VIN £ VIH
–1 uA
–1 uA
1 uA
300 uA
IINZZ
IINM
IOL
ZZ Input Current
VDD ³ VIN ³ VIL
0 V £ VIN £ VIL
–300 uA
–1 uA
1 uA
1 uA
Mode Pin Input Current
Output Leakage Current
Output Disable,
VOUT = 0 to VDD
–1 uA
1 uA
VOH
VOH
VOL
IOH = –4 mA, VDDQ = 2.375 V
IOH = –4 mA, VDDQ = 3.135 V
IOL = 4 mA
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
—
—
—
0.4 V
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
Rev: 1.01 11/2000
15/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
AC Electrical Characteristics
-225
-200
-180
-166
-150
-133
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock Cycle Time
tKC
tKQ
4.4
—
1.5
1.5
8.5
—
3.0
3.0
1.3
1.5
1.5
—
0
—
2.5
—
—
—
7.0
—
—
—
—
2.5
2.5
—
5.0
—
—
3.0
—
—
—
7.5
—
—
—
—
5.5
—
—
3.2
—
—
—
8.0
—
—
—
—
6.0
—
—
3.5
—
—
—
8.5
—
—
—
—
3.5
3.5
—
6.7
—
—
3.8
—
—
—
10.0
—
—
—
—
3.8
3.8
—
7.5
—
1.5
1.5
15.0
—
3.0
3.0
1.7
2
—
4.0
—
—
—
ns
ns
ns
ns
ns
Pipeline
tKQX
1.5
1.5
10.0
—
1.5
1.5
10.0
—
1.5
1.5
10.0
—
1.5
1.5
10.0
—
tLZ1
tKC
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKQ
11.0 ns
Flow
Through
tKQX
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.5
1.7
1.5
—
—
—
—
—
4.0
4.0
—
ns
ns
ns
ns
ns
ns
ns
tLZ1
tKH
tKL
Clock LOW Time
tHZ1
tOE
Clock to Output in High-Z
G to Output Valid
3.0 1.5 3.2
1.5
—
0
3.2
—
3.2
tOLZ1
G to output in Low-Z
0
—
0
—
0
0
tOHZ1
tS
G to output in High-Z
Setup time
—
1.5
0.5
5
2.5
—
—
—
—
1.5
0.5
5
3.0
—
—
—
—
1.5
0.5
5
3.2
—
—
—
—
1.5
0.5
5
3.5
—
—
—
—
1.5
0.5
5
3.8
—
—
—
—
1.5
0.5
5
4.0
—
—
—
ns
ns
ns
ns
Hold time
tH
tZZS2
ZZ setup time
tZZH2
tZZR
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
100
100
100
100
100
100
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
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Preliminary
GS815118/36T-225/200/180/166/150/133
Write Cycle Timing
Single Write
tS tH
Burst Write
Deselected
Write
CK
ADSP is blocked by E inactive
tKC
tKL
tKH
ADSP
tH
tH
tS
ADSC initiated write
ADSC
tS
ADV
ADV must be inactive for ADSP Write
tH
tS
WR2
WR3
WR1
A0–An
tS tH
GW
BW
tH
tS
tS
tH
WR3
WR1
WR2
BA–BD
E1
tS
tH
E1 masks ADSP
E1 only sampled with ADSP or ADSC
G
tS
tH
Write specified byte for 2A and all bytes for 2B, 2C& 2D
Hi-Z
D1A
D2C
D2D
D3A
DQA–DQD
D2A
D2B
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Preliminary
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Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tS
tKH
tS
tH
ADSP is blocked by E inactive
tKC
ADSP
ADSC
ADV
tH
ADSC initiated read
tH
tS
Suspend Burst
Suspend Burst
tS
tH
RD1
RD2
RD3
A0–An
GW
tS
tS
tH
tH
BW
BA–BD
tH
tS
E1 masks ADSP
E1
G
tOHZ
tOE
tKQX
tKQX
tHZ
tOLZ
Hi-Z
Q2B
Q2c
Q3A
Q1A
Q2A
Q2D
DQA–DQD
tLZ
tKQ
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
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Flow Through Read-Write Cycle Timing
Single Write
Burst Read
Single Read
CK
tS tH
tKC
ADSP is blocked by E inactive
ADSC initiated read
tKH tKL
ADSP
ADSC
tS tH
tS tH
ADV
tS
tH
RD2
RD1
WR1
A0–An
tS tH
GW
tH
tS
BW
tS
tH
BA–BD
WR1
tS
tH
E1 masks ADSP
E1
tOHZ
tOE
G
tS
tH
tKQ
Hi-Z
DQA–DQD
Q1A
D1A
Q2A
Q2A
Q2B
Q2c
Q2D
Burst wrap around to it’s initial state
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Preliminary
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Pipelined SCD Read Cycle Timing
Single Read
Burst Read
tKC
CK
tKL
tKH
tH
tH
tS
ADSP is blocked by E inactive
ADSP
ADSC
tS
ADSC initiated read
tS tH
Suspend Burst
ADV
tH
tS
RD2
RD3
RD1
A0–An
tS
tS
tH
tH
GW
BW
BWA–BWD
tH
tS
E1 masks ADSP
E1
tOE
G
tOHZ
tKQX
Q3A
tKQX
Q2A
tOLZ
tLZ
Hi-Z
DQA–DQD
Q1A
Q2B
Q2D
Q2c
tHZ
tKQ
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Preliminary
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Pipelined SCD Read-Write Cycle Timing
Single Write
Single Read
Burst Read
tKL
CK
tH
tS
tKH
tKC
ADSP is blocked by E inactive
ADSC initiated read
ADSP
ADSC
tS tH
tS tH
ADV
tS
tH
RD2
WR1
A0–An
RD1
tS
tH
GW
BW
tS
tH
tH
tS
WR1
BWA–BWD
E1
tS
tH
E1 masks ADSP
tOE
tOHZ
G
tS
tH
tKQ
Hi-Z
Q1A
D1A
Q2A
Q2B
Q2c
DQA–DQD
Q2D
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Preliminary
GS815118/36T-225/200/180/166/150/133
Sleep Mode Timing Diagram
CK
tH
tS
tKC
tKL
tKH
ADSP
ADSC
ZZ
tZZH
tZZS
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings) but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface
standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Unlike
JTAG implementations that have been common among SRAM vendors for the last several years, this implementation does offer a
form of EXTEST, known as Clock Assisted EXTEST, reducing or eliminating the “hand coding” that has been required to
overcome the test program compiler errors caused by previous non-compliant implementations. The JTAG Port interfaces with
conventional 2.5 V CMOS logic level signaling.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
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Preliminary
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JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
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Preliminary
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JTAG TAP Block Diagram
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1 0
·
· · ·
Boundary Scan Register
n
2
1
0
· · · · · · · · ·
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
ID Code
I/O
Not Used
Configuration
1
1
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
10 9 8 7 6 5 4 3 2 1
0
x36
x18
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
1
1
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1
compliant because some of the mandatory instructions are uniquely implemented. The TAP on this device may be used to monitor
all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This
device will not perform INTEST or the preload portion of the SAMPLE / PRELOAD command.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
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When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring con-
tents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm
the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data cap-
ture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O
ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the
TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-
DR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This
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Preliminary
GS815118/36T-225/200/180/166/150/133
functionality is not Standard 1149.1 compliant.
EXTEST (EXTEST-A)
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in
the device, is loaded with all logic 0s. The EXTEST implementation in this device does not, without further user intervention, actually move
the contents of the scan chain onto the RAM’s output pins. Therefore, this device is not strictly 1149.1-compliant. Nevertheless, this RAM’s
TAP does respond to an all 0s instruction, EXTEST (000), by overriding the RAM’s control inputs and activating the Data I/O output drivers.
The RAM’s main clock (CK) may then be used to transfer Boundary Scan Register contents associated with each I/O from the scan register
to the RAM’s output drivers and onto the I/O pins. A single CK transition is sufficient to transfer the data, but more transitions will do no
harm.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-
ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
EXTEST-A
IDCODE
Code
000
Description
Notes
Places the Boundary Scan Register between TDI and TDO.
This RAM implements an Clock Assisted EXTEST function. *Not 1149.1
Compliant *
1
1, 2
1
001
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
010
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
011
100
1
1
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1
Compliant *
SAMPLE/
PRELOAD
GSI
RFU
101
110
111
GSI private instruction.
1
1
1
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
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JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
VIHT
Min.
Max.
Unit Notes
0.7 * VDD
VDD +0.3
Test Port Input High Voltage
V
V
1, 2
1, 2
3
VILT
0.3 * VDD
Test Port Input Low Voltage
–0.3
–300
–1
IINTH
IINTL
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
1
1
uA
uA
uA
V
4
IOLT
–1
1
5
VOHT
VOLT
1.7
—
0.4
6, 7
6, 8
—
V
Note:
1. This device features input buffers compatible with 2.5 V I/O drivers.
2. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tTKC.
3. VDD ³ VIN ³ VIL
4. 0 V £ VIN £ VIL
5. Output Disable, VOUT = 0 to VDD
6. The TDO output driver is served by the VDD supply.
7. IOH = –4 mA
8. IOL = + 4 mA
JTAG Port AC Test Conditions
Parameter
Input high level
Conditions
2.3 V
JTAG Port AC Test Load
DQ
Input low level
0.2 V
30pF*
Input slew rate
1 V/ns
50W
Input reference level
Output reference level
1.25 V
VT = 1.25 V
1.25 V
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
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JTAG Port Timing Diagram
tTKL
tTKH
tTKC
TCK
tTS tTH
TMS
TDI
TDO
tTKQ
JTAG Port AC Electrical Characteristics
Parameter
Symbol Min Max Unit
TCK Cycle Time
tTKC
tTKQ
tTKH
tTKL
tTS
20
—
10
10
5
—
10
—
—
—
—
ns
ns
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
tTH
5
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GS816118/36T TQFP Boundary Scan Register
Order
1
x36
PH = 0
x18
Pin
n/a
n/a
44
45
46
47
48
49
50
Order
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
x36
ADSC
x18
Pin
85
86
87
88
89
n/a
n/a
92
93
94
Order
66
x36
x18
Pin
DQD5
DQD6
DQD7
DQD8
DQB9
24
2
PH = 0
A10
G
BW
67
NC = 1 25
NC = 1 28
NC = 1 29
3
68
4
A11
GW
CK
69
5
A12
70
x36 = DQD9 NC = 1 30
6
A13
PH = 0
PH = 0
A17
71
LBO
A5
31
32
33
34
35
36
37
7
A14
72
8
A15
73
A4
9
A16
BA
74
A3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
30
31
32
33
x36 = DQA9 NC = 1 51
BB
75
A2
DQA8
DQA7
DQA6
DQA5
DQA4
DQA3
DQA2
DQA1
NC = 1 52
NC = 1 53
NC = 1 56
NC = 1 57
BC
NC = 1 95
76
A1
BD
NC = 1 96
77
A0
A18
E1
A7
A6
97
98
78
PH = 0
n/a
BPR 1999.05.14
DQA1
DQA2
DQA3
DQA4
58
59
62
63
64
66
68
69
72
73
74
99
100
x36 = DQC9 NC = 1
1
2
DQC8
DQC7
DQC6
DQC5
DQC4
DQC3
DQC2
DQC1
NC = 1
NC = 1
NC = 1
NC = 1
DQB1
ZZ
3
QE
6
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQA5
DQA6
DQA7
DQA8
DQA9
7
8
DQB2
9
DQB3
12
13
14
16
n/a
18
19
22
23
DQB4
NC = 1 75
FT
NC = 1 78
DP
NC = 1 79
PH = 1
A9
A8
81
82
83
84
DQD1
DQB5
DQB6
DQB7
DQB8
DQD2
DQD3
DQD4
ADV
ADSP
Note:
1. The Boundary Scan Register contains a number of registers that are not connected to any pin. They default to the value shown at reset.
2. Registers are listed in exit order (i.e. Location 1 is the first out of the TDO pin.
3. NC = No Connect, NA = Not Active, PH = Place Holder (No associated pin)
Rev: 1.01 11/2000
29/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
TQFP Package Drawing
q
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
0.75
L1
Y
A1
A2
E1
E
0.10
q
0°
7°
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.01 11/2000
30/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
1M x 18
1M x 18
GS815118 T-225
GS815118 T-200
GS815118 T-180
GS815118 T-166
GS815118 T-150
GS815118 T-133
GS815136T-225
GS815136T-200
GS815136T-180
GS815136T-166
GS815136T-150
GS815136T-133
GS815118 T-225I
GS815118 T-200I
GS815118 T-180I
GS815118 T-166I
GS815118 T-150I
GS815118 T-133I
GS815136T-225I
GS815136T-200I
GS815136T-180I
GS815136T-166I
GS815136T-150I
GS815136T-133I
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
ByteSafe Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
225/7
200/7.5
180/8
C
C
C
C
C
C
C
C
C
C
C
C
I
1M x 18
1M x 18
166/8.5
150/10
133/11
225/7
1M x 18
1M x 18
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
1M x 18
200/7.5
180/8
166/8.5
150/10
133/11
225/7
Not Available
Not Available
1M x 18
200/7.5
180/8
I
1M x 18
I
1M x 18
166/8.5
150/10
133/11
225/7
I
1M x 18
I
1M x 18
I
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
Notes:
I
Not Available
Not Available
200/7.5
180/8
I
I
166/8.5
150/10
133/11
I
I
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS815118T-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.01 11/2000
31/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS815118/36T-225/200/180/166/150/133
16M Sync SRAM Data Sheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
815118_r1
• Update Features list on page 1
815118_r1; 815118_r1_01
Content
• Completely change table on page 1
• Update Mode Pin Functions table on page 7
Rev: 1.01 11/2000
32/32
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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