GS816036T-250I [GSI]
1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs; 1M ×18 ， 512K ×32 ， 512K ×36 18MB同步突发静态存储器
| 型号： | GS816036T-250I |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| 文件： | 总28页 (文件大小：811K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS816018/32/36T-250/225/200/166/150/133
250 MHz–133 MHz
100-Pin TQFP
Commercial Temp
Industrial Temp
1M x 18, 512K x 32, 512K x 36
2.5 V or 3.3 V V
DD
18Mb Sync Burst SRAMs
2.5 V or 3.3 V I/O
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
-250 -225 -200 -166 -150 -133 Unit
Byte Write and Global Write
Pipeline
3-1-1-1
tKQ
tCycle
2.5 2.7 3.0 3.4 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Curr (x18) 280 255 230 200 185 165 mA
Curr (x32/x36) 330 300 270 230 215 190 mA
3.3 V
2.5 V
Curr (x18) 275 250 230 195 180 165 mA
Curr (x32/x36) 320 295 265 225 210 185 mA
Sleep Mode
Flow
Through
2-1-1-1
tKQ
tCycle
5.5 6.0 6.5 7.0 7.5 8.5 ns
5.5 6.0 6.5 7.0 7.5 8.5 ns
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Curr (x18) 175 165 160 150 145 135 mA
Curr (x32/x36) 200 190 180 170 165 150 mA
3.3 V
2.5 V
Core and Interface Voltages
The GS816018/32/36T operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
Curr (x18) 175 165 160 150 145 135 mA
Curr (x32/x36) 200 190 180 170 165 150 mA
from the internal circuits and are 3.3 V and 2.5 V compatible.
Functional Description
Applications
The GS816018/32/36T is an 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
Rev: 2.12 3/2002
1/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
GS816018 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A19
NC
NC
VDDQ
VSS
NC
DQA9
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
VDDQ
4
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
5
6
7
8
9
1M x 18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Top View
FT
VDD
NC
VSS
DQB5
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.12 3/2002
2/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
GS816032 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
DQC8
DQC7
VDDQ
2
3
4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
5
6
7
8
9
512K x 32
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
FT
VDD
NC
VSS
DQD1
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.12 3/2002
3/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
GS816036 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQB9
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
DQC9
DQC8
DQC7
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
VDDQ
4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
5
6
7
8
9
512K x 36
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
FT
VDD
NC
VSS
DQD1
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
DQA9
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
DQD9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.12 3/2002
4/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
TQFP Pin Description
Pin Location
Symbol
Type
Description
37, 36
A0, A1
I
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,
47, 48, 49, 50, 43, 42
A2–A18
I
I
Address Inputs
80
A19
Address Inputs (x18 versions)
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8
I/O
I/O
Data Input and Output pins (x32, x36 Version)
18, 19, 22, 23, 24, 25, 28, 29
DQA9, DQB9,
DQC9, DQD9
51, 80, 1, 30
Data Input and Output pins (x36 Version)
No Connect (x32 Version)
51, 80, 1, 30
NC
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQA1–DQA9
DQB1–DQB9
I/O
Data Input and Output pins (x18 Version)
51, 52, 53, 56, 57
75, 78, 79, 95, 96,
1, 2, 3, 6, 7,
NC
—
No Connect (x18 Version)
25, 28, 29, 30
87
BW
I
I
Byte Write—Writes all enabled bytes; active low
93, 94
BA, BB
Byte Write Enable for DQA, DQB Data I/Os; active low
Byte Write Enable for DQC, DQD Data I/Os; active low
(x32, x36 Version)
95, 96
BC, BD
I
89
CK
I
I
I
I
I
I
I
I
I
I
I
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
88
GW
98, 92
E1, E3
97
E2
Chip Enable; active high
86
G
ADV
Output Enable; active low
83
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
84, 85
ADSP, ADSC
ZZ
64
14
31
FT
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
LBO
VDD
15, 41, 65, 91
VSS
VDDQ
NC
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
16, 38, 39, 66
I
I
I/O and Core Ground
Output driver power supply
No Connect
—
Rev: 2.12 3/2002
5/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
GS816018/32/36 Block Diagram
Register
A0–An
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
36
36
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E2
E3
D
Q
Register
D
Q
FT
G
1
Power Down
Control
DQx1–DQx9
ZZ
Note: Only x36 version shown for simplicity.
Rev: 2.12 3/2002
6/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Mode Pin Functions
Mode Name
Pin
Name
State
Function
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Burst Order Control
LBO
H
L
Output Register Control
FT
H or NC
L or NC
H
Active
Power Down Control
Note:
ZZ
Standby, IDD = ISB
There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 2.12 3/2002
7/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
BA
X
BB
X
BC
X
BD
X
Notes
1
Read
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 2.12 3/2002
8/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Synchronous Truth Table
Operation
State
Address
Used
2
3
4
Diagram
E1
ADSP ADSC ADV
E
W
DQ
5
Key
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
None
None
X
X
H
L
X
X
L
L
X
L
X
X
X
X
X
X
L
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
F
F
T
T
T
X
X
X
X
X
X
X
X
High-Z
None
X
L
L
H
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
R
L
L
X
H
X
H
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 2.12 3/2002
9/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CR
CW
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW)
control inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 2.12 3/2002
10/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 2.12 3/2002
11/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS
)
Symbol
Description
Voltage on VDD Pins
Value
Unit
V
VDD
VDDQ
VCK
–0.5 to 4.6
Voltage in VDDQ Pins
–0.5 to 4.6
V
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 6
V
VI/O
–0.5 to VDDQ +0.5 (£ 4.6 V max.)
V
VIN
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
–0.5 to VDD +0.5 (£ 4.6 V max.)
V
IIN
+/–20
+/–20
mA
mA
W
IOUT
PD
1.5
oC
oC
TSTG
TBIAS
Note:
–55 to 125
–55 to 125
Temperature Under Bias
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Condi-
tions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Rev: 2.12 3/2002
12/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Power Supply Voltage Ranges
Parameter
Symbol
VDD3
Min.
Typ.
Max.
Unit
Notes
3.3 V Supply Voltage
2.5 V Supply Voltage
3.0
2.3
3.0
2.3
3.3
2.5
3.3
2.5
3.6
2.7
3.6
V
V
V
V
VDD2
3.3 V VDDQ I/O Supply Voltage
2.5 V VDDQ I/O Supply Voltage
Notes:
VDDQ3
VDDQ2
2.7
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
V
Range Logic Levels
DDQ3
Parameter
Symbol
VIH
Min.
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VDD Input Low Voltage
VDDQ I/O Input High Voltage
VDDQ I/O Input Low Voltage
VDD + 0.3
2.0
–0.3
2.0
—
—
—
—
V
V
V
V
1
VIL
0.8
1
VIHQ
VILQ
VDDQ + 0.3
1,3
1,3
–0.3
0.8
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
V
Range Logic Levels
DDQ2
Parameter
Symbol
VIH
Min.
Typ.
Max.
VDD + 0.3
0.3*VDD
Unit
Notes
VDD Input High Voltage
VDD Input Low Voltage
VDDQ I/O Input High Voltage
VDDQ I/O Input Low Voltage
0.6*VDD
—
—
—
—
V
V
V
V
1
VIL
–0.3
1
VIHQ
VILQ
0.6*VDD
VDDQ + 0.3
0.3*VDD
1,3
1,3
–0.3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Rev: 2.12 3/2002
13/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Recommended Operating Temperatures
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
TA
TA
Ambient Temperature (Commercial Range Versions)
0
25
25
70
85
°C
°C
2
2
Ambient Temperature (Industrial Range Versions)
Note:
–40
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 2.0 V
VSS
50%
VDD
50%
V
SS – 2.0 V
20% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
Typ.
Max.
Unit
Input Capacitance
4
6
5
7
pF
pF
CI/O
VOUT = 0 V
Input/Output Capacitance
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Layer Board
Symbol
RQJA
Max
Unit
Notes
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
single
four
—
40
24
9
°C/W
°C/W
°C/W
1,2
1,2
3
RQJA
RQJC
Junction to Case (TOP)
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 2.12 3/2002
14/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
AC Test Conditions
Parameter
Conditions
VDD – 0.2 V
Input high level
Input low level
0.2 V
1 V/ns
VDD/2
Input slew rate
Input reference level
VDDQ/2
Output reference level
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig.
1 unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
30pF*
50W
VDDQ/2
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
VDD ³ VIN ³ VIH
0 V £ VIN £ VIH
–1 uA
–1 uA
1 uA
IIN1
ZZ Input Current
FT Input Current
100 uA
VDD ³ VIN ³ VIL
0 V £ VIN £ VIL
–100 uA
–1 uA
1 uA
1 uA
IIN2
IOL
Output Disable, VOUT = 0 to VDD
IOH = –8 mA, VDDQ = 2.375 V
IOH = –8 mA, VDDQ = 3.135 V
IOL = 8 mA
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
–1 uA
1.7 V
2.4 V
—
1 uA
—
VOH2
VOH3
VOL
—
0.4 V
Rev: 2.12 3/2002
15/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Rev: 2.12 3/2002
16/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
AC Electrical Characteristics
-250
-225
-200
-166
-150
-133
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKC
tKQ
4.0
—
—
2.5
—
—
—
—
—
5.5
—
—
—
—
—
—
4.4
—
—
2.7
—
—
—
—
—
6.0
—
—
—
—
—
—
5.0
—
—
3.0
—
—
—
—
—
6.5
—
—
—
—
—
—
6.0
—
—
3.4
—
—
—
—
—
7.0
—
—
—
—
—
—
6.7
—
—
3.8
—
—
—
—
—
7.5
—
—
—
—
—
—
7.5
—
1.5
1.5
1.5
0.5
8.5
—
3.0
3.0
1.5
0.5
1.7
2
—
4.0
—
—
—
—
—
8.5
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
1.5
1.5
1.2
0.2
5.5
—
1.5
1.5
1.3
0.3
6.0
—
1.5
1.5
1.4
0.4
6.5
—
1.5
1.5
1.5
0.5
7.0
—
1.5
1.5
1.5
0.5
7.5
—
Pipeline
tLZ1
tS
Hold time
tH
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKC
tKQ
tKQX
3.0
3.0
1.5
0.5
1.3
1.5
3.0
3.0
1.5
0.5
1.3
1.5
3.0
3.0
1.5
0.5
1.3
1.5
3.0
3.0
1.5
0.5
1.3
1.5
3.0
3.0
1.5
0.5
1.5
1.7
Flow
Through
tLZ1
tS
Hold time
tH
Clock HIGH Time
Clock LOW Time
tKH
tKL
Clock to Output in
High-Z
tHZ1
1.5
2.3
1.5
2.5
1.5
3.0
1.5
3.0 1.5 3.0 1.5 3.0
ns
G to Output Valid
G to output in Low-Z
G to output in High-Z
ZZ setup time
tOE
—
0
2.3
—
2.3
—
—
—
—
0
2.5
—
2.5
—
—
—
—
0
3.2
—
3.0
—
—
—
—
0
3.5
—
3.0
—
—
—
—
0
3.8
—
3.0
—
—
—
—
0
4.0
—
3.0
—
—
—
ns
ns
ns
ns
ns
ns
tOLZ1
tOHZ1
tZZS2
—
5
—
5
—
5
—
5
—
5
—
5
tZZH2
tZZR
ZZ hold time
1
1
1
1
1
1
ZZ recovery
20
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 2.12 3/2002
17/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Write Cycle Timing
Single Write
tS tH
Burst Write
Deselected
Write
CK
ADSP is blocked by E inactive
tKC
tKL
tKH
ADSP
tH
tH
tS
ADSC initiated write
ADSC
tS
ADV
ADV must be inactive for ADSP Write
tH
tS
WR2
WR3
WR1
A0–An
tS tH
GW
BW
tH
tS
tS
tH
WR3
WR1
WR2
BA–BD
E1
tS
tS
tH
tH
E1 masks ADSP
Deselected with E2
E2
tS tH
E2 and E3 only sampled with ADSP or ADSC
E3
G
tS
Write specified byte for 2A and all bytes for 2B, 2C& 2D
tH
Hi-Z
D2C
D2D
D3A
DQA–DQD
D1A
D2A
D2B
Rev: 2.12 3/2002
18/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tS
tKH
tH
ADSP is blocked by E inactive
ADSC initiated read
tKC
ADSP
ADSC
ADV
tS tH
tH
tS
Suspend Burst
Suspend Burst
tS
tH
RD1
RD2
RD3
A0–An
GW
tS
tS
tH
tH
BW
BA–BB
E1
tH
tS
E1 masks ADSP
tS tH
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
tS
tH
E3
G
tOHZ
tOE
tKQX
tKQX
Q3A
tOLZ
Q2B
Q2c
Q1A
Q2A
Q2D
DQA–DQD
Hi-Z
tLZ
tHZ
tKQ
Rev: 2.12 3/2002
19/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Flow Through Read-Write Cycle Timing
Single Write
Burst Read
Single Read
CK
tS tH
tKC
ADSP is blocked by E inactive
tKH tKL
ADSP
ADSC
tS tH
ADSC initiated read
tS tH
ADV
tS
tH
RD2
WR1
RD1
A0–An
tS
tS
tH
GW
tS
tH
BW
tS
tH
BA–BD
WR1
tS
tS
tS
tH
E1 masks ADSP
E1
tH
tH
E2 and E3 only sampled with ADSP and ADSC
E2
E3
Deselected with E3
tOHZ
tOE
G
tS
tH
tKQ
Hi-Z
DQA–DQD
Q1A
D1A
Q2A
Q2A
Q2B
Q2c
Q2D
Burst wrap around to it’s initial state
Rev: 2.12 3/2002
20/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Pipelined SCD Read Cycle Timing
Single Read
Burst Read
CK
tKL
tKH
tH
tH
tS
tKC
ADSP is blocked by E inactive
ADSP
ADSC
tS
ADSC initiated read
tS tH
Suspend Burst
ADV
tH
tS
RD2
RD3
RD1
A0–An
GW
tS
tS
tH
tH
BW
BWA–BWD
E1
tH
tS
E1 masks ADSP
tS tH
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
E3
tS
tH
tOE
G
tOHZ
tKQX
tKQX
Q3A
tOLZ
tLZ
Hi-Z
DQA–DQD
Q1A
Q2A
Q2B
Q2D
Q2c
tHZ
tKQ
Rev: 2.12 3/2002
21/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Pipelined SCD Read-Write Cycle Timing
Single Write
Single Read
Burst Read
tKL
CK
tH
tS
tKH
tKC
ADSP is blocked by E inactive
ADSC initiated read
ADSP
ADSC
tS tH
tS tH
ADV
tS
tH
RD2
RD1
WR1
A0–An
tS
tS
tH
GW
tH
BW
tH
tS
WR1
BWA–BWD
tS
tS
tS
tH
tH
tH
E1 masks ADSP
E1
E2 and E3 only sampled with ADSP and ADSC
E2
E3
Deselected with E3
tOE
tOHZ
G
tS
tH
tKQ
Hi-Z
Q1A
D1A
Q2A
Q2Bb
Q2c
DQA–DQD
Q2D
Rev: 2.12 3/2002
22/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
CK
tH
tS
tKC
tKL
tKH
ADSP
ADSC
ZZ
tZZH
tZZS
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.
Rev: 2.12 3/2002
23/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
TQFP Package Drawing
q
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
0.10
7°
q
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 2.12 3/2002
24/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
1M x 18
1M x 18
GS816018T-250
GS816018T-225
GS816018T-200
GS816018T-166
GS816018T-150
GS816018T-133
GS816032T-250
GS816032T-225
GS816032T-200
GS816032T-166
GS816032T-150
GS816032T-133
GS816036T-250
GS816036T-225
GS816036T-200
GS816036T-166
GS816036T-150
GS816036T-133
GS816018T-250I
GS816018T-225I
GS816018T-200I
GS816018T-166I
GS816018T-150I
GS816018T-133I
GS816032T-250I
GS816032T-225I
GS816032T-200I
GS816032T-166I
GS816032T-150I
GS816032T-133I
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
250/5.5
225/6
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
1M x 18
200/6.5
166/7
1M x 18
1M x 18
150/7.5
133/8.5
250/5.5
225/6
1M x 18
512K x 32
512K x 32
512K x 32
512K x 32
512K x 32
512K x 32
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
1M x 18
200/6.5
166/7
150/7.5
133/8.5
250/5.5
225/6
200/6.5
166/7
150/7.5
133/8.5
250/5.5
225/6
Not Available
Not Available
Not Available
1M x 18
I
1M x 18
200/6.5
166/7
I
1M x 18
I
1M x 18
150/7.5
133/8.5
250/5.5
225/6
I
1M x 18
I
512K x 32
512K x 32
512K x 32
512K x 32
512K x 32
512K x 32
Notes:
I
Not Available
Not Available
Not Available
I
200/6.5
166/7
I
I
150/7.5
133/8.5
I
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018T-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 2.12 3/2002
25/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
Notes:
GS816036T-250I
GS816036T-225I
GS816036T-200I
GS816036T-166I
GS816036T-150I
GS816036T-133I
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
250/5.5
225/6
I
I
I
I
I
I
Not Available
Not Available
Not Available
200/6.5
166/7
150/7.5
133/8.5
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018T-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 2.12 3/2002
26/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Converted from 0.25u 3.3V process to 0.18u 2.5V process.
Master File Rev B
• Added x72 Pinout.
GS816018T-150IT 1.00 9/
1999A;GS816018T-150IT
2.00 1/1999B
Content
Format
• Added GSI Logo.
• Changed Flow-Through Read-Write cycle Timing Diagram for
accuracy
GS816018T- 2.00 11/
1999B;GS816018T 2.01 1/
2000C
• Changed pin description in TQFP to match order of pins in
pinout.
GS816018T 2.01 1/
2000C;GS816018 T 2.02 1/
2000D
• Front page; Features - changed 2.5V I/O supply to 2.5V
or3.3V I/O supply; Core and Interface voltages - Changed
paragraph to include information for 3.3V;Completeness
• Absolute Maximum Ratings; Changed VDDQ - Value: From: -
.05 to VDD : to : -.05 to 3.6; Completeness.
• Recommended Operating Conditions;Changed: I/O Supply
Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from
VDD +0.3 to 3.6; Same page - took out Note 1;Completeness
• Electrical Characteristics - Added second Output High Voltage
line to table; completeness.
GS18/362.0 1/2000DGS18/
362.03 2/2000E
• Note: There was not a Rev 2.02 for the 8160Z or the 8161Z.
• Input High Voltage (p. 11) changed to 0.7* VDD
• Input Low Voltage (p.11) changed to 0.3* VDD
GS18/362.03 2/2000E;
816018_r2_04
Content
Content
• Changed the value of ZZ recovery in the AC Electrical
Characteristics table on page 15 from 20 ns to 100 ns
816018_r2_04;
816018_r2_05
• Added 225 MHz speed bin
• Updated Pg. 1 table, AC Characteristics table, and Operating
Currents table to match 815xxx
• Updated format to comply with Technical Publications
standards
816018_r2_05;
816018_r2_06
Content/Format
• Updated Capitance table—removed Input row and changed
Output row to I/O
816018_r2_06;
816018_r2_07
Content
Content
• Updated Features list on page 1
• Completely reworked table on page 1
• Updated Mode Pin Functions tableon page 7
816018_r2_07;
816018_r2_08
• Added 3.3 V references to entire document
• Updated Operating Conditions table
816018_r2_08;
816018_r2_09
• Added Pin 56 to Pin Description table
• Updated Operating Currents table and added note
• Updated Application Tips paragraph
Content
• Updated table on page 1; added power numbers
Rev: 2.12 3/2002
27/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Updated Operating Currents table
• Updated table on page 1; updated power numbers
• Updated Recommended Operating Conditions table (added
VDDQ references)
816018_r2_09;
816018_r2_10
Content
Content
• Updated table on page 1
• Created recommended operating conditions tables on pages
12 and 13
• Updated AC Electrical Characteristics table
• Added Sleep mode description on page 23
• Updated Ordering Information for 225 MHz part (changed
from 7ns to 6.5 ns)
816018_r2_10;
816018_r2_11
• Added 250 MHz speed bin
• Deleted 180 MHz speed bin
• Updated AC Characteristics table
• Updated FT power numbers
• Updated Mb references from 16Mb to 18Mb
• Updated AC Test Conditions table and removed Output Load
2 diagram
816018_r2_11;
816018_r2_12
Content
Rev: 2.12 3/2002
28/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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