GS8160E32GT-166IT_技术文档

GS8160E18/32/36T-250/225/200/166/150/133

250 MHz–133 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

1M x 18, 512K x 36

18Mb Sync Burst SRAMs

2.5 V or 3.3 V V

DD

2.5 V or 3.3 V I/O

with the Linear Burst Order (LBO) input. The Burst function need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

Flow Through/Pipeline Reads

• Dual Cycle Deselect (DCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

The function of the Data Output register can be controlled by the user

via the FT mode pin (Pin 14). Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the Data

Output Register. Holding FT high places the RAM in Pipeline mode,

activating the rising-edge-triggered Data Output Register.

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

DCD Pipelined Reads

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

The GS8160E18/32/36T is a DCD (Dual Cycle Deselect) pipelined

synchronous SRAM. SCD (Single Cycle Deselect) versions are also

available. DCD SRAMs pipeline disable commands to the same

degree as read commands. DCD RAMs hold the deselect command

for one full cycle and then begin turning off their outputs just after the

second rising edge of clock.

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

Functional Description

Applications

Byte Write and Global Write

The GS8160E18/32/36T is an 18,874,368-bit (16,777,216-bit for x32

version) high performance synchronous SRAM with a 2-bit burst

address counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications, ranging

from DSP main store to networking chip set support.

Byte write operation is performed by using Byte Write enable (BW)

input combined with one or more individual byte write signals (Bx).

In addition, Global Write (GW) is available for writing all bytes at one

time, regardless of the Byte Write control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of

the ZZ signal, or by stopping the clock (CK). Memory data is retained

during Sleep mode.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW)

are synchronous and are controlled by a positive-edge-triggered clock

input (CK). Output enable (G) and power down control (ZZ) are

asynchronous inputs. Burst cycles can be initiated with either ADSP

or ADSC inputs. In Burst mode, subsequent burst addresses are

generated internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or interleave order

Core and Interface Voltages

The GS8160E18/32/36T operates on a 2.5 V or 3.3 V power supply.

All input are 3.3 V and 2.5 V compatible. Separate output power

(V_DDQ) pins are used to decouple output noise from the internal

circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

t_KQ

2.5

4.0

2.7

4.4

3.0

5.0

3.4

6.0

3.8

6.7

4.0

7.5

ns

tCycle

Curr (x18)

280

255

300

230

270

200

230

185 165

215 190

mA

3.3 V

2.5 V

Curr (x32/x36) 330

Curr (x18) 275

Curr (x32/x36) 320

250

295

230

265

195

225

180 165

210 185

mA

Flow

Through

2-1-1-1

t_KQ

5.5

6.0

6.5

7.0

7.5

8.5

ns

tCycle

Curr (x18)

Curr (x32/x36) 200

175

165

190

160

180

150

170

145 135

165 150

mA

3.3 V

2.5 V

Curr (x18) 175

Curr (x32/x36) 200

165

190

160

180

150

170

145 135

165 150

mA

Rev: 2.13 11/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

GS8160E18 100-Pin TQFP Pinout (Package T)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

A

NC

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

V

NC

V

DDQ

SS

V

NC

DQPA

DQA

V

SS

NC

DQB

1M x 18

Top View

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

DDQ

SS

V

DDQ

DQA

DQB

V

FT

SS

NC

V

DD

V

NC

DD

ZZ

V

SS

DQ^A

DQA

DQB

V

DQA

NC

V

NC

DDQ

SS

V

SS

DQB

DQPB

NC

V

SS

DDQ

SS

V

DDQ

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Rev: 2.13 11/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

GS8160E32 100-Pin TQFP Pinout (Package T)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

NC

DQB

DQ^B

V

NC

DQC

DQ^C

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V

DDQ

V

SS

DQB

DQC

DQ^C

DQC

512K x 32

Top View

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

DDQ

SS

V

DDQ

DQB

DQC

V

SS

FT

NC

V

DD

V

ZZ

NC

DD

V

SS

DQ^A

DQA

V

DQD

DDQ

V

DDQ

SS

V

SS

DQA

DQD

V

SS

DDQ

SS

V

DDQ

DQA

NC

DQD

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Rev: 2.13 11/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

GS8160E36 100-Pin TQFP Pinout (Package T)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

DQPB

DQB

DQPC

DQC

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQB

DQC

V

DDQ

SS

V

SS

DQB

DQC

512K x 36

Top View

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

DDQ

SS

V

DDQ

DQB

DQC

V

SS

FT

NC

V

DD

V

ZZ

NC

DD

V

SS

DQ^A

DQA

DQD

DDQ

V

DDQ

SS

V

SS

DQA

DQD

V

SS

DDQ

SS

V

DDQ

DQA

DQD

DQA

DQD

DQPA

DQPD

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Rev: 2.13 11/2004

4/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

TQFP Pin Description

Symbol

A0, A1

A

Type

Description

Address field LSBs and Address Counter preset Inputs

Address Input

I

DQ^A

DQB

DQC

DQD

I/O

Data Input and Output pins

NC

—

No Connect

Byte Write—Writes all enabled bytes; active low

Byte Write Enable for DQA, DQB Data I/Os; active low

Clock Input Signal; active high

BW

I

B^A, BB, BC, BD

CK

GW

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

E¹

E²

Chip Enable; active high

E³

Chip Enable; active low

G

ADV

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

ADSP, ADSC

ZZ

LBO

Linear Burst Order mode; active low

Core power supply

V

DD

V

I

I/O and Core Ground

SS

V

Output driver power supply

DDQ

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

GS8160E18/32/36 Block Diagram

^RegisteQ^r

A0–An

D

A0

A1

A0

A1

D0

D1

Counter

Load

Q0

Q1

A

LBO

ADV

CK

Memory

Array

ADSC

ADSP

Q

D

Register

GW

BW

BA

D

Q

Register

36

D

Q

BB

BC

BD

4

Register

D

Q

Register

D

Q

Register

D

Q

Register

E1

E2

E3

D

Q

Register

D

Q

FT

G

0

Power Down

Control

DQx1–DQx9

ZZ

Note: Only x36 version shown for simplicity.

Rev: 2.13 11/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

Mode Pin Functions

Mode Name

Pin Name

State

Function

Linear Burst

Interleaved Burst

Flow Through

Pipeline

L

Burst Order Control

Output Register Control

Power Down Control

LBO

H

L

FT

ZZ

H or NC

L or NC

H

Active

Standby, I = I

DD SB

Note:

There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in

the default states as specified in the above tables.

Burst Counter Sequences

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

1st address

2nd address

3rd address

4th address

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Note:

The burst counter wraps to initial state on the 5th clock.

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Rev: 2.13 11/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

Byte Write Truth Table

Function

Read

GW

BW

H

L

BA

X

BB

X

BC

X

BD

X

Notes

1

H

L

Read

H

L

H

L

H

L

H

L

1

Write byte a

Write byte b

Write byte c

Write byte d

Write all bytes

L

2, 3

L

H

L

2, 3

L

H

L

2, 3, 4

L

H

L

X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x32 and x36 versions.

Rev: 2.13 11/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

Synchronous Truth Table

Operation

State

Address

Used

2

3

4

Diagram

E1

ADSP ADSC ADV

E

W

DQ

5

Key

Deselect Cycle, Power Down

Read Cycle, Begin Burst

None

X

H

L

X

L

X

L

X

L

X

F

T

F

T

F

T

High-Z

F

T

X

High-Z

None

X

L

H

L

High-Z

External

X

L

Q

D

Q

D

Q

D

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

R

L

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

W

L

CR

CW

H

Current

H

Notes:

1. X = Don’t Care, H = High, L = Low

2. E = T (True) if E²= 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 2.13 11/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

Simplified State Diagram

X

Deselect

W

R

W

R

X

R

X

First Write

First Read

CW

CR

W

R

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW)

control inputs, and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

Rev: 2.13 11/2004

10/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

Simplified State Diagram with G

X

Deselect

W

R

W

R

X

W

R

X

First Write

First Read

CR

CW

CR

W

R

W

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 2.13 11/2004

11/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

Description

Value

Unit

V

Voltage on V Pins

–0.5 to 4.6

DD

V

Voltage in V

Pins

DDQ

–0.5 to 4.6

V

DDQ

V

–0.5 to V

+0.5 (≤ 4.6 V max.)

DDQ

Voltage on I/O Pins

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

V

I/O

V

–0.5 to V +0.5 (≤ 4.6 V max.)

V

IN

DD

I

+/–20

mA

W

IN

I

OUT

P

1.5

D

o

T

–55 to 125

C

STG

o

T

Temperature Under Bias

C

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Power Supply Voltage Ranges

Parameter

Symbol

Min.

3.0

Typ.

3.3

Max.

3.6

Unit

Notes

V

3.3 V Supply Voltage

2.5 V Supply Voltage

V

DD3

V

2.3

2.5

2.7

DD2

3.3 V V

I/O Supply Voltage

V

3.0

3.3

3.6

DDQ

DDQ3

2.5 V V

I/O Supply Voltage

V

2.3

2.5

2.7

DDQ2

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

Rev: 2.13 11/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

V

Range Logic Levels

Parameter

DDQ3

Symbol

Min.

2.0

Typ.

—

Max.

Unit

Notes

V

Input High Voltage

V

+ 0.3

DD

V

1

DD

IH

V

Input Low Voltage

V

–0.3

2.0

—

0.8

+ 0.3

1

DD

IL

V

I/O Input High Voltage

I/O Input Low Voltage

V

—

1,3

DDQ

IHQ

DDQ

V

–0.3

—

0.8

DDQ

ILQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

3.

V

(max) is voltage on V

pins plus 0.3 V.

IHQ

DDQ

V

Range Logic Levels

Parameter

DDQ2

Symbol

Min.

Typ.

—

Max.

Unit

Notes

V

Input High Voltage

V

0.6*V

V

+ 0.3

DD

V

1

DD

IH

DD

V

Input Low Voltage

V

0.3*V

DD

–0.3

—

1

DD

IL

V

I/O Input High Voltage

I/O Input Low Voltage

V

0.6*V

V

+ 0.3

DDQ

—

1,3

DDQ

IHQ

DD

V

0.3*V

DD

–0.3

—

DDQ

ILQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

3.

V

(max) is voltage on V

pins plus 0.3 V.

IHQ

DDQ

Recommended Operating Temperatures

Parameter

Symbol

Min.

0

Typ.

25

Max.

70

Unit

°C

Notes

T

Ambient Temperature (Commercial Range Versions)

2

A

T

Ambient Temperature (Industrial Range Versions)

–40

25

85

°C

A

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

Rev: 2.13 11/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

50% tKC

V

+ 2.0 V

50%

DD

V

SS

50%

V

DD

V

– 2.0 V

SS

50% tKC

V

IL

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 2.5 V)

A

DD

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

pF

C

V

= 0 V

Input Capacitance

4

6

5

7

IN

C

V

OUT

= 0 V

Input/Output Capacitance

pF

I/O

Note:

These parameters are sample tested.

AC Test Conditions

Parameter

Conditions

V

– 0.2 V

Input high level

Input low level

DD

0.2 V

1 V/ns

/2

Input slew rate

V

Input reference level

DD

V

/2

Output reference level

Output load

DDQ

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

Output Load 1

DQ

*

50Ω

30pF

V

DDQ/2

* Distributed Test Jig Capacitance

Rev: 2.13 11/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I

V = 0 to V

IN DD

–1 uA

1 uA

IL

V

≥ V ≥ V

IN

–1 uA

1 uA

100 uA

DD

IH

I

ZZ Input Current

FT Input Current

IN1

0 V ≤ V ≤ V

IN

V

≥ V ≥ V

IN

–100 uA

–1 uA

1 uA

DD

IL

I

IN2

0 V ≤ V ≤ V

IN

I

Output Disable, V

= 0 to V

DD

Output Leakage Current

Output High Voltage

Output Low Voltage

–1 uA

1.7 V

2.4 V

—

1 uA

—

OL

OUT

DDQ

V

I

= –8 mA, V

= 2.375 V

= 3.135 V

OH2

OH

V

—

OH3

V

I

= 8 mA

OL

0.4 V

OL

Rev: 2.13 11/2004

15/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

Rev: 2.13 11/2004

16/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

AC Electrical Characteristics

-250

-225

-200

-166

-150

-133

Parameter

Symbol

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Clock Cycle Time

tKC

tKQ

4.0

—

2.5

—

5.5

—

4.4

—

2.7

—

6.0

—

5.0

—

3.0

—

6.5

—

6.0

—

3.4

—

7.0

—

6.7

—

3.8

—

7.5

—

7.5

—

1.5

0.5

8.5

—

3.0

1.5

0.5

1.7

2

—

4.0

—

8.5

—

ns

Clock to Output Valid

Clock to Output Invalid

Pipeline

tKQX

1.5

1.2

0.2

5.5

—

3.0

1.5

0.5

1.3

1.5

1.3

0.3

6.0

—

3.0

1.5

0.5

1.3

1.5

1.4

0.4

6.5

—

3.0

1.5

0.5

1.3

1.5

0.5

7.0

—

3.0

1.5

0.5

1.3

1.5

0.5

7.5

—

3.0

1.5

0.5

1.5

1.7

1

Clock to Output in Low-Z

tLZ

Setup time

Hold time

tS

tH

Clock Cycle Time

Clock to Output Valid

tKC

tKQ

tKQX

Clock to Output Invalid

Clock to Output in Low-Z

Setup time

Flow

Through

1

tLZ

tS

tH

Hold time

Clock HIGH Time

Clock LOW Time

tKH

tKL

Clock to Output in

High-Z

1

1.5

2.3

1.5

2.5

1.5

3.0

1.5

3.0 1.5 3.0 1.5 3.0

ns

tHZ

G to Output Valid

G to output in Low-Z

G to output in High-Z

ZZ setup time

tOE

—

0

2.3

—

2.3

—

0

2.5

—

2.5

—

0

3.2

—

3.0

—

0

3.5

—

3.0

—

0

3.8

—

3.0

—

0

4.0

—

3.0

—

ns

1

tOLZ

1

—

5

—

5

—

5

—

5

—

5

—

5

tOHZ

2

tZZS

2

ZZ hold time

1

tZZH

ZZ recovery

tZZR

20

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Rev: 2.13 11/2004

17/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

Pipeline Mode Timing

Begin

Read A Cont

Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont

tKL

Deselect Deselect

tKH

tKC

CK

ADSP

tS

ADSC initiated read

tH

ADSC

ADV

tS

tH

A

B

C

Ao–An

GW

tS

tH

BW

tS

Ba–Bd

E1

tS

Deselected with E1

tH

E2 and E3 only sampled with ADSC

tH

E2

E3

G

tS

D(B)

tKQ

tHZ

tOE

tOHZ

Q(A)

tH

tLZ

tKQX

Hi-Z

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

DQa–DQd

Rev: 2.13 11/2004

18/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

Flow Through Mode Timing

Begin

Read A Cont

tKH

Deselect Write B

tKC

Read C Read C+1 Read C+2 Read C+3 Read C Deselect

tKL

CK

Fixed High

ADSP

tS

tH

tS

tH

ADSC initiated read

ADSC

ADV

Ao–An

GW

tH

tS

tH

tS

tH

A

B

C

tS

tH

tS

tH

BW

tH

tS

Ba–Bd

E1

tS

Deselected with E1

tH

E1 masks ADSP

tS

tH

E2 and E3 only sampled with ADSP and ADSC

E1 masks ADSP

E2

tS

tH

E3

G

tH

tS

tOE

tKQ

tKQX

tHZ

tOHZ

D(B)

tLZ

Q(A)

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

Q(C)

DQa–DQd

Rev: 2.13 11/2004

19/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of

SB

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

SB

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKH

tKC

tKL

CK

Setup

Hold

ADSP

ADSC

tZZR

tZZS

tZZH

ZZ

Application Tips

Single and Dual Cycle Deselect

SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output

drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there

will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs (like this one) do not waste

bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at

bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.

Rev: 2.13 11/2004

20/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

TQFP Package Drawing (Package T)

θ

L

c

L1

Symbol

Description

Standoff

Min. Nom. Max

A1

A2

b

0.05

1.35

0.20

0.09

0.10

1.40

0.30

—

0.15

1.45

0.40

0.20

22.1

20.1

16.1

14.1

—

Body Thickness

Lead Width

c

Lead Thickness

D

Terminal Dimension 21.9

Package Body 19.9

Terminal Dimension 15.9

22.0

20.0

16.0

14.0

0.65

0.60

1.00

e

D1

E

b

E1

e

Package Body

Lead Pitch

13.9

—

L

Foot Length

Lead Length

Coplanarity

Lead Angle

0.45

—

0.75

—

L1

Y

A1

A2

E1

E

0.10

7°

θ

0°

—

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

Rev: 2.13 11/2004

21/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

Ordering Information for GSI Synchronous Burst RAMs

2

Speed

3

1

Org

Type

Package

Status

T

Part Number

A

(MHz/ns)

1M x 18

GS8160E18T-250

GS8160E18T-225

GS8160E18T-200

GS8160E18T-166

GS8160E18T-150

GS8160E18T-133

GS8160E32T-250

GS8160E32T-225

GS8160E32T-200

GS8160E32T-166

GS8160E32T-150

GS8160E32T-133

GS8160E36T-250

GS8160E36T-225

GS8160E36T-200

GS8160E36T-166

GS8160E36T-150

GS8160E36T-133

GS8160E18T-250I

GS8160E18T-225I

GS8160E18T-200I

GS8160E18T-166I

GS8160E18T-150I

GS8160E18T-133I

GS8160E32T-250I

GS8160E32T-225I

DCD Pipeline/Flow Through

TQFP

250/5.5

225/6

C

I

1M x 18

200/6.5

166/7

1M x 18

150/7.5

133/8.5

250/5.5

225/6

1M x 18

512K x 32

512K x 36

1M x 18

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

1M x 18

I

1M x 18

200/6.5

166/7

I

1M x 18

I

1M x 18

150/7.5

133/8.5

250/5.5

225/6

I

1M x 18

I

512K x 32

I

512K x 32

I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160E18T-150IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow through mode-selectable by the user.

3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 2.13 11/2004

22/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

Ordering Information for GSI Synchronous Burst RAMs

2

Speed

3

1

Org

Type

Package

Status

T

Part Number

A

(MHz/ns)

512K x 32

512K x 36

GS8160E32T-200I

GS8160E32T-166I

GS8160E32T-150I

GS8160E32T-133I

GS8160E36T-250I

GS8160E36T-225I

GS8160E36T-200I

GS8160E36T-166I

GS8160E36T-150I

GS8160E36T-133I

DCD Pipeline/Flow Through

TQFP

200/6.5

166/7

I

150/7.5

133/8.5

250/5.5

225/6

200/6.5

166/7

150/7.5

133/8.5

512K x 36

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160E18T-150IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow through mode-selectable by the user.

3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 2.13 11/2004

23/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

18Mb Sync SRAM Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Format or Content

Page;Revisions;Reason

• Converted from 0.25u 3.3V process to 0.18u 2.5V process.

Master File Rev B

GS8160E18T-150IT 1.00 9/

1999A;GS8160E18T-150IT

2.00 1/1999B

Content

Format

• Added x72 Pinout.

• Added GSI Logo.

• Changed Flow-Through Read-Write cycle Timing Diagram for

accuracy

GS8160E18T- 2.00 11/

1999B;GS8160E18T 2.01 1/

2000C

• Changed pin description in TQFP to match order of pins in

pinout.

GS8160E18T 2.01 1/

2000C;GS8160E18 T 2.02 1/

2000D

• Front page; Features - changed 2.5V I/O supply to 2.5V

or3.3V I/O supply; Core and Interface voltages - Changed

paragraph to include information for 3.3V;Completeness

• Absolute Maximum Ratings; Changed VDDQ - Value: From: -

.05 to VDD : to : -.05 to 3.6; Completeness.

GS18/362.0 1/2000DGS18/

362.03 2/2000E

• Recommended Operating Conditions;Changed: I/O Supply

Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from

VDD +0.3 to 3.6; Same page - took out Note 1;Completeness

• Electrical Characteristics - Added second Output High Voltage

line to table; completeness.

• Note: There was not a Rev 2.02 for the 8160Z or the 8161Z.

• Changed the value of ZZ recovery in the AC Electrical

Characteristics table on page 15 from 20 ns to 100 ns

GS18/362.03 2/2000E;

8160E18_r2_04

Content

• Added 225 MHz speed bin

• Updated Pg. 1 table, AC Characteristics table, and Operating

Currents table to match 815xxx

8160E18_r2_04;

8160E18_r2_05

Content/Format

• Updated format to comply with Technical Publications

standards

• Updated Capitance table—removed Input row and changed

Output row to I/O

8160E18_r2_05;

8160E18_r2_06

Content

• Updated Features list on page 1

8160E18_r2_06;

8160E18_r2_07

• Completely reworked table on page 1

• Updated Mode Pin Functions table on page 7

• Added 3.3 V references to entire document

• Updated Operating Conditions table

8160E18_r2_07;

8160E18_r2_08

• Added Pin 56 to Pin Description table

Content

• Updated Operating Currents table and added note

• Updated Application Tips paragraph

• Updated table on page 1; added power numbers

Rev: 2.13 11/2004

24/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160E18/32/36T-250/225/200/166/150/133

18Mb Sync SRAM Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Format or Content

Page;Revisions;Reason

• Updated Operating Currents table

• Updated table on page 1; updated power numbers

8160E18_r2_08;

8160E18_r2_09

Content

• Updated Recommended Operating Conditions table (added

V

references)

DDQ

• Updated table on page 1

• Created recommended operating conditions tables on pages

12 and 13

• Updated AC Electrical Characteristics table

• Added Sleep mode description on page 23

• Updated Ordering Information for 225 MHz part (changed

from 7ns to 6.5 ns)

8160E18_r2_09;

8160E18_r2_10

• Added 250 MHz speed bin

• Deleted 180 MHz speed bin

• Updated AC Characteristics table

• Updated FT power numbers

8160E18_r2_10;

8160E18_r2_11

• Updated ZZ recovery time diagram

• Updated Mb references from 16Mb to 18Mb

• Updated AC Test Conditions table and removed Output Load

2 diagram

Content

• Removed pin locations from pin description table

• Removed Preliminary banner

8160E18_r2_11;

8160E18_r2_12

Content

• Updated format

8160E18_r2_12;

8160E18_r2_13

Format/Content

• Updated timing diagrams

Rev: 2.13 11/2004

25/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS8160E32GT-166IT
厂家：	GSI TECHNOLOGY
描述：	Cache SRAM, 512KX32, 7ns, CMOS, PQFP100, TQFP-100 静态存储器
文件：	总25页 (文件大小：647K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS8160E32GT-166IT [GSI]

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