GS8161Z18AGT-250T [GSI]
ZBT SRAM, 1MX18, 5.5ns, CMOS, PQFP100, TQFP-100;型号: | GS8161Z18AGT-250T |
厂家: | GSI TECHNOLOGY |
描述: | ZBT SRAM, 1MX18, 5.5ns, CMOS, PQFP100, TQFP-100 静态存储器 |
文件: | 总36页 (文件大小:735K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
300 MHz–150 MHz
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 100-lead TQFP and 165-bump FP-BGA
packages
TheGS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
may be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
Functional Description
The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs,
like ZBT, NtRAM, NoBL or other pipelined read/double late
write or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
is implemented with GSI's high performance CMOS
technology and is available in JEDEC-standard 100-pin TQFP
and 165-bump FP-BGA packages.
Parameter Synopsis
-300
-250
-200
-150
Unit
tKQ(x18/x36)
tCycle
2.5
3.3
2.5
4.0
3.0
5.0
3.8
6.7
ns
ns
Pipeline
3-1-1-1
335
390
280
330
230
270
185
210
mA
mA
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
5.0
5.0
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
Flow Through
2-1-1-1
230
270
210
240
185
205
170
190
mA
mA
Curr (x18)
Curr (x32/x36)
Rev: 1.03a 5/2003
1/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
GS8161Z18AT Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
V
NC
NC
2
3
V
4
DDQ
DDQ
SS
V
NC
V
5
SS
NC
NC
6
DQPA
DQA
DQA
7
8
DQB
DQB
V
9
1M x 18
Top View
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
DDQ
SS
V
DDQ
DQA
DQB
DQA5
DQB
FT
V
SS
NC
V
DD
V
NC
DD
ZZ
V
SS
DQA
DQA
DQB
DQB
V
V
V
DDQ
DDQ
SS
V
SS
DQA
DQA
NC
DQB
DQB
DQPB
NC
NC
V
V
SS
DDQ
SS
V
V
DDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.03a 5/2003
2/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
GS8161Z36AT Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPB
DQB
DQPC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
DQC
2
DQB
3
V
V
V
4
DDQ
DDQ
SS
V
5
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
6
7
8
9
512K x 36
Top View
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
DDQ
SS
V
V
DDQ
DQB
DQC
DQB
DQC
FT
V
V
SS
NC
DD
NC
SS
V
DD
ZZ
V
DQA
DQA
DQD
DQD
V
V
V
DDQ
DDQ
SS
V
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
DDQ
SS
V
V
DDQ
DQA
DQD
DQA
DQD
DQPA
DQPD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.03a 5/2003
3/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
100-Pin TQFP Pin Descriptions
Symbol
A0, A1
A
Type
In
Description
Burst Address Inputs; Preload the burst counter
Address Inputs
In
CK
In
Clock Input Signal
BA
In
Byte Write signal for data inputs DQA1–DQA9; active low
Byte Write signal for data inputs DQB1–DQB9; active low
Byte Write signal for data inputs DQC1–DQC9; active low
Byte Write signal for data inputs DQD1–DQD9; active low
Write Enable; active low
BB
In
BC
In
BD
In
W
In
E1
In
Chip Enable; active low
E2
In
Chip Enable—Active High. For self decoded depth expansion
Chip Enable—Active Low. For self decoded depth expansion
Output Enable; active low
E3
In
G
In
ADV
CKE
NC
DQA
DQB
DQC
DQD
ZZ
In
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
No Connect
In
—
I/O
I/O
I/O
I/O
In
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
FT
In
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low.
LBO
In
V
In
Core power supply
DD
V
In
In
Ground
SS
V
Output driver power supply
DDQ
Rev: 1.03a 5/2003
4/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
A
11
A
A
B
C
D
E
F
NC
A
E1
BB
NC
E3
CKE
ADV
A
A
B
C
D
E
F
NC
NC
A
E2
NC
BA
CK
W
G
A
A
NC
NC
NC
NC
NC
NC
DQA
DQA
DQA
DQA
NC
A
NC
DQPA
DQA
DQA
DQA
DQA
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DQB
DQB
DQB
DQB
MCH
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
NC
G
H
J
NC
G
H
J
FT
NC
NC
DQB
DQB
DQB
DQB
DQPB
NC
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
NC
V
V
V
V
V
V
V
V
NC
K
L
NC
NC
M
N
P
R
NC
NC
M
N
P
R
NC
V
NC
TDI
NC
A1
A0
NC
V
NC
DDQ
SS
SS
DDQ
NC
A
A
A
TDO
TCK
A
A
A
NC
LBO
NC
A
TMS
A
A
A
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03a 5/2003
5/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
165 Bump BGA—x32 Common I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
A
11
A
B
C
D
E
F
NC
A
E1
BC
BB
E3
CKE
ADV
A
NC
A
B
C
D
E
F
NC
NC
A
E2
BD
BA
CK
W
G
A
A
NC
NC
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
DQC
DQC
DQC
DQC
FT
DQC
DQC
DQC
DQC
MCH
DQD
DQD
DQD
DQD
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQB
DQB
DQB
DQB
NC
DQB
DQB
DQB
DQB
ZZ
G
H
J
G
H
J
NC
NC
DQD
DQD
DQD
DQD
NC
V
V
DQA
DQA
DQA
DQA
NC
DQA
DQA
DQA
DQA
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
V
V
V
V
V
V
V
V
K
L
M
N
P
R
M
N
P
R
V
NC
TDI
NC
A1
A0
NC
V
SS
DDQ
SS
DDQ
NC
NC
A
A
A
TDO
TCK
A
A
A
A
NC
LBO
NC
A
TMS
A
A
A
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03a 5/2003
6/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
165 Bump BGA—x36 Common I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
A
11
A
B
C
D
E
F
NC
A
E1
BC
BB
E3
CKE
ADV
A
NC
A
B
C
D
E
F
NC
DQPC
DQC
DQC
DQC
DQC
FT
A
E2
BD
BA
CK
W
G
A
A
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
DQC
DQC
DQC
DQC
MCH
DQD
DQD
DQD
DQD
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQB
DQB
DQB
DQB
NC
G
H
J
G
H
J
NC
NC
DQD
DQD
DQD
DQD
DQPD
NC
V
V
DQA
DQA
DQA
DQA
NC
DQA
DQA
DQA
DQA
DQPA
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
V
V
V
V
V
V
V
V
K
L
M
N
P
R
M
N
P
R
V
NC
TDI
NC
A1
A0
NC
V
SS
DDQ
SS
DDQ
NC
A
A
A
TDO
TCK
A
A
A
A
LBO
NC
A
TMS
A
A
A
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03a 5/2003
7/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
GS8161Z18/32/36AD 165-Bump BGA Pin Description
Symbol
A0, A1
A
Type
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I
I
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA, BB, BC, BD
I
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
NC
CK
Clock Input Signal; active high
Clock Input Buffer Enable; active low
Write Enable; active low
CKE
W
I
I
E1
I
Chip Enable; active low
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
Burst address counter advance enable; active high
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Scan Test Mode Select
ADV
ZZ
I
I
FT
I
LBO
TMS
TDI
TDO
TCK
MCH
I
I
I
Scan Test Data In
O
I
Scan Test Data Out
Scan Test Clock
—
I
Must Connect High
V
Core power supply
DD
V
I
I
I/O and Core Ground
SS
V
Output driver power supply
DDQ
Rev: 1.03a 5/2003
8/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
GS8161Z18/32/36A NBT SRAM Functional Block Diagram
n s e e S A m p s
i t r e W D r i v e r
s
Rev: 1.03a 5/2003
9/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
W
H
L
BA
X
BB
X
BC
X
BD
X
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (BA, BB, BC & BD) determine which bytes will be written. All or none may be activated. A write cycle
with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.03a 5/2003
10/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Synchronous Truth Table
Operation
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Continue
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
Write Abort, Continue Burst
Clock Edge Ignore, Stall
Sleep Mode
Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes
D
D
D
D
R
B
None
None
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
None
X
H
X
H
X
H
X
H
X
X
X
H
L
1
External
Next
L-H
L-H
Q
Q
X
L
X
L
H
L
L
1,10
2
R
B
External
Next
H
H
X
X
X
X
X
X
L-H High-Z
X
L
X
L
H
L
L-H High-Z 1,2,10
W
B
External
Next
L-H
L-H
D
D
3
X
L
X
L
H
L
X
L
L
1,3,10
2,3
W
B
None
H
H
X
X
L-H High-Z
Next
X
X
X
X
X
X
H
X
X
X
X
X
L-H High-Z 1,2,3,10
Current
None
L-H
X
-
4
High-Z
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect
cycle is executed first.
2. Dummy Read and Write abort can be considered NOP’s because the SRAM performs no operation. A Write abort occurs when the W pin
is sampled low but no Byte Write pins are active so no Write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write
cycles.
4. If CKE High occurs during a pipelined Read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a Write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.03a 5/2003
11/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Pipelined and Flow Through Read Write Control State Diagram
D
B
Deselect
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
W
R
Burst Read
Burst Write
B
B
D
D
Key
Notes:
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram
Rev: 1.03a 5/2003
12/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
R
W
B
Intermediate
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
Intermediate
D
Intermediate
W
R
High Z
B
D
Intermediate
Key
Notes:
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+2)
Intermediate State (N+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Intermediate
State
Current State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.03a 5/2003
13/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Flow Through Mode Data I/O State Diagram
R
W
B
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
D
W
R
High Z
B
D
Key
Notes:
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow through Read Write Control State Diagram
Rev: 1.03a 5/2003
14/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Pin
Mode Name
Burst Order Control
Output Register Control
Power Down Control
State
Function
Name
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
LBO
H
L
FT
ZZ
H or NC
L or NC
H
Active
Standby, I = I
DD SB
Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.03a 5/2003
15/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
CK
tZZR
ZZ
Sleep
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V or V
on pipelined parts and V on flow
DD
DDQ
SS
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Rev: 1.03a 5/2003
16/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 4.6
DD
DD
V
Voltage in V
Pins
DDQ
–0.5 to 4.6
V
DDQ
V
–0.5 to V
+0.5 (≤ 4.6 V max.)
DDQ
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
I/O
V
–0.5 to V +0.5 (≤ 4.6 V max.)
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to
Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of
time, may affect reliability of this component.
Rev: 1.03a 5/2003
17/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Power Supply Voltage Ranges
Parameter
Symbol
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
Notes
V
3.3 V Supply Voltage
2.5 V Supply Voltage
V
V
V
V
DD3
V
2.3
2.5
2.7
DD2
3.3 V V
2.5 V V
I/O Supply Voltage
I/O Supply Voltage
V
3.0
3.3
3.6
DDQ
DDQ
DDQ3
V
2.3
2.5
2.7
DDQ2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
V
Range Logic Levels
Parameter
DDQ3
Symbol
Min.
2.0
Typ.
—
Max.
Unit
Notes
V
Input High Voltage
V
V
+ 0.3
DD
V
V
V
V
1
DD
IH
V
Input Low Voltage
V
–0.3
2.0
—
0.8
+ 0.3
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
V
—
1,3
1,3
DDQ
IHQ
DDQ
V
V
–0.3
—
0.8
DDQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
3.
V
(max) is voltage on V
pins plus 0.3 V.
IHQ
DDQ
V
Range Logic Levels
Parameter
DDQ2
Symbol
Min.
Typ.
—
Max.
Unit
Notes
V
Input High Voltage
V
0.6*V
V
+ 0.3
DD
V
V
V
V
1
DD
IH
DD
V
Input Low Voltage
V
0.3*V
DD
–0.3
—
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
0.6*V
V
+ 0.3
DDQ
—
1,3
1,3
DDQ
IHQ
DD
V
V
0.3*V
DD
–0.3
—
DDQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
3.
V
(max) is voltage on V
pins plus 0.3 V.
IHQ
DDQ
Rev: 1.03a 5/2003
18/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Recommended Operating Temperatures
Parameter
Symbol
Min.
0
Typ.
25
Max.
70
Unit
°C
Notes
T
Ambient Temperature (Commercial Range Versions)
2
2
A
T
Ambient Temperature (Industrial Range Versions)
–40
25
85
°C
A
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
50%
DD
V
SS
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V
= 0 V
Input Capacitance
4
6
5
7
IN
IN
C
V
OUT
= 0 V
Input/Output Capacitance
pF
I/O
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
Max
40
Unit
Notes
1,2
R
R
R
single
four
—
°C/W
°C/W
°C/W
ΘJA
ΘJA
ΘJC
24
1,2
9
3
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.03a 5/2003
19/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
AC Test Conditions
Parameter
Conditions
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
/2
Input slew rate
V
Input reference level
DD
V
/2
Output reference level
Output load
DDQ
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
*
50Ω
30pF
V
DDQ/2
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
V
≥ V ≥ V
IN
–1 uA
–1 uA
1 uA
100 uA
DD
IH
IH
I
I
ZZ Input Current
FT Input Current
IN1
IN2
0 V ≤ V ≤ V
IN
V
≥ V ≥ V
IN
–100 uA
–1 uA
1 uA
1 uA
DD
IL
IL
0 V ≤ V ≤ V
IN
I
Output Disable, V
= 0 to V
DD
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
–1 uA
1.7 V
2.4 V
—
1 uA
—
OL
OUT
DDQ
DDQ
V
V
I
I
= –8 mA, V
= –8 mA, V
= 2.375 V
= 3.135 V
OH2
OH3
OH
OH
—
V
I
= 8 mA
OL
0.4 V
OL
Rev: 1.03a 5/2003
20/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Rev: 1.03a 5/2003
21/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
AC Electrical Characteristics
-300
-250
-200
-150
Parameter
Symbol
Unit
Min
3.3
—
Max
—
2.5
—
—
—
—
—
5.0
—
—
—
—
—
Min
4.0
—
Max
—
2.5
—
—
—
—
—
5.5
—
—
—
—
—
Min
5.0
—
Max
—
3.0
—
—
—
—
—
6.5
—
—
—
—
—
Min
6.7
—
Max
—
3.8
—
—
—
—
—
7.5
—
—
—
—
—
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
tKC
tKQ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
1.5
1.5
1.0
0.1
5.0
—
1.5
1.5
1.2
0.2
5.5
—
1.5
1.5
1.4
0.4
6.5
—
1.5
1.5
1.5
0.5
7.5
—
Pipeline
tLZ1
tS
Clock to Output in Low-Z
Setup time
Hold time
tH
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
tKC
tKQ
tKQX
3.0
3.0
1.4
0.4
1.3
3.0
3.0
1.5
0.5
1.3
3.0
3.0
1.5
0.5
1.3
3.0
3.0
1.5
0.5
1.5
Flow Through
tLZ1
tS
Clock to Output in Low-Z
Setup time
Hold time
tH
Clock HIGH Time
tKH
Clock LOW Time
tKL
1.5
1.5
—
1.5
1.5
—
1.5
1.5
—
1.7
1.5
—
ns
ns
Clock to Output in
High-Z
tHZ1
2.5
2.5
3.0
3.0
G to Output Valid
G to output in Low-Z
G to output in High-Z
ZZ setup time
tOE
—
0
2.5
—
2.5
—
—
—
—
0
2.5
—
2.5
—
—
—
—
0
3.0
—
3.0
—
—
—
—
0
3.8
—
3.8
—
—
—
ns
ns
ns
ns
ns
ns
tOLZ1
tOHZ1
tZZS2
tZZH2
tZZR
—
5
—
5
—
5
—
5
ZZ hold time
1
1
1
1
ZZ recovery
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times
as specified above.
Rev: 1.03a 5/2003
22/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Rev: 1.03a 5/2003
23/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Rev: 1.03a 5/2003
24/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DDQ
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and
0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising
edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI
and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Rev: 1.03a 5/2003
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© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1 0
·
· · ·
Boundary Scan Register
n
2 1 0
· · · · · · · · ·
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
ID Code
I/O
Not Used
Configuration
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
1
1
x36
x18
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
Rev: 1.03a 5/2003
26/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
Rev: 1.03a 5/2003
27/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The
EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when
the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the
sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in
parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the
Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-
ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 1.03a 5/2003
28/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
JTAG TAP Instruction Set Summary
Instruction
EXTEST
IDCODE
Code
000
001
Description
Notes
1
1, 2
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
010
011
TDO.
1
1
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
100
101
110
111
1
1
1
1
GSI
RFU
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.03a 5/2003
29/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
2.0
Max.
Unit Notes
V
V
V
+0.3
DD3
3.3 V Test Port Input High Voltage
3.3 V Test Port Input Low Voltage
2.5 V Test Port Input High Voltage
2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
V
V
1
1
IHJ3
V
–0.3
0.8
+0.3
ILJ3
V
0.6 * V
V
1
IHJ2
DD2
DD2
V
0.3 * V
1
–0.3
–300
–1
V
1
ILJ2
DD2
I
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
Test Port Output High Voltage
1.7
—
5, 6
5, 7
5, 8
5, 9
OHJ
V
Test Port Output Low Voltage
—
0.4
V
OLJ
V
V
– 100 mV
DDQ
Test Port Output CMOS High
—
V
OHJC
V
Test Port Output CMOS Low
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
3. 0 V ≤ V ≤ V
IN
ILJn
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V
supply.
DDQ
6.
7.
8.
9.
I
I
I
I
= –4 mA
OHJ
= + 4 mA
OLJ
= –100 uA
= +100 uA
OHJC
OHJC
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
V
– 0.2 V
Input high level
Input low level
DQ
DD
0.2 V
1 V/ns
*
50Ω
Input slew rate
30pF
V
V
/2
Input reference level
DDQ
V
/2
DDQ
/2
Output reference level
DDQ
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
Rev: 1.03a 5/2003
30/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
JTAG Port Timing Diagram
tTKL
tTS
tTKH
tTKC
TCK
tTH
TMS
TDI
TDO
tTKQ
JTAG Port AC Electrical Characteristics
Parameter
TCK Cycle Time
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
50
—
Max
—
Unit
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
20
20
10
10
—
—
ns
ns
tTH
—
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
Rev: 1.03a 5/2003
31/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
TQFP Package Drawing
θ
TQFP Package Drawing
L
c
L1
Symbol
Description
Standoff
Min.
0.05
1.35
0.20
0.09
Nom.
0.10
1.40
0.30
Max
0.15
1.45
0.40
0.20
20.1
20.1
16.1
14.1
A1
A2
Body Thickness
Lead Width
b
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
e
D1
E
b
E1
Package Body
Lead Pitch
13.9
e
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
0.75
L1
A1
A2
E1
E
Y
θ
0.10
0°
7°
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
BPR 1999.05.18
Rev: 1.03a 5/2003
32/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Package Dimensions—165-Bump FPBGA (Package D)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.50 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
I
A
B
C
D
E
F
G
H
J
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
1.0
13±0.07
B
0.20(4x)
SEATING PLANE
C
Rev: 1.03a 5/2003
33/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Ordering Information—GSI NBT Synchronous SRAM
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
1M x 18
1M x 18
1M x 18
1M x 18
1M x 18
1M x 18
1M x 18
1M x 18
GS8161Z18AT-300
GS8161Z18AT-250
GS8161Z18AT-200
GS8161Z18AT-150
GS8161Z18AD-300
GS8161Z18AD-250
GS8161Z18AD-200
GS8161Z18AD-150
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
TQFP
TQFP
300/5
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
250/5.5
200/6.5
150/7.5
300/5
TQFP
TQFP
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
TQFP
250/5.5
200/6.5
150/7.5
300/5
512K x 32 GS8161Z32AD-300
512K x 32 GS8161Z32AD-250
512K x 32 GS8161Z32AD-200
512K x 32 GS8161Z32AD-150
512K x 36 GS8161Z36AT-300
512K x 36 GS8161Z36AT-250
512K x 36 GS8161Z36AT-200
512K x 36 GS8161Z36AT-150
512K x 36 GS8161Z36AD-300
512K x 36 GS8161Z36AD-250
512K x 36 GS8161Z36AD-200
512K x 36 GS8161Z36AD-150
250/5.5
200/6.5
150/7.5
300/5
TQFP
250/5.5
200/6.5
150/7.5
300/5
TQFP
TQFP
165 BGA
165 BGA
165 BGA
165 BGA
TQFP
250/5.5
200/6.5
150/7.5
300/5
1M x 18
1M x 18
1M x 18
1M x 18
1M x 18
1M x 18
1M x 18
1M x 18
GS8161Z18AT-300I
GS8161Z18AT-250I
GS8161Z18AT-200I
GS8161Z18AT-150I
GS8161Z18AD-300I
GS8161Z18AD-250I
GS8161Z18AD-200I
GS8161Z18AD-150I
TQFP
250/5.5
200/6.5
150/7.5
300/5
I
TQFP
I
TQFP
I
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
I
250/5.5
200/6.5
150/7.5
300/5
I
I
I
512K x 32 GS8161Z32AD-300I
512K x 32 GS8161Z32AD-250I
Notes:
I
250/5.5
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8161Z18AT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.03a 5/2003
34/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
512K x 32 GS8161Z32AD-200I
512K x 32 GS8161Z32AD-150I
512K x 36 GS8161Z36AT-300I
512K x 36 GS8161Z36AT-250I
512K x 36 GS8161Z36AT-200I
512K x 36 GS8161Z36AT-150I
512K x 36 GS8161Z36AD-300I
512K x 36 GS8161Z36AD-250I
512K x 36 GS8161Z36AD-200I
512K x 36 GS8161Z36AD-150I
Notes:
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
165 BGA
165 BGA
TQFP
200/6.5
150/7.5
300/5
I
I
I
I
I
I
I
I
I
I
TQFP
250/5.5
200/6.5
150/7.5
300/5
TQFP
TQFP
165 BGA
165 BGA
165 BGA
165 BGA
250/5.5
200/6.5
150/7.5
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8161Z18AT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.03a 5/2003
35/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
18Mb Sync SRAM Data Sheet Revision History
DS/DateRev. Code: Old;
Types of Changes
Format or Content
Page;Revisions;Reason
New
• Creation of new datasheet
8161Z18A_r1
• Updated FT power numbers
• Updated AC Characteristics table
• Updated ZZ recovery time diagram
• Updated AC Test Conditions table and removed Output Load
2 diagram
8161Z18A_r1;
Content
8161Z18A_r1_01
• Removed extraneous V
table on page 12 and changed
DDQ1
8161Z18A_r1_01;
8161Z18A_r1_02
V
table to V
DDQ2 DDQ
Content
Content
• Removed pin locations from pin description table
• Removed BSR table
• Entire datasheet rewritten due to design changes
GS8161ZxxA_r1_02;
GS8161ZxxA_r1_03
Rev: 1.03a 5/2003
36/36
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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