GS8161Z18BD-200IVT [GSI]
ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165;型号: | GS8161Z18BD-200IVT |
厂家: | GSI TECHNOLOGY |
描述: | ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165 静态存储器 |
文件: | 总34页 (文件大小:2243K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
GS8161ZxxB(T/D)-xxxV
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
250 MHz–150 MHz
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
rail for proper operation. Asynchronous inputs include the
Features
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. Thifeature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
The GS8161ZxxB(T/D)-xxxV may be configured by the user
to operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registrs that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 100-lead TQFP and 165-bump FP-BGA
packages
• RoHS-compliant TQFPand BGA packages available
Functional Description
The GS8161ZxxB(T/D)-xxxV is implemented with GSI's high
performance CMOS technology and is available in JEDEC-
standard 100-pin TQFP and 165-bump FP-BGA packages.
The GS8161ZxxB(T/D)-xxxV is an 18Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
Parameter Synopsis
-250
-200
-150
Unit
tKQ(x18/x36)
tCycle
3.0
4.0
3.0
5.0
3.8
6.7
ns
ns
Pipeline
3-1-11
280
330
230
270
185
210
mA
mA
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
Flow Through
2-1-1-1
210
240
185
205
170
190
mA
mA
Curr (x18)
Curr (x32/x36)
Rev: 1.03 9/2008
1/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
GS8161Z18BT-xxxV Pinout (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
NC
NC
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
V
V
NC
DQPA
DQA
DQA
V
V
DQA
DQA5
V
NC
V
ZZ
DQA
DQA
V
V
DDQ
DDQ
V
SS
SS
NC
NC
DQB
DQB
1M x 18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
Top View
V
DDQ
DDQ
DQB
DQB
FT
SS
V
DD
NC
DD
V
SS
DQB
DQB
V
DDQ
DDQ
V
V
SS
SS
DQA
DQA
NC
NC
V
DQB
DQB
DQPB
NC
V
SS
SS
V
V
DDQ
DDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.03 9/2008
2/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
GS8161Z36BT-xxxV Pinout (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPB
DQB
DQB
DQPC
DQC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
V
DDQ
DDQ
V
V
SS
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
512K x 36
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
Top View
V
DDQ
DDQ
DQB
DQB
DQC
DQC
FT
V
SS
NC
V
DD
V
NC
DD
ZZ
DQA
DQA
V
SS
DQD
DQD
V
V
DDQ
DDQ
V
V
SS
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
SS
V
V
DDQ
DDQ
DQA
DQA
DQPA
DQD
DQD
DQPD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.03 9/2008
3/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
100-Pin TQFP Pin Descriptions
Symbol
A0, A1
A
Type
In
Description
Burst Address Inputs; Preload the burst counter
Address Inputs
In
CK
In
Clock Input Signal
BA
In
Byte Write signal for data inputs DQA1–DQA9; active low
Byte Write signal for data inputs DQB1–DQB9; active low
Byte Write signal for data inputs DQC1–DQC9; active low
Byte Write signal for data inputs DQD1–DQD9; active low
Write Enable; active low
BB
In
BC
In
BD
In
W
In
E1
In
Chip Enable; ctive low
E2
In
Chip Enable—Active High. For self decoded depth expansion
Chip Enable—Active Low. For self decoded depth expansion
Output Enable; active low
E3
In
G
In
ADV
CKE
NC
In
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
No Connect
In
—
I/O
I/O
I/O
I/O
In
DQA
DQB
DQC
DQD
ZZ
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
FT
In
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low.
LBO
MCH
In
—
In
Must Connect High (165 BGA only)
Core power supply
V
DD
V
In
In
Ground
SS
V
Output driver power supply
DDQ
Rev: 1.03 9/2008
4/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
A
11
A
A
B
C
D
E
F
NC
A
E1
BB
NC
E3
CKE
ADV
A
A
B
C
D
E
F
NC
NC
A
E2
NC
BA
CK
W
G
A
A
NC
NC
NC
NC
NC
NC
DQA
DQA
DQA
DQA
NC
A
NC
DQPA
DQA
DQA
DQA
DQA
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DQB
DQB
DQB
DQB
MCH
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
NC
G
H
J
NC
G
H
J
FT
NC
NC
DQB
DQB
DQB
DQB
DQPB
NC
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
NC
V
V
V
V
V
V
V
V
NC
K
L
NC
NC
M
N
P
R
NC
NC
M
N
P
R
NC
V
NC
TDI
NC
A1
A0
NC
V
NC
DDQ
SS
SS
DDQ
NC
A
A
A
TDO
TCK
A
A
A
NC
LBO
NC
A
TMS
A
A
A
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03 9/2008
5/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
165 Bump BGA—x32 Common I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
A
11
A
B
C
D
E
F
NC
A
E1
BC
BB
E3
CKE
ADV
A
NC
A
B
C
D
E
F
NC
NC
A
E2
BD
BA
CK
W
G
A
A
NC
NC
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
DQC
DQC
DQC
DQC
FT
DQC
DQC
DQC
DQC
MCH
DQD
DQD
DQD
DQD
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQB
DQB
DQB
DQB
NC
DQB
DQB
DQB
DQB
ZZ
G
H
J
G
H
J
NC
NC
DQD
DQD
DQD
DQD
NC
V
V
DQA
DQA
DQA
DQA
NC
DQA
DQA
DQA
DQA
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
V
V
V
V
V
V
V
V
K
L
M
N
P
R
M
N
P
R
V
NC
TDI
NC
A1
A0
NC
V
SS
DDQ
SS
DDQ
NC
NC
A
A
A
TDO
TCK
A
A
A
A
NC
LBO
NC
A
TMS
A
A
A
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03 9/2008
6/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
165 Bump BGA—x36 Common I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
A
11
A
B
C
D
E
F
NC
A
E1
BC
BB
E3
CKE
ADV
A
NC
A
B
C
D
E
F
NC
DQPC
DQC
DQC
DQC
DQC
FT
A
E2
BD
BA
CK
W
G
A
A
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
DQC
DQC
DQC
DQC
MCH
DQD
DQD
DQD
DQD
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQB
DQB
DQB
DQB
NC
G
H
J
G
H
J
NC
NC
DQD
DQD
DQD
DQD
DQPD
NC
V
V
DQA
DQA
DQA
DQA
NC
DQA
DQA
DQA
DQA
DQPA
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
V
V
V
V
V
V
V
V
K
L
M
N
P
R
M
N
P
R
V
NC
TDI
NC
A1
A0
NC
V
SS
DDQ
SS
DDQ
NC
A
A
A
TDO
TCK
A
A
A
A
LBO
NC
A
TMS
A
A
A
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03 9/2008
7/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
GS8161Z18/32/36B(T/D)-xxxV NBT SRAM Functional Block Diagram
s
n s e e S A m p
i t r e W D r i v e r
Rev: 1.03 9/2008
8/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
W
H
L
BA
X
BB
X
BC
X
BD
X
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is seleced, CKE is asserted low, and the write input is sampled low at the rising edge of
clock. The Byte Write Enable inputs (BA, BB, BC & BD) determine which bytes will be written. All or none may be activated. A
write cycle with no Byte Write inputs active s a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into thRAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.03 9/2008
9/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Synchronous Truth Table
Operation
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Abort, Begin Burst
Write Cycle, Continue Burst
Write Abort, Continue Burst
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Continue
Sleep Mode
R
B
R
B
W
D
B
B
D
D
D
D
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
H
L
H
X
H
X
L
X
X
X
X
L
L
X
L
H
X
H
X
H
H
X
X
X
X
L
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
Q
Q
1,10
2
External
Next
H
H
X
X
X
X
X
X
X
X
X
X
High-Z
H
L
X
L
X
L
High-Z 1,2,10
External
None
D
High-Z
D
3
1
L
L
H
L
L
L
Next
H
H
L
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
1,3,10
Next
H
X
X
X
X
X
X
High-Z 1,2,3,10
High-Z
None
None
L
High-Z
None
L
High-Z
None
H
X
X
X
X
X
High-Z
High-Z
-
1
4
None
Clock Edge Ignore, Stall
Current
L-H
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of ontrol signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is icorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.03 9/2008
10/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Pipelined and Flow Through Read Write Control State Diagram
D
B
Deselect
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
W
R
Burst Read
Burst Write
B
B
D
D
Key
Notes:
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram
Rev: 1.03 9/2008
11/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
R
W
B
Intermediate
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
Intermediate
D
Intermediate
W
R
High Z
B
D
Intermediate
Key
Notes:
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+2)
Intermediate State (N+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Intermediate
State
Current State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.03 9/2008
12/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Flow Through Mode Data I/O State Diagram
R
W
B
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
D
W
R
High Z
B
D
Key
Notes:
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow through Read Write Control State Diagram
Rev: 1.03 9/2008
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
L
Burst Order Control
LBO
H
L
Output Register Control
Power Down Control
FT
ZZ
H or NC
L or NC
H
Active
Standby, I = I
DD SB
Note:
There is a pull-up device on the FT pin and a pull-down device on thZZ pin, so this input pin can be unconnected and the chip will operate in
the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. ThereforeSleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
ZZ
tZZR
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found
on Pin 14. Not all vendors offer this option, however mosmark Pin 14 as V or V
on pipelined parts and V on flow
DD
DDQ
SS
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Rev: 1.03 9/2008
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 4.6
DD
DD
V
Voltage on V
Pins
–0.5 to V
V
DDQ
DDQ
DD
V
–0.5 to V
+0.5 (≤ 4.6 V ax.)
DDQ
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
V
I/O
V
–0.5 to V +0.5 (≤ 4.6 V max.)
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are eeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges (1.8 V/2.5 V Version)
Parameter
Symbol
Min.
1.7
Typ.
1.8
Max.
2.0
Unit
Notes
V
1.8 V Supply Voltage
2.5 V Supply Voltage
V
V
V
V
DD1
V
2.3
2.5
2.7
DD2
1.8 V V
I/O Supply Voltage
V
V
1.7
1.8
DDQ
DDQ
DDQ1
DD
2.5 V V
I/O Supply Voltage
V
V
2.3
2.5
DDQ2
DD
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
V
& V
Range Logic Levels
DDQ2
DDQ1
Parameter
Symbol
Min.
Typ.
—
Max.
Unit
V
Notes
V
V
Input High Voltage
V
0.6*V
V
+ 0.3
DD
1
1
DD
IH
DD
Input Low Voltage
V
0.3*V
DD
–0.3
—
V
DD
IL
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Recommended Operating Temperatures
Parameter
Symbol
Min.
0
Typ.
25
Max.
70
Unit
°C
Notes
T
Ambient Temperature (Commercial Range Versions)
2
2
A
T
Ambient Temperature (Industrial Range Versions)
–40
25
85
°C
A
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
DD
V
SS
50%
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
8
Max.
10
Unit
pF
C
V
= 0 V
Input Capacitance
IN
IN
C
V
OUT
= 0 V
Input/Output Capacitance
12
14
pF
I/O
Note:
These parameters are sample tested.
Rev: 1.03 9/2008
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
AC Test Conditions
Parameter
Conditions
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
/2
Figure 1
Output Load 1
Input slew rate
V
DQ
Input reference level
DD
V
/2
Output reference level
Output load
DDQ
*
50Ω
30pF
Fig. 1
Notes:
V
DDQ/2
* Distributed Test Jig Capacitance
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig.
1 unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
I
V
≥ V ≥ 0 V
DD IN
FT, ZZ Input Current
–100 uA
–1 uA
100 uA
1 uA
IN
I
Output Disable, V
= 0 to V
Output Leakage Current
OL
OUT DD
DC Output Characteristics (1.8 V/2.5 V Version)
Parameter
Symbol
Test Conditions
Min
Max
—
V
I
= –4 mA, V
= 1.7 V
V
– 0.4 V
DDQ
1.8 V Output High Voltage
2.5 V Output High Voltage
1.8 V Output Low Voltage
2.5 V Output Low Voltage
OH1
OH
DDQ
V
I
= –8 mA, V
= 2.375 V
DDQ
1.7 V
—
OH2
OH
V
I
I
= 4 mA
= 8 mA
—
—
0.4 V
0.4 V
OL1
OL
OL
V
OL2
Rev: 1.03 9/2008
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Operating Currents
-250
-200
-150
0
to
–40
to
0
to
–40
to
0
to
–40
to
Parameter
Test Conditions
Mode
Symbol
Unit
70°C
85°C
70°C
85°C
70°C
85°C
IDD
290
40
300
40
240
30
250
3
190
20
200
20
Pipeline
mA
mA
mA
mA
IDDQ
(x32/
x36)
IDD
220
20
230
20
190
15
200
15
175
15
185
15
Device Selected;
All other inputs
≥VIH or ≤ VIL
Flow Through
Pipeline
IDDQ
Operating
Current
IDD
260
20
270
20
215
15
225
15
170
15
180
15
Output open
IDDQ
(x18)
IDD
200
10
210
10
175
10
185
10
160
10
170
10
Flow Through
IDDQ
ISB
ISB
IDD
Pipeline
Flow Through
Pipeline
40
40
85
50
0
90
40
40
75
50
50
80
40
40
60
50
50
65
mA
mA
mA
Standby
Current
ZZ ≥ VDD – 0.2 V
—
—
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
Deselect
Current
IDD
Flow Through
6
65
50
55
50
55
mA
Notes:
1.
2. All parameters listed are worst case scenario.
I
and I
apply to any combination of V and V
operation.
DDQ
DD
DDQ
DD
Rev: 1.03 9/2008
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
AC Electrical Characteristics
-250
-200
-150
Unit
Parameter
Symbol
Min
4.0
—
Max
—
3.0
—
—
—
—
—
5.5
—
—
—
—
—
Min
5.0
—
Max
—
3.0
—
—
—
—
—
6.5
—
—
—
—
—
Min
6.7
—
Max
—
3.8
—
—
—
—
—
7.5
—
—
—
—
—
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKC
tKQ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
1.5
1.5
1.4
0.2
5.5
—
1.5
1.5
1.4
0.4
6.5
—
1.5
1.5
1.5
0.5
7.5
—
Pipeline
tLZ1
tS
Hold time
tH
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKC
tKQ
tKQX
2.0
2.0
1.5
0.5
1.3
2.0
2.0
1.5
0.5
1.3
2.0
2.0
1.5
0.5
1.5
Flow Through
tLZ1
tS
Hold time
tH
Clock HIGH Time
tKH
Clock LOW Time
tKL
1.7
1.5
—
1.7
1.5
—
1.7
1.5
—
ns
ns
Clock to Output in
High-Z
tHZ1
2.5
3.0
3.0
G to Output Valid
G to output in Low-Z
G to output in High-Z
ZZ setup time
tOE
—
0
2.5
—
2.5
—
—
—
—
0
3.0
—
3.0
—
—
—
—
0
3.8
—
3.8
—
—
—
ns
ns
ns
ns
ns
ns
tOLZ1
tOHZ1
tZZS2
tZZH2
tZZR
—
5
—
5
—
5
ZZ hold time
1
1
1
ZZ recovery
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in der to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Pipeline Mode Timing (NBT)
Write A
Write B
Write B+1
tKL
Read C
tKC
Cont
Read D
Write E
Read F
Write G
Deselect
tKH
CK
CKE
tH
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
E*
ADV
W
Bn
A0–An
DQa–DQd
A
B
C
D
E
F
G
tH
tLZ
tKQ
tHZ
tS
D(A)
tKQX
D(B)
D(B+1)
Q(C)
Q(D)
D(E)
Q(F)
D(G)
tOLZ
tOHZ
tOE
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Flow Through Mode Timing (NBT)
Write A
Write B
Write B+1
tKL
Read C
Cont
Read D
Write E
Read F
Write G
tKH
tKC
CK
CKE
E*
tH
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
ADV
W
Bn
A0–An
DQ
A
B
C
D
E
F
G
tH
tKQ
tLZ
tKQX
tKQ
tLZ
tS
D(A)
tHZ
tKQX
D(B)
D(B+1)
Q(C)
Q(D)
D(E)
Q(F)
D(G)
tOLZ
tOE
tOHZ
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output drivers
DD
are powered by V
.
DDQ
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked.
TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused,
TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
Rev: 1.03 9/2008
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI nd TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Regiters is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falliedge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register tat can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also incudes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Rev: 1.03 9/2008
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
·
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1
0
·
· · ·
Control Signals
Test Access Port (TAP) Controller
TMS
TCK
* For the value of M, see the BSDL file, which is available at by contacting us at apps@gsitechnology.com.
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
GSI Technology
Not Used
JEDEC Vendor
ID Code
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0 1 1 0 1 1 0 0 1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
Rev: 1.03 9/2008
24/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction egister are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
1
Capture DR
Capture IR
0
0
St DR
Shift IR
0
0
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
Rev: 1.03 9/2008
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© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s cntents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the istruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 1.03 9/2008
26/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
1
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
010
011
TDO.
1
1
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Registr between TDI and
TDO.
100
101
110
111
1
1
1
1
GSI
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.03 9/2008
27/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
JTAG Port Recommended Operating Conditions and DC Characteristics (1.8/2.5 V Version)
Parameter
Symbol
Min.
–0.3
Max.
Unit Notes
V
0.3 * V
1.8 V Test Port Input Low Voltage
2.5 V Test Port Input Low Voltage
1.8 V Test Port Input High Voltage
2.5 V Test Port Input High Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
V
V
1
1
ILJ1
DD1
V
0.3 * V
DD2
–0.3
ILJ2
V
0.6 * V
V
V
+0.3
+0.3
V
1
IHJ1
DD1
DD1
DD2
V
0.6 * V
DD2
V
1
IHJ2
I
–300
–1
1
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
Test Port Output High Voltage
1.7
—
0.4
—
5, 6
5, 7
5, 8
5, 9
OHJ
V
Test Port Output Low Voltage
—
V
OLJ
V
V
– 100 mV
DDQ
Test Port Output CMOS High
V
OHJC
V
Test Port Output CMOS Low
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –2 V < Vi < V
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
3. 0 V ≤ V ≤ V
IN
ILJn
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V
supply.
DDQ
6.
7.
8.
9.
I
I
I
I
= –4 mA
OHJ
= + 4 mA
OLJ
= –100 uA
= +100 uA
OHJC
OLJC
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
V
– 0.2 V
Input high level
Input low level
DQ
DD
0.2 V
1 V/ns
*
50Ω
Input slew rate
30pF
V
V
/2
Input reference level
DDQ
V
/2
DDQ
/2
Output reference level
DDQ
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.03 9/2008
28/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
tTH
tTH
tTS
tTS
TDI
TMS
TDO
tTKQ
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
Max
—
Unit
TCK Cycle Time
50
—
ns
ns
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
20
20
10
10
—
—
tTH
—
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
Rev: 1.03 9/2008
29/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
TQFP Package Drawing (Package T)
θ
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
0.10
7°
θ
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.03 9/2008
30/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Package Dimensions—165-Bump FPBGA (Package D)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.60 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
1.0
13±0.05
B
0.20(4x)
SEATING PLANE
C
Rev: 1.03 9/2008
31/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Ordering Information for GSI Synchronous Burst RAMs
2
Voltage
Option
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
1M x 18
1M x 18
GS8161Z18BT-250V
GS8161Z18BT-200V
GS8161Z18BT-150V
GS8161Z36BT-250V
GS8161Z36BT-200V
GS8161Z36BT-150V
GS8161Z18BT-250IV
GS8161Z18BT-200IV
GS8161Z18BT-150IV
GS8161Z36BT-250IV
GS8161Z36BT-200IV
GS8161Z36BT-150IV
GS8161Z18BD-250V
GS8161Z18BD-200V
GS8161Z18BD-150V
GS8161Z32BD-250V
GS8161Z32BD-200V
GS8161Z32BD-150V
GS8161Z36BD-250V
GS8161Z36BD-200V
GS8161Z36BD-150V
GS8161Z18BD-250IV
GS8161Z18BD-200IV
GS8161Z18BD-150IV
GS8161Z32BD-250IV
GS8161Z32BD-200IV
GS8161Z32BD-150IV
GS8161Z36BD-250IV
GS8161Z36BD-200IV
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
TQFP
TQFP
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
C
C
C
C
C
C
I
1M x 18
TQFP
512K x 36
512K x 36
512K x 36
1M x 18
TQFP
TQF
TQFP
TQFP
1M x 18
TQFP
I
1M x 18
TQFP
I
512K x 36
512K x 36
512K x 36
1M x 18
TQFP
I
TQFP
I
TQFP
I
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
C
C
C
C
C
C
C
C
C
I
1M x 18
1M x 18
512K x 32
512K x 32
512K x 32
512K x 36
512K x 36
512K x 36
1M x 18
1M x 18
I
1M x 18
I
512K x 32
512K x 32
512K x 32
512K x 36
512K x 36
I
I
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8161Z18BT-
150VT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.03 9/2008
32/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
Ordering Information for GSI Synchronous Burst RAMs (Continued)
2
Voltage
Option
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
512K x 36
1M x 18
GS8161Z36BD-150IV
GS8161Z18BGT-250V
GS8161Z18BGT-200V
GS8161Z18BGT-150V
GS8161Z36BGT-250V
GS8161Z36BGT-200V
GS8161Z36BGT-150V
GS8161Z18BGT-250IV
GS8161Z18BGT-200IV
GS8161Z18BGT-150IV
GS8161Z36BGT-250IV
GS8161Z36BGT-200IV
GS8161Z36BGT-150IV
GS8161Z18BGD-250V
GS8161Z18BGD-200V
GS8161Z18BGD-150V
GS8161Z32BGD-250V
GS8161Z32BGD-200V
GS8161Z32BGD-150V
GS8161Z36BGD-250V
GS8161Z36BGD-200V
GS8161Z36BGD-150V
GS8161Z18BGD-250IV
GS8161Z18BGD-200IV
GS8161Z18BGD-150IV
GS8161Z32BGD-250IV
GS8161Z32BGD-200IV
GS8161Z32BGD-150IV
GS8161Z36BGD-250IV
GS8161Z6BGD-200IV
GS8161Z36BGD-150IV
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NB
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
165 BGA
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
250/5.5
200/6.5
150/7.5
I
C
C
C
C
C
C
I
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQF
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
1M x 18
1M x 18
512K x 36
512K x 36
512K x 36
1M x 18
1M x 18
I
1M x 18
I
512K x 36
512K x 36
512K x 36
1M x 18
I
I
I
C
C
C
C
C
C
C
C
C
I
1M x 18
1M x 18
512K x 32
512K x 32
512K x 32
512K x 36
512K x 36
512K x 36
1M x 18
1M x 18
I
1M x 18
I
512K x 32
512K x 32
512K x 32
512K x 36
512K x 36
512K x 36
I
I
I
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8161Z18BT-
150VT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.03 9/2008
33/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxB(T/D)-xxxV
18Mb Sync SRAM Data Sheet Revision History
DS/DateRev. Code: Old;
Types of Changes
Format or Content
Page;Revisions;Reason
New
• Creation of new datasheet
8161ZVxxB_r1
• Updated Abs Max section
8161ZVxxB_r1;
8161ZxxB-xxxV
• Updated AC Characteristics table
• Changed ordering information to relect new nomenclature
• (Rev1.01a: Corrected JTAG Op Cond table)
Content
• Added MCH to Pin Description (pg. 4), removed Status column
from Ordering Information table, Updated 165 BGA Package
Drawing
8161ZVxxB_r1.01;
8161ZVxxB_r1.02
Content
Content
• Updated for MP status
8161ZVxxB_r1.02;
8161ZVxxB_r1.03
Rev: 1.03 9/2008
34/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
相关型号:
GS8161Z18BGD-150IT
ZBT SRAM, 1MX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-165
GSI
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