GS8162Z18BB-300 [GSI]
ZBT SRAM, 1MX18, 5.3ns, CMOS, PBGA119, FBGA-119;型号: | GS8162Z18BB-300 |
厂家: | GSI TECHNOLOGY |
描述: | ZBT SRAM, 1MX18, 5.3ns, CMOS, PBGA119, FBGA-119 静态存储器 |
文件: | 总30页 (文件大小:1386K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Preliminary
GS8162Z18/36B(B/D)
300 MHz–150 MHz
119- & 165-Bump BGA
Commercial Temp
Industrial Temp
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Features
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• On-chip parity encoding and error detection
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
The GS8162Z18/36B(B/D) may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-bump and 165-bump BGA packages
• Pb-Free 119-bump and 165-bump BGA packages available
Functional Description
The GS8162Z18/36B(B/D) is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump or 165-bump BGA package.
The GS8162Z18/36B(B/D) is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
-300
-250
-200
-150
Unit
2.5
3.3
2.5
4.0
3.0
5.0
3.8
6.7
ns
ns
tKQ
tCycle
Pipeline
3-1-1-1
335
390
280
330
230
270
185
210
mA
mA
Curr (x18)
Curr (x36)
tKQ
5.3
5.3
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
tCycle
Flow Through
2-1-1-1
230
270
210
240
185
205
170
190
mA
mA
Curr (x18)
Curr (x36)
Rev: 1.03 4/2005
1/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
E1
BB
NC
E3
CKE
ADV
A
A
A
A
A
B
C
D
E
F
NC
NC
A
E2
NC
BA
CK
W
G
A
NC
DQPA
DQA
DQA
DQA
DQA
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
NC
NC
NC
NC
ZQ
DQA
DQA
DQA
DQA
NC
A
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DQB
DQB
DQB
DQB
MCH
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
NC
G
H
J
NC
G
H
J
FT
NC
NC
DQB
DQB
DQB
DQB
DQPB
NC
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
NC
V
V
V
V
V
V
V
V
NC
K
L
NC
NC
M
N
P
R
NC
NC
M
N
P
R
DNU
NC
V
NC
TDI
NC
A1
A0
NC
V
NC
DDQ
SS
SS
DDQ
A
A
A
TDO
TCK
A
A
A
NC
LBO
NC
A
TMS
A
A
A
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03 4/2005
2/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
165 Bump BGA—x36 Common I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
E1
BC
BB
E3
CKE
ADV
A
A
NC
A
B
C
D
E
F
NC
DQPC
DQC
DQC
DQC
DQC
FT
A
E2
BD
BA
CK
W
G
A
A
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
DQC
DQC
DQC
DQC
MCH
DQD
DQD
DQD
DQD
DNU
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQB
DQB
DQB
DQB
ZQ
G
H
J
G
H
J
NC
NC
DQD
DQD
DQD
DQD
DQPD
NC
V
V
DQA
DQA
DQA
DQA
NC
DQA
DQA
DQA
DQA
DQPA
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
V
V
V
V
V
V
V
V
K
L
M
N
P
R
M
N
P
R
V
NC
TDI
NC
A1
A0
NC
V
SS
DDQ
SS
DDQ
A
A
A
TDO
TCK
A
A
A
A
LBO
NC
A
TMS
A
A
A
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03 4/2005
3/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
GS8162Z36B Pad Out—119-Bump BGA—Top View (Package B)
1
2
A
3
A
A
A
4
A
5
A
A
A
6
A
7
A
B
C
D
E
F
V
V
DDQ
DDQ
NC
NC
E2
ADV
E3
NC
NC
A
V
A
DD
DQC
DQC
DQPC
DQC
DQC
DQC
DQC
V
ZQ
E1
G
V
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
DDQ
DDQ
G
H
J
DQC
BC
A
BB
DQB
DQC
V
W
V
DQB
SS
SS
V
V
NC
V
NC
V
V
DDQ
DDQ
DD
DD
DD
K
L
DQD
DQD
DQD
DQD
DQD
DQPD
A
V
CK
V
DQA
DQA
DQA
DQA
DQPA
A
DQA
SS
SS
DQD
BD
NC
CKE
A1
BA
DQA
M
N
P
R
T
V
V
V
V
DDQ
DDQ
SS
SS
SS
SS
SS
SS
DQD
V
V
V
V
DQA
DQD
NC
A0
DQA
NC
ZZ
LBO
A
V
FT
DD
NC
NC
A
A
NC
U
V
TMS
TDI
TCK
TDO
NC
V
DDQ
DDQ
Rev: 1.03 4/2005
4/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
GS8162Z18B Pad Out—119-Bump BGA—Top View (Package B)
1
2
A
3
A
A
A
4
A
5
A
A
A
6
A
7
A
B
C
D
E
F
V
V
DDQ
DDQ
NC
NC
E2
ADV
E3
NC
NC
A
V
A
DD
DQB
NC
NC
DQB
NC
DQB
NC
V
ZQ
E1
G
V
DQPA
NC
DQA
NC
DQA
NC
SS
SS
SS
SS
SS
SS
V
V
V
V
DQA
V
V
DDQ
DDQ
G
H
J
NC
BB
A
NC
DQA
DQB
V
W
V
NC
SS
SS
V
V
NC
V
NC
V
V
DDQ
DDQ
DD
DD
DD
K
L
NC
DQB
NC
V
CK
V
NC
DQA
NC
DQA
NC
A
DQA
SS
SS
DQB
NC
NC
CKE
A1
BA
NC
M
N
P
R
T
V
DQB
NC
V
V
V
V
V
DDQ
DDQ
SS
SS
SS
SS
SS
SS
DQB
V
V
NC
NC
NC
NC
DQPB
A
A0
DQA
NC
ZZ
LBO
A
V
FT
DD
A
NC
A
A
U
V
TMS
TDI
TCK
TDO
NC
V
DDQ
DDQ
Rev: 1.03 4/2005
5/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
GS8162Z18/36 119-Bump and 165-Bump BGA Pin Description
Symbol
A0, A1
A
Type
Description
I
I
Address field LSBs and Address Counter Preset Inputs
Address Inputs
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA, BB, BC, BD
I
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
NC
CK
CKE
W
Clock Input Signal; active high
Clock Enable; active low
I
I
Write Enable; active low
E1
I
Chip Enable; active low
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
ZZ
I
Burst address counter advance enable; active high
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
I
FT
I
LBO
I
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
ZQ
I
I
I
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
TMS
TDI
O
I
TDO
TCK
V
I
Core power supply
I/O and Core Ground
DD
V
I
SS
V
I
Output driver power supply
DDQ
BPR1999.05.18
Rev: 1.03 4/2005
6/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
W
H
L
BA
X
BB
X
BC
X
BD
X
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is asserted low, and the Write input is sampled low at the rising edge of
clock. The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A
write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.03 4/2005
7/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Synchronous Truth Table
Operation
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
R
B
R
B
W
B
B
D
D
D
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L
L
L
L
L
L
L
L
L
L
L
H
L
H
X
H
X
L
X
X
X
X
L
L
X
L
H
X
H
X
H
X
X
X
X
L
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
Q
Q
1,10
2
External
Next
H
H
X
X
X
X
X
X
High-Z
Dummy Read, Continue Burst
Write Cycle, Begin Burst
H
L
X
L
X
L
High-Z 1,2,10
External
Next
D
D
3
Write Cycle, Continue Burst
Write Abort, Continue Burst
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
H
H
L
X
X
X
X
X
L
X
X
H
X
X
X
X
X
H
X
1,3,10
Next
H
X
X
X
High-Z 1,2,3,10
High-Z
None
None
L
High-Z
None
L
High-Z
1
Deselect Cycle
D
D
None
L-H
L
L
L
H
L
H
L
X
L
High-Z
Deselect Cycle, Continue
Sleep Mode
None
None
L-H
X
L
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
High-Z
High-Z
-
1
4
Clock Edge Ignore, Stall
Current
L-H
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.03 4/2005
8/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Pipelined and Flow Through Read Write Control State Diagram
D
B
Deselect
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
W
R
Burst Read
Burst Write
B
B
D
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram
Rev: 1.03 4/2005
9/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
R
W
B
Intermediate
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
Intermediate
D
Intermediate
W
R
High Z
B
D
Intermediate
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+2)
Intermediate State (N+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Intermediate
State
Current State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.03 4/2005
10/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Flow Through Mode Data I/O State Diagram
R
W
B
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
D
W
R
High Z
B
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 1.03 4/2005
11/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
FLXDrive™
The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Mode Pin Functions
Pin
Mode Name
Burst Order Control
Output Register Control
Power Down Control
State
Function
Name
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
LBO
H
L
FT
ZZ
ZQ
H or NC
L or NC
H
Active
Standby, I = I
DD SB
L
High Drive (Low Impedance)
Low Drive (High Impedance)
FLXDrive Output Impedance Control
H or NC
Note:
There arepull-up devices on the ZQ and FT pins and pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Rev: 1.03 4/2005
12/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
01
00
10
11
11
10
10
11
11
10
00
01
01
00
Note:
Note:
The burst counter wraps to initial state on the 5th clock.
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
ZZ
tZZR
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Bump 5R. Not all vendors offer this option, however most mark Bump 5R as V or V
on pipelined parts and V
DD
DDQ
SS
on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.
Rev: 1.03 4/2005
13/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Operating Currents
-300
-250
-200
-150
0
to
°C
–40
to
85°C
0
to
–40
to
0
to
–40
to
0
to
–40
to
Parameter
Test Conditions
Mode
Symbol
Unit
70°C 85°C 70°C 85°C 70°C 85°C
IDD
345
45
355
45
290
40
300
40
240
30
250
30
190
20
200
20
Pipeline
mA
mA
mA
mA
IDDQ
(x36)
(x18)
IDD
Flow
Through
240
30
250
30
220
20
230
20
190
15
200
15
175
15
185
15
Device Selected;
All other inputs
≥VIH or ≤ VIL
IDDQ
Operating
Current
IDD
310
25
320
25
260
20
270
20
215
15
225
15
170
15
180
15
Pipeline
Output open
IDDQ
IDD
Flow
Through
215
15
225
15
200
10
210
10
175
10
185
10
160
10
170
10
IDDQ
ISB
ISB
IDD
IDD
Pipeline
40
40
85
60
50
50
90
65
40
40
85
60
50
50
90
65
40
40
75
50
50
50
80
55
40
40
60
50
50
50
65
55
mA
mA
mA
mA
Standby
Current
ZZ ≥ VDD – 0.2 V
—
—
Flow
Through
Pipeline
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
Deselect
Current
Flow
Through
Notes:
1.
2. All parameters listed are worst case scenario.
I
and I
apply to any combination of V , V , V
, and V
operation.
DDQ2
DD
DDQ
DD3 DD2 DDQ3
Rev: 1.03 4/2005
14/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
AC Electrical Characteristics
-300
-250
-200
-150
Unit
Parameter
Symbol
Min
3.3
—
Max
—
2.5
—
—
—
—
—
5.3
—
—
—
—
—
Min
4.0
—
Max
—
2.5
—
—
—
—
—
5.5
—
—
—
—
—
Min
5.0
—
Max
—
3.0
—
—
—
—
—
6.5
—
—
—
—
—
Min
6.7
—
Max
—
3.8
—
—
—
—
—
7.5
—
—
—
—
—
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
tKC
tKQ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
1.5
1.5
1.0
0.1
5.3
—
1.5
1.5
1.2
0.2
5.5
—
1.5
1.5
1.4
0.4
6.5
—
1.5
1.5
1.5
0.5
7.5
—
Pipeline
tLZ1
tS
Clock to Output in Low-Z
Setup time
Hold time
tH
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
tKC
tKQ
tKQX
2.0
2.0
1.4
0.4
1.0
2.0
2.0
1.5
0.5
1.3
2.0
2.0
1.5
0.5
1.3
2.0
2.0
1.5
0.5
1.5
Flow Through
tLZ1
tS
Clock to Output in Low-Z
Setup time
Hold time
tH
Clock HIGH Time
tKH
Clock LOW Time
tKL
1.2
1.5
—
1.5
1.5
—
1.5
1.5
—
1.7
1.5
—
ns
ns
Clock to Output in
High-Z
tHZ1
2.5
2.5
3.0
3.0
G to Output Valid
G to output in Low-Z
G to output in High-Z
ZZ setup time
tOE
—
0
2.5
—
2.5
—
—
—
—
0
2.5
—
2.5
—
—
—
—
0
3.0
—
3.0
—
—
—
—
0
3.8
—
3.8
—
—
—
ns
ns
ns
ns
ns
ns
tOLZ1
tOHZ1
tZZS2
tZZH2
tZZR
—
5
—
5
—
5
—
5
ZZ hold time
1
1
1
1
ZZ recovery
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.03 4/2005
15/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Pipeline Mode Timing (NBT)
Write A
Read B
Suspend
tKH
Read C
tKC
Write D
writeno-op
Read E
Deselect
tKL
CK
A
tH
tH
tH
tH
tH
tH
tS
A
B
C
D
E
tS
tS
tS
tS
tS
CKE
E*
ADV
W
tH
tS
Bn
tH
tLZ
tKQ
tHZ
tS
tKQX
D(A)
Q(B)
Q(C)
D(D)
Q(E)
DQ
Rev: 1.03 4/2005
16/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Flow Through Mode Timing (NBT)
Write A
Write B
Write B+1 Read C
tKL
Cont
Read D
Write E
Read F
Write G
tKH
tKC
CK
CKE
E
tH
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
ADV
W
Bn
A0–An
A
B
C
D
E
F
G
tKQ
tLZ
tH
tKQ
tLZ
D(B+1)
tKQX
tS
D(A)
tHZ
Q(D)
tKQX
D(G)
DQ
D(B)
Q(C)
D(E)
Q(F)
tOLZ
tOE
tOHZ
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 1.03 4/2005
17/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DDQ
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 1.03 4/2005
18/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
·
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1
0
·
· · ·
Control Signals
Test Access Port (TAP) Controller
TMS
TCK
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.03 4/2005
19/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
ID Code
I/O
Not Used
Configuration
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
1
1
1
1
1
x72
x36
x32
x18
x16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
X
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.03 4/2005
20/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
1
1
Exit2 DR
Exit2 IR
0
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Rev: 1.03 4/2005
21/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
1
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
010
011
TDO.
1
1
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
100
101
110
111
1
1
1
1
GSI
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.03 4/2005
22/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
2.0
Max.
Unit Notes
V
V
V
+0.3
DD3
3.3 V Test Port Input High Voltage
3.3 V Test Port Input Low Voltage
2.5 V Test Port Input High Voltage
2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
V
V
1
1
IHJ3
V
–0.3
0.8
+0.3
ILJ3
V
0.6 * V
V
1
IHJ2
DD2
DD2
V
0.3 * V
1
–0.3
–300
–1
V
1
ILJ2
DD2
I
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
Test Port Output High Voltage
1.7
—
5, 6
5, 7
5, 8
5, 9
OHJ
V
Test Port Output Low Voltage
—
0.4
V
OLJ
V
V
– 100 mV
DDQ
Test Port Output CMOS High
—
V
OHJC
V
Test Port Output CMOS Low
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V
+1.5 V maximum, with a pulse width not to exceed 50% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
3. 0 V ≤ V ≤ V
IN
ILJn
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V
supply.
DDQ
6.
7.
8.
9.
I
I
I
I
= –4 mA
OHJ
= + 4 mA
OLJ
= –100 uA
= +100 uA
OHJC
OHJC
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
V
– 0.2 V
Input high level
Input low level
DQ
DD
0.2 V
1 V/ns
*
50Ω
Input slew rate
30pF
V
V
/2
Input reference level
DDQ
V
/2
DDQ
/2
Output reference level
DDQ
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.03 4/2005
23/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
TDI
tTH
tTH
tTS
tTS
TMS
TDO
tTKQ
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
Max
—
Unit
TCK Cycle Time
50
—
ns
ns
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
20
20
10
10
—
—
tTH
—
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
Rev: 1.03 4/2005
24/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Package Dimensions—165-Bump FPBGA (Package D; Variation 2)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.44~0.64 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
1.0
13±0.07
B
0.20(4x)
SEATING PLANE
C
Rev: 1.03 4/2005
25/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
TOP VIEW
BOTTOM VIEW
A1
A1
S
Ø0.10
C
S
S
S
Ø0.30 C A
B
Ø0.60~0.90 (119x)
1
2
3
4
5
6
7
7
6
5
4 3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
M
N
P
R
T
U
K
L
M
N
P
R
T
U
B
1.27
7.62
14±0.10
A
0.20(4x)
SEATING PLANE
C
Rev: 1.03 4/2005
26/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
1M x 18
1M x 18
GS8162Z18BB-300
GS8162Z18BB-250
GS8162Z18BB-200
GS8162Z18BB-150
GS8162Z36BB-300
GS8162Z36BB-250
GS8162Z36BB-200
GS8162Z36BB-150
GS8162Z18BB-300I
GS8162Z18BB-250I
GS8162Z18BB-200I
GS8162Z18BB-150I
GS8162Z36BB-300I
GS8162Z36BB-250I
GS8162Z36BB-200I
GS8162Z36BB-150I
GS8162Z18BGB-300
GS8162Z18BGB-250
GS8162Z18BGB-200
GS8162Z18BGB-150
GS8162Z36BGB-300
GS8162Z36BGB-250
GS8162Z36BGB-200
GS8162Z36BGB-150
GS8162Z18BGB-300I
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
119 BGA (Var. 2)
119 BGA (Var. 2)
300/5.3
250/5.5
200/6.5
150/7.5
300/5.3
250/5.5
200/6.5
150/7.5
300/5.3
250/5.5
200/6.5
150/7.5
300/5.3
250/5.5
200/6.5
150/7.5
300/5.3
250/5.5
200/6.5
150/7.5
300/5.3
250/5.5
200/6.5
150/7.5
300/5.3
C
C
C
C
C
C
C
C
I
1M x 18
119 BGA (Var. 2)
1M x 18
119 BGA (Var. 2)
512K x 36
512K x 36
512K x 36
512K x 36
1M x 18
119 BGA (Var. 2)
119 BGA (Var. 2)
119 BGA (Var. 2)
119 BGA (Var. 2)
119 BGA (Var. 2)
1M x 18
119 BGA (Var. 2)
I
1M x 18
119 BGA (Var. 2)
I
1M x 18
119 BGA (Var. 2)
I
512K x 36
512K x 36
512K x 36
512K x 36
1M x 18
119 BGA (Var. 2)
I
119 BGA (Var. 2)
I
119 BGA (Var. 2)
I
119 BGA (Var. 2)
I
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
C
C
C
C
C
C
C
C
I
1M x 18
1M x 18
1M x 18
512K x 36
512K x 36
512K x 36
512K x 36
1M x 18
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162Z36BB-200IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.03 4/2005
27/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Ordering Information for GSI Synchronous Burst RAMs (Cont.)
2
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
1M x 18
1M x 18
GS8162Z18BGB-250I
GS8162Z18BGB-200I
GS8162Z18BGB-150I
GS8162Z36BGB-300I
GS8162Z36BGB-250I
GS8162Z36BGB-200I
GS8162Z36BGB-150I
GS8162Z18BD-300
GS8162Z18BD-250
GS8162Z18BD-200
GS8162Z18BD-150
GS8162Z36BD-300
GS8162Z36BD-250
GS8162Z36BD-200
GS8162Z36BD-150
GS8162Z18BD-300I
GS8162Z18BD-250I
GS8162Z18BD-200I
GS8162Z18BD-150I
GS8162Z36BD-300I
GS8162Z36BD-250I
GS8162Z36BD-200I
GS8162Z36BD-150I
GS8162Z18BGD-300
GS8162Z18BGD-250
GS8162Z18BGD-200
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
Pb-Free 119 BGA (Var. 2)
165 BGA (Var. 2)
250/5.5
200/6.5
150/7.5
300/5.3
250/5.5
200/6.5
150/7.5
300/5.3
250/5.5
200/6.5
150/7.5
300/5.3
250/5.5
200/6.5
150/7.5
300/5.3
250/5.5
200/6.5
150/7.5
300/5.3
250/5.5
200/6.5
150/7.5
300/5.3
250/5.5
200/6.5
I
I
I
I
I
I
I
1M x 18
512K x 36
512K x 36
512K x 36
512K x 36
1M x 18
C
C
C
C
C
C
C
C
I
1M x 18
165 BGA (Var. 2)
1M x 18
165 BGA (Var. 2)
1M x 18
165 BGA (Var. 2)
512K x 36
512K x 36
512K x 36
512K x 36
1M x 18
165 BGA (Var. 2)
165 BGA (Var. 2)
165 BGA (Var. 2)
165 BGA (Var. 2)
165 BGA (Var. 2)
1M x 18
165 BGA (Var. 2)
I
1M x 18
165 BGA (Var. 2)
I
1M x 18
165 BGA (Var. 2)
I
512K x 36
512K x 36
512K x 36
512K x 36
1M x 18
165 BGA (Var. 2)
I
165 BGA (Var. 2)
I
165 BGA (Var. 2)
I
165 BGA (Var. 2)
I
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
C
C
C
1M x 18
1M x 18
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162Z36BB-200IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.03 4/2005
28/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
Ordering Information for GSI Synchronous Burst RAMs (Cont.)
2
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
1M x 18
512K x 36
512K x 36
512K x 36
512K x 36
1M x 18
GS8162Z18BGD-150
GS8162Z36BGD-300
GS8162Z36BGD-250
GS8162Z36BGD-200
GS8162Z36BGD-150
GS8162Z18BGD-300I
GS8162Z18BGD-250I
GS8162Z18BGD-200I
GS8162Z18BGD-150I
GS8162Z36BGD-300I
GS8162Z36BGD-250I
GS8162Z36BGD-200I
GS8162Z36BGD-150I
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
Pb-Free 165 BGA (Var. 2)
150/7.5
300/5.3
250/5.5
200/6.5
150/7.5
300/5.3
250/5.5
200/6.5
150/7.5
300/5.3
250/5.5
200/6.5
150/7.5
C
C
C
C
C
I
1M x 18
I
1M x 18
I
1M x 18
I
512K x 36
512K x 36
512K x 36
512K x 36
I
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162Z36BB-200IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.03 4/2005
29/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18/36B(B/D)
18Mb Sync SRAM Datasheet Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Page;Revisions;Reason
New
• Creation of new datasheet
GS8162ZxxB_r1
• Updated overshoot/undershoot information
GS8162ZxxB_r1;
GS8162ZxxB_r1_01
Content
Content
Content
• Added 165 BGA information
• Added Pb-free information
• Added 300 MHz speed bin
GS8162ZxxB_r1_01;
GS8162ZxxB_r1_02
• Corrected extra DQA pins on x36 119 BGA pinout (changed to
DQD)
GS8162ZxxB_r1_02;
GS8162ZxxB_r1_03
Rev: 1.03 4/2005
30/30
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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