GS8170DW72AC-250IT [GSI]
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| 型号： | GS8170DW72AC-250IT |
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GSI TECHNOLOGY |
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GS8170DW36/72AC-350/333/300/250
250 MHz–350 MHz
209-Bump BGA
Commercial Temp
Industrial Temp
18Mb Σ1x1Dp CMOS I/O
Double Late Write SigmaRAM™
1.8 V V
DD
1.8 V I/O
Features
• Double Late Write mode, Pipelined Read mode
• JEDEC-standard SigmaRAM™ pinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• Byte write operation (9-bit bytes)
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
• Pb-Free 209-bump BGA package available
Bottom View
SigmaRAM Family Overview
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
GS8170DW36/72A SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
Functional Description
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
ΣRAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
ΣRAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The ΣRAM™ family standard
allows a user to implement the interface protocol best suited to
the task at hand.
ΣRAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Parameter Synopsis
Key Fast Bin Specs
Cycle Time
Symbol
tKHKH
tKHQV
- 350
2.86 ns
1.7 ns
Access Time
Rev: 1.04 4/2005
1/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
SigmaRAM Pinouts
256K x 72 Common I/O—Top View (Package C)
1
2
3
4
5
A
6
ADV
W
7
A
8
9
A
10
11
A
B
C
DQg
DQg
DQg
DQg
DQg
DQg
A
E2
Bg
Bd
E3
Bb
Be
DQb
DQb
DQb
DQb
DQb
DQb
Bc
Bh
NC
A
Bf
Ba
NC
E1
NC
(144M)
D
E
F
DQg
DQg
DQc
DQc
DQc
DQc
CQ2
DQh
DQh
DQh
DQh
DQd
DQd
DQd
DQg
DQc
DQc
DQc
DQc
DQc
CQ2
DQh
DQh
DQh
DQh
DQh
DQd
DQd
V
NC
NC
MCL
NC
NC
V
DQb
DQf
DQf
DQf
DQf
DQf
CQ1
DQa
DQa
DQa
DQa
DQa
DQe
DQe
DQb
DQb
DQf
DQf
DQf
DQf
CQ1
DQa
DQa
DQa
DQa
DQe
DQe
DQe
SS
SS
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DD
DD
DD
DDQ
DDQ
V
V
V
ZQ
V
V
V
SS
SS
SS
SS
SS
SS
G
H
J
V
V
EP2
V
V
DDQ
DDQ
DD
DD
DDQ
DDQ
V
V
V
EP3
V
V
V
SS
SS
SS
SS
SS
SS
V
V
MCH
MCL
MCH
MCL
MCH
MCL
V
V
DDQ
DDQ
DD
DD
DDQ
DDQ
K
L
CK
NC
V
V
NC
NC
SS
SS
V
V
V
V
V
V
DDQ
DDQ
DDQ
DD
DD
DDQ
M
N
P
R
T
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
DDQ
DDQ
DD
DD
DDQ
DDQ
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
DDQ
DDQ
DD
DD
DD
DDQ
DDQ
V
NC
A
NC
MCL
A
NC
NC
A
V
SS
SS
U
NC
NC
NC
NC
(72M)
(36M)
V
DQd
DQd
DQd
DQd
A
A
A
A
A1
A0
A
A
A
A
DQe
DQe
DQe
DQe
W
• 2002.06
•
TMS
TDI
TDO
TCK
2
11 x 19 Bump BGA—14 x 22 mm Body—1 mm Bump Pitch
Note:
Users of CMOS I/O SigmaRAMs may wish to connect “NC, V ” and the “NC, CK” pins to V
(i.e., V
/2) to
DDQ
REF
REF
allow alternate use of future HSTL I/O SigmaRAMs.
Rev: 1.04 4/2005
2/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
512K x 36 Common I/O—Top View (Package C)
1
2
3
4
5
A
A
6
ADV
W
7
A
8
9
10
11
A
B
C
NC
NC
NC
NC
NC
NC
A
E2
NC
Bd
E3
Bb
NC
A
DQb
DQb
DQb
DQb
DQb
DQb
Bc
NC
A
NC
Ba
NC
E1
NC
(144M)
D
E
F
NC
NC
NC
DQc
DQc
DQc
DQc
DQc
CQ2
NC
V
NC
NC
MCL
NC
NC
V
DQb
NC
DQb
DQb
NC
SS
SS
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DD
DD
DD
DDQ
DDQ
DQc
DQc
DQc
DQc
CQ2
NC
V
V
V
ZQ
V
V
V
NC
SS
SS
SS
SS
SS
SS
G
H
J
V
V
EP2
V
V
NC
NC
DDQ
DDQ
DD
DD
DDQ
DDQ
V
V
V
EP3
V
V
V
NC
NC
SS
SS
SS
SS
SS
SS
V
V
MCH
MCL
MCH
MCL
MCH
MCL
V
V
NC
NC
DDQ
DDQ
DD
DD
DDQ
DDQ
K
L
CK
NC
V
V
NC
NC
CQ1
DQa
DQa
DQa
DQa
DQa
NC
CQ1
DQa
DQa
DQa
DQa
NC
SS
SS
V
V
V
V
V
V
DDQ
DDQ
DDQ
DD
DD
DDQ
M
N
P
R
T
NC
NC
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
NC
NC
V
V
V
V
V
V
DDQ
DDQ
DD
DD
DDQ
DDQ
NC
NC
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
DQd
DQd
DQd
NC
V
V
V
V
V
V
V
DDQ
DDQ
DD
DD
DD
DDQ
DDQ
DQd
DQd
V
NC
A
NC
MCL
A
NC
NC
A
V
NC
SS
SS
U
NC
NC
NC
NC
NC
NC
(72M)
(36M)
V
DQd
DQd
DQd
DQd
A
A
A
A
A1
A0
A
A
A
A
NC
NC
NC
NC
W
TMS
TDI
TDO
TCK
2
• 2002.06
11 x 19 Bump BGA—14 x 22 mm Body—1 mm Bump Pitch
•
Note:
Users of CMOS I/O SigmaRAMs may wish to connect “NC, V ” and the “NC, CK” pins to V
(i.e., V
/2) to
DDQ
REF
REF
allow alternate use of future HSTL I/O SigmaRAMs.
Rev: 1.04 4/2005
3/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
Pin Description Table
Symbol
A
Description
Address
Type
Input
Comments
—
Active High
ADV
Advance
Input
Bx
Byte Write Enable
Write Enable
Chip Enable
Chip Enable
Chip Enable Program Pin
Clock
Input
Active Low
W
Input
Active Low
E1
Input
Active Low
E2 & E3
EP2 & EP3
CK
Input
Programmable Active High or Low
To be tied directly to V , V
or V
SS
Mode Input
Input
DD DDQ
Active High
CQ, CQ
DQ
Echo Clock
Output
Input/Output
Three State - Deselect via E2 or E3 False
Data I/O
Three State
Active High
MCH
MCL
Must Connect High
Must Connect Low
Input
Input
To be tied directly to V or V
DD
DDQ
Active Low
To be tied directly to V
SS
Low = Low Impedance [High Drive]
High = High Impedance [Low Drive]
ZQ
Output Impedance Control
Mode Input
To be tied directly to V
or V
DDQ
SS
TCK
TDI
Test Clock
Test Data In
Input
Input
Output
Input
—
Active High
—
—
—
TDO
TMS
NC
Test Data Out
Test Mode Select
No Connect
Not connected to die or any other pin
V
Core Power Supply
Input
1.8 V Nominal
1.8 V Nominal
—
DD
V
Output Driver Power Supply
Ground
Input
Input
DDQ
V
SS
Operation Control
All address, data and control inputs (with the exception of EP2, EP3, ZQ, and the mode pins, L6, M6, and J6) are synchronized to
rising clock edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the
Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of
the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted
that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1–CQ2.
Rev: 1.04 4/2005
4/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
Read Operations
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2,
and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the
address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines
that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge
of clock the read data is allowed to propagate through the output register and onto the output pins.
Single Data Rate Pipelined Read
Read
Deselect
Read
Read
Read
CK
Address
ADV
/E1
A
XX
C
D
E
F
/W
DQ
QA
QC
QD
CQ
Key
Hi-Z
Access
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
Rev: 1.04 4/2005
5/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
Double Late Write
Double Late Write means that Data In is required on the third rising edge of clock. Double Late Write is used to implement
Pipeline mode NBT SRAMs.
SigmaRAM Double Late Write with Pipelined Read
Read
Write
Read
Write
Read
CK
Address
ADV
/E1
A
B
C
D
E
F
/W
DQ
QA
DB
QC
DD
CQ
Key
Hi-Z
Access
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle.
Example of x36 Byte Write Truth Table
Function
Read
W
H
L
Ba
X
Bb
X
Bc
X
Bd
X
Write Byte A
Write Byte B
Write Byte C
Write Byte D
Write all Bytes
Write Abort
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Rev: 1.04 4/2005
6/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
Two Byte Write Control Example with Double Late Write SigmaRAM
Write
Write
Write
Non-Write
Write
CK
Address
ADV
/E1
A
B
C
D
E
F
ADV
/BA
/BB
DA
DA
DB
DE
DQA0-DQA8
DC
DQB0-DQB8
CQ
Special Functions
Burst Cycles
Although SRAMs can sustain 100% bus bandwidth by eliminating the bus turnaround cycle in Double Late Write mode, burst read
or burst write cycles may also be performed. SRAMs provide an on-chip burst address generator that can be utilized, if desired, to
simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the
internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in
a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.
Rev: 1.04 4/2005
7/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
SigmaRAM Pipelined Burst Reads with Counter Wrap-around
Read
Continue
Continue
Continue
Continue
CK
External
Address
A2
A2
XX
A3
XX
A0
XX
A1
XX
A2
Internal
Address
Counter Wraps
ADV
/E1
/W
DQ
CQ
QA2
QA3
QA0
QA1
Rev: 1.04 4/2005
8/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
SigmaRAM Double Late Write SRAM Burst Writes with Counter Wrap-around
Write
Continue
Continue
Continue
Continue
CK
Address
A2
A2
XX
A3
XX
A0
XX
A1
XX
A2
XX
Internal
Address
ADV
/E1
Counter Wraps
/W
DQ
CQ
D2
D3
D0
D1
D2
Burst Order
The burst address counter wraps around to its initial state after four internal addresses (the loaded address and three more) have
been accessed. SigmaRAMs always count in linear burst order.
Linear Burst Order
A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Note:
The burst counter wraps to initial state on the 5th rising edge of clock.
Echo Clock
SRAMs feature Echo Clocks, CQ1, CQ2, CQ1, and CQ2 that track the performance of the output drivers. The Echo Clocks are
delayed copies of the main RAM clock, CK. Echo Clocks are designed to track changes in output driver delays due to variance in
die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. SigmaRAMs
provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1 and CQ2).
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
Rev: 1.04 4/2005
9/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
Programmable Enables
ΣRAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active
low or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at V
,
DD
E2 functions as an active high enable. If EP2 is held to V , E2 functions as an active low chip enable input.
SS
Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming
the enable inputs of four SRAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four
SRAMs can be made to look like one larger RAM to the system.
Example Four Bank Depth Expansion Schematic—Σ1x1Dp
A –A
0
n
E1
CK
W
DQ –DQ
0
n
Bank 0
Bank 3
Bank 1
Bank 2
A
A –A
A –A
A –A
A –A
0
n – 2
n – 1
0
n – 2
n – 1
0
n – 2
n – 1
0
n – 2
A
A
A
A
A
A
A
n – 1
E3
E2
E1
CK
E3
E2
E1
CK
E3
E3
A
A
A
A
n
n
n
n
E2
E2
E1
E1
CK
CK
EP3
EP2
1
0
EP3
EP2
1
1
EP3
EP2
0
0
EP3
0
1
W
W
W
W
DQ
CQ
DQ
CQ
DQ
CQ
DQ
CQ
EP2
CQ
Bank Enable Truth Table
EP2
EP3
E2
E3
Bank 0
V
V
V
Active Low
Active Low
Active High
Active High
Active Low
Active High
Active Low
Active High
SS
SS
DD
DD
SS
DD
Bank 1
Bank 2
Bank 3
V
V
V
V
SS
DD
V
Rev: 1.04 4/2005
10/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
Echo Clock Control in Two Banks of SigmaRAMs
Read
Read
Read
Read
Read
CK
Address
A
B
C
D
E
F
ADV
/E1
/E2 Bank 1
E2 Bank 2
DQ
Bank 1
QA
QC
CQ
Bank 1
CQ1 + CQ2
CQ
Bank 2
DQ
Bank 2
QB
QD
Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
In some applications it may be appropriate to pause between banks; to deselect both RAMs with E1 before resuming read
operations. An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle
in the bank. Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a write to Bank 2
would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed.
Rev: 1.04 4/2005
11/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
.
Pipelined Read Bank Switch with E1 Deselect
Read
No Op
Read
Read
Read
CK
Address
A
XX
C
D
E
F
ADV
/E1
/E2 Bank 1
E2 Bank 2
DQ
Bank 1
QA
CQ
Bank 1
CQ1 + CQ2
CQ
Bank 2
DQ
Bank 2
QC
QD
Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
CMOS Output Driver Impedance Control
CMOS I/O SigmaRAMs are supplied with selectable (high or low) impedance output drivers. The ZQ pin allows selection between
SRAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ high) point-to-point
applications.
Rev: 1.04 4/2005
12/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
Double Late Write, Pipelined Read Truth Table
E1
E
ADV W
B
DQ/CQ
DQ/CQ
(t
DQ/CQ
Previous
Operation
CK
Current Operation
(t ) (t ) (t ) (t ) (t )
(t )
)
(t
)
n
n
n
n
n
n
n+1
n+2
0→1
0→1
0→1
0→1
X
F
0
X
X
X
Bank Deselect
***/***
Hi-Z/Hi-Z
***/***
Hi-Z/Hi-Z
Hi-Z/Hi-Z
Hi-Z/CQ
Hi-Z/CQ
---
X
1
X
T
X
1
0
1
X
X
X
X
X
X
Bank Deselect Bank Deselect (Continue)
---
X
Deselect
---
X
Deselect
Deselect (Continue)
Hi-Z/CQ
---
Write
0→1
0→1
0→1
0
0
T
T
X
X
0
0
1
1
0
0
T
F
T
F
X
Loads new address
Stores DQx if Bx = 0
***/***
***/***
***/***
***/***
***/***
***/***
D1/CQ
Hi-Z/CQ
Dn/CQ
Write (Abort)
Loads new address
No data stored
X
Write Continue
Increments address by 1
Stores DQx if Bx = 0
X
X
X
X
Write
Write
Dn-1/CQ
Dn-1/CQ
Write Continue (Abort)
Increments address by 1
No data stored
0→1
0→1
Hi-Z/CQ
Read
Loads new address
0
T
X
0
1
1
X
X
X
***/***
Q1/CQ
Qn/CQ
---
---
Read Continue
Increments address by 1
0→1
X
X
Read
Qn-1/CQ
Notes:
1. If E2 = EP2 and E3 = EP3, then E = “T” else E = “F”.
2. If one or more Bx = 0, then B = “T” else B = “F”.
3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
4. “***” indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.
5. “---” indicates that the DQ input requirement / output state and CQ output state are determined by the next operation.
6. DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
7. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.
8. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces
of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial exter-
nal (base) address.
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GS8170DW36/72AC-350/333/300/250
Common I/O State Diagram
X,F,0,X or X,X,1,X
Bank
Deselect
0,T,0,1
0,T,0,0
1,T,0,X
X,F,0,X
Deselect
0,T,0,1
0,T,0,0
1,T,0,X or X,X,1,X
1,T,0,X
1,T,0,X
0,T,0,0
0,T,0,1
Read
Read
Write
X,F,0,X
X,F,0,X
0,T,0,1
0,T,0,1
X,X,1,X
X,X,1,X
0,T,0,0
0,T,0,0
1,T,0,X
X,F,0,X
0,T,0,0 0,T,0,1
1,T,0,X
X,F,0,X
Write
Continue
Continue
X,X,1,X
X,X,1,X
n
n+1
n+2
n+3
Key
Input Command Code
Clock (CK)
ƒ
Transition
Current State (n)
Next State (n + 1)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State & Next State Definition for Read/Write Control State Diagram
Notes:
1. The notation “X,X,X,X” controlling the state transitions above indicate the states of inputs E1, E, ADV, and W respectively.
2. If (E2 = EP2 and E3 = EP3) then E = “T” else E = “F”.
3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
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GS8170DW36/72AC-350/333/300/250
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
Voltage on V Pins
–0.5 to 2.5
V
V
DD
DD
V
Voltage in V
Pins
–0.5 to V
DDQ
DDQ
DD
V
–0.5 to V
+ 0.5 (≤ 2.5 V max.)
DDQ
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
V
I/O
V
–0.5 to V + 0.5 (≤ 2.5 V max.)
DDQ
V
IN
I
+/–100
+/–100
125
mA dc
mA dc
IN
I
OUT
o
T
Maximum Junction Temperature
Storage Temperature
C
J
T
–55 to 125
ºC
STG
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Supply Voltage
Symbol
Min.
1.7
Typ.
1.8
Max.
Unit
V
Notes
V
1.95
DD
V
V
1.8 V I/O Supply Voltage
1.7
1.8
V
DDQ
DD
Ambient Temperature
(Commercial Range Versions)
T
0
25
25
70
85
°C
°C
1
1
A
Ambient Temperature
(Industrial Range Versions)
T
–40
A
Note:
The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted
are evaluated for worst case in the temperature range marked on the device.
CMOS I/O DC Input Characteristics
Parameter
Symbol
Min.
Typ.
—
Max.
Unit
V
Notes
V
0.65 * V
V
+ 0.3
DDQ
CMOS Input High Voltage
CMOS Input Low Voltage
1
1
IH
DDQ
V
0.35 * V
DDQ
–0.3
—
V
IL
Note: For devices supplied with CMOS input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
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GS8170DW36/72AC-350/333/300/250
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 1.0 V
DD
V
SS
50%
50%
V
DD
V
– 1.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 1.8 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V
= 0 V
= 0 V
Input Capacitance
4
6
5
7
IN
IN
C
V
OUT
Output Capacitance
pF
OUT
Note:
This parameter is sample tested.
AC Test Conditions
Parameter
Conditions
V
Input high level
Input low level
DDQ
0 V
Max. input slew rate
Input reference level
Output reference level
2 V/ns
V
V
/2
/2
DDQ
DDQ
AC Test Load Diagram
DQ
RQ = 250 Ω (HSTL I/O)
50Ω
VT = V /2
DDQ
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GS8170DW36/72AC-350/333/300/250
Input and Output Leakage Characteristics
Parameter
Symbol
Test Conditions
Min.
Max
Notes
Input Leakage Current
(except mode pins)
I
V
= 0 to V
–2 uA
2 uA
—
IL
IN
DDQ
ZQ, MCH, MCL, EP2, EP3
Pin Input Current
I
V
= 0 to V
–50 uA
–2 uA
50 uA
2 uA
—
—
INM
IN
DDQ
Output Disable,
= 0 to V
I
Output Leakage Current
OL
V
OUT
DDQ
Selectable Impedance Output Driver DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min.
Max
—
Notes
V
I
= –4 mA
= 4 mA
= –8 mA
= 8 mA
V
V
– 0.4 V
DDQ
Low Drive Output High Voltage
Low Drive Output Low Voltage
High Drive Output High Voltage
High Drive Output Low Voltage
1
1
2
2
OHL
OHL
V
I
—
0.4 V
—
OLL
OLL
V
I
– 0.4 V
DDQ
OHH
OHH
V
I
—
0.4 V
OLH
OLH
Notes:
1. ZQ = 1; High Impedance output driver setting
2. ZQ = 0; Low Impedance output driver setting
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GS8170DW36/72AC-350/333/300/250
Operating Currents
-350
–40°C
-333
–40°C
-300
–40°C
-250
–40°C
0°C
to
0°C
to
0°C
to
0°C
to
Parameter
Symbol
Test Conditions
to
to
to
to
70°C
+85°C
70°C
+85°C
70°C
+85°C
70°C
+85°C
IDDP (PL)
IDDP (PL)
ISB1 (PL)
ISB1 (PL)
ISB2 (PL)
ISB2 (PL)
E1 ≤ VIL Max.
tKHKH ≥ tKHKH Min.
All other inputs
365 mA 375 mA 345 mA 355 mA 320 mA 330 mA 275 mA 285 mA
x72
Operating
Current
265 mA 275 mA 245 mA 255 mA 225 mA 235 mA 200 mA 210 mA
x36
VIL ≥ VIN ≥ VIH
E1 ≥ VIH Min. or
tKHKH ≥ tKHKH Min.
All other inputs
x72
80 mA
75 mA
80 mA
75 mA
90 mA
85 mA
90 mA
85 mA
75 mA
70 mA
75 mA
70 mA
85 mA
80 mA
85 mA
80 mA
70 mA
65 mA
70 mA
65 mA
80 mA
75 mA
80 mA
75 mA
65 mA
60 mA
65 mA
60 mA
75 mA
70 mA
75 mA
70 mA
Chip Disable
Current
x36
VIL ≥ VIN ≥ VIH
E2 or E3 False
tKHKH ≥ tKHKH Min.
All other inputs
x72
Bank Deselect
Current
x36
VIL ≥ VIN ≥ VIH
Device Deselected
All inputs
VSS + 0.10 V
CMOS
Deselect
Current
IDD3
45 mA
55 mA
45 mA
55 mA
45 mA
55 mA
45 mA
55 mA
≥ VIN
≥
VDD – 0.10 V
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GS8170DW36/72AC-350/333/300/250
AC Electrical Characteristics
-350
Min
-333
Min
-300
Min
-250
Min
Parameter
Symbol
Unit Notes
Max
—
Max
—
Max
—
Max
—
Clock Cycle Time
Clock High Time
tKHKH
tKHKL
2.86
1.0
1.0
0.5
—
3.0
1.2
1.2
0.5
—
3.3
1.3
1.3
0.5
4.0
1.6
1.6
0.5
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
2
—
—
—
—
Clock Low Time
tKLKH
—
—
—
—
Clock High to Echo Clock Low-Z
Clock High to Echo Clock High
Clock Low to Echo Clock Low
Clock High to Echo Clock High-Z
Clock High to Output Low-Z
Clock High to Output Valid
Clock High to Output Invalid
Clock High to Output High-Z
Echo Clock High to Output Valid
Echo Clock High to Output Invalid
Address Valid to Clock High
Clock High to Address Don’t Care
Enable Valid to Clock High
Clock High to Enable Don’t Care
Write Valid to Clock High
tKHCX1
tKHCH
tKLCL
—
—
—
—
1.7
1.7
1.7
—
1.8
1.8
1.8
—
1.8
1.8
1.8
—
2.1
2.1
2.1
—
—
—
—
—
tKHCZ
tKHQX1
tKHQV
tKHQX
tKHQZ
tCHQV
tCHQX
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tBVKH
tKHBX
tDVKH
tKHDX
tadvVKH
tKHadvX
—
—
—
1, 2
1
0.5
—
0.5
—
0.5
0.5
0.5
—
1.7
—
1.8
—
1.8
—
2.1
—
—
—
1
0.5
—
0.5
—
0.5
—
1.7
0.35
—
1.8
0.35
—
1.8
0.38
—
2.1
0.45
—
—
—
—
–0.38
0.7
0.4
0.7
0.4
0.7
0.4
0.7
0.4
0.5
0.4
0.7
0.4
—
2
–0.35
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
–0.35
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.5
0.4
0.6
0.4
–0.45
0.8
0.5
0.8
0.5
0.8
0.5
0.8
0.5
0.5
0.5
0.8
0.5
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Clock High to Write Don’t Care
Byte Write Valid to Clock High
Clock High to Byte Write Don’t Care
Data In Valid to Clock High
Clock High to Data In Don’t Care
ADV Valid to Clock High
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Clock High to ADV Don’t Care
Notes:
—
—
—
—
1. Measured at 100 mV from steady state. Not 100% tested.
2. Guaranteed by design. Not 100% tested.
3. For any specific temperature and voltage tKHCZ < tKHCX1.
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GS8170DW36/72AC-350/333/300/250
Timing Parameter Key—Pipelined Read Cycle Timing
tKHKH
tKHKL
CK
tKHAX
tKLKH
tAVKH
C
D
A
E
tKHQZ
tKHQX
tKHQV
tKHQX1
DQ (Data Out)
QB
tCHQX
tCHQV
tKHCH
tKHCX1
tCHCL
tCLCH
tKHCZ
CQ
= CQ High Z
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GS8170DW36/72AC-350/333/300/250
Timing Parameter Key—Double Late Write Mode Control and Data In Timing
CK
tKHAX
tAVKH
A
B
A
C
tnVKH
tKHnX
E1, E2, E3,
W, Bx, ADV
tDVKH
tKHDX
DQ (Data In)
DA
Note: tnVKH = tEVKH, tWVKH, tBVKH, etc. and tKHnX = tKHEX, tKHWX, tKHBX, etc.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DDQ
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
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GS8170DW36/72AC-350/333/300/250
JTAG Port Registers
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
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GS8170DW36/72AC-350/333/300/250
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
·
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1
0
·
· · ·
Control Signals
Test Access Port (TAP) Controller
TMS
TCK
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
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GS8170DW36/72AC-350/333/300/250
Tap Controller Instruction Set
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
I/O
Not Used
Configuration
ID Code
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
1
1
x72
x36
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
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GS8170DW36/72AC-350/333/300/250
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
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GS8170DW36/72AC-350/333/300/250
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
1
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
RFU
010
011
TDO.
1
1
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
100
101
110
111
1
1
1
1
GSI
RFU
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.04 4/2005
26/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
DQ
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
*
50Ω
30pF
Input slew rate
V
/2
V
V
/2
Input reference level
DDQ
DDQ
* Distributed Test Jig Capacitance
/2
Output reference level
DDQ
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
V
0.6 * V
V
+0.3
DD
Test Port Input High Voltage
V
V
1
1
IHJ
DD
V
0.3 * V
1
Test Port Input Low Voltage
–0.3
–300
–1
ILJ
DD
I
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
1.7
—
5, 6
5, 7
5, 8
5, 9
OHJ
V
—
0.4
—
V
OLJ
V
V
– 100 mV
DDQ
V
OHJC
V
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V
+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
ILJn
3. 0 V ≤ V ≤ V
IN
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V
supply.
DDQ
6.
7.
8.
9.
I
I
I
I
= –4 mA
OHJ
= + 4 mA
OLJ
= –100 uA
= +100 uA
OHJC
OHJC
Rev: 1.04 4/2005
27/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
TDI
tTH
tTS
tTH
tTS
TMS
TDO
tTKQ
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
50
—
Max
—
Unit
ns
TCK Cycle Time
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
ns
20
20
10
10
ns
—
ns
—
ns
tTH
—
ns
Rev: 1.04 4/2005
28/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
209 BGA Package Drawing (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
C A1
A
Side View
D
aaa
D1
e
Bottom View
∅b
e
Symbol
Min
—
Typ
—
Max
1.70
0.60
0.70
0.38
22.1
Units
mm
mm
mm
mm
mm
Symbol
Min
—
Typ
18.0 (BSC)
14.0
Max
—
Units
mm
mm
mm
mm
mm
A
A1
∅b
c
D1
E
0.40
0.50
0.31
21.9
0.50
0.60
0.36
22.0
13.9
—
14.1
—
E1
e
10.0 (BSC)
1.00 (BSC)
0.15
—
—
D
aaa
—
—
Rev 1.0
Rev: 1.04 4/2005
29/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
•
Ordering Information—GSI SigmaRAM
Speed
(MHz)
T
Org
Part Number
Type
I/O
A
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
256K x 72
256K x 72
256K x 72
GS8170DW36AC-350
GS8170DW36AC-333
GS8170DW36AC-300
GS8170DW36AC-250
GS8170DW36AC-350I
GS8170DW36AC-333I
GS8170DW36AC-300I
GS8170DW36AC-250I
GS8170DW72AC-350
GS8170DW72AC-333
GS8170DW72AC-300
GS8170DW72AC-250
GS8170DW72AC-350I
GS8170DW72AC-333I
GS8170DW72AC-300I
GS8170DW72AC-250I
GS8170DW36AGC-350
GS8170DW36AGC-333
GS8170DW36AGC-300
GS8170DW36AGC-250
GS8170DW36AGC-350I
GS8170DW36AGC-333I
GS8170DW36AGC-300I
GS8170DW36AGC-250I
GS8170DW72AGC-350
GS8170DW72AGC-333
GS8170DW72AGC-300
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double Late Write Σ1x1Dp ΣRAM
Double 5Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
350MHz
333 MHz
300 MHz
250 MHz
350 MHz
333 MHz
300 MHz
250 MHz
350MHz
333 MHz
300 MHz
250 MHz
350 MHz
333 MHz
300 MHz
250 MHz
350MHz
333 MHz
300 MHz
250 MHz
350 MHz
333 MHz
300 MHz
250 MHz
350MHz
333 MHz
300 MHz
C
C
C
C
I
I
I
I
C
C
C
C
I
I
I
I
C
C
C
C
I
I
I
I
C
C
C
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS817xx72C-300T.
2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
Rev: 1.04 4/2005
30/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
Ordering Information—GSI SigmaRAM
Speed
(MHz)
T
Org
Part Number
Type
I/O
A
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
GS8170DW72AGC-250
GS8170DW72AGC-350I
GS8170DW72AGC-333I
GS8170DW72AGC-300I
GS8170DW72AGC-250I
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
Pb-Free Double Late Write Σ1x1Dp ΣRAM
CMOS
CMOS
CMOS
CMOS
CMOS
250 MHz
350 MHz
333 MHz
300 MHz
250 MHz
C
I
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS817xx72C-300T.
2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
Rev: 1.04 4/2005
31/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DW36/72AC-350/333/300/250
18Mb Sync ΣRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
8170DWxxA_r1
• Updated 350 MHz AC specs
• Updated format
8170DWxxA_r1;
8170DWxxA_r1_01
8170DWxxA_r1_01;
8170DWxxA_r1_02
Format
Content
Content
• Removed Preliminary banner due to qualification of part
• Corrected JTAG information
8170DWxxA_r1_02;
8170DWxxA_r1_03
• Added Pb-Free information
8170DWxxA_r1_03;
8170DWxxA_r1_04
Rev: 1.04 4/2005
32/32
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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