GS8182D37BGD-375_技术文档

GS8182D19/37BD-435/400/375/333/300

435 MHz–300 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

18Mb SigmaQuad-II+

Burst of 4 SRAM

1.8 V V

DD

1.8 V and 1.5 V I/O

one element in a family of low power, low voltage HSTL I/O

SRAMs designed to operate at the speeds needed to implement

economical high performance networking systems.

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD)

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Clocking and Addressing Schemes

The GS8182D19/37D SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Each internal read and write operation in a SigmaQuad-II B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaQuad-II B4 RAM is always two address pins

less than the advertised index depth (e.g., the 2M x 8 has a

512K addressable index).

SigmaQuad™ Family Overview

The GS8182D19/37D are built in compliance with the

SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 18,874,368-bit (18Mb)

SRAMs. The GS8182D19/37D SigmaQuad SRAMs are just

Parameter Synopsis

-435

2.3 ns

0.45 ns

-400

-375

-333

3.3 ns

0.45 ns

-300

3.0 ns

0.45 ns

tKHKH

tKHQV

2.5 ns

2.67 ns

0.45 ns

Rev: 1.03a 11/2011

1/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

512K x 36 SigmaQuad-II+ SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

NC/SA

(288Mb) (72 Mb)

NC/SA

(36Mb) (144Mb)

NC/SA

A

CQ

W

BW2

K

BW1

R

CQ

B

C

D

E

F

Q27

D27

D28

Q29

Q30

D30

Doff

D31

Q32

Q33

D33

D34

Q35

TDO

Q18

Q28

D20

D29

Q21

D22

D18

D19

Q19

Q20

D21

Q22

SA

BW3

SA

K

BW0

SA

D17

D16

Q16

Q15

D14

Q13

Q17

Q7

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

V

NC

V

SS

V

D15

D6

SS

DD

SS

DD

V

DDQ

V

Q14

D13

DDQ

G

H

J

V

REF

DDQ

Q31

D23

Q23

D24

D25

Q25

Q26

SA

D12

Q12

D11

D10

Q10

Q9

Q4

K

L

D32

Q24

Q34

D26

D35

TCK

V

D3

Q11

Q1

V

DDQ

SS

M

N

P

R

V

SS

V

SA

QVLD

NC

SA

V

D9

SA

D0

SA

TMS

2

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35

2. NC = Not connected

Rev: 1.03a 11/2011

2/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

1M x 18 SigmaQuad-II+ SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

NC/SA

(144 Mb) (36 Mb)

NC/SA

(288Mb)

NC/SA

(72 Mb)

A

CQ

W

BW1

K

R

SA

CQ

B

C

D

E

F

NC

Doff

NC

TDO

Q9

NC

D9

SA

NC

SA

K

BW0

SA

NC

Q7

NC

D6

NC

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

D10

Q10

Q11

D12

Q13

V

NC

V

SS

D11

NC

V

SS

DD

SS

DD

V

DDQ

Q12

D13

V

DDQ

G

H

J

V

REF

DDQ

NC

D14

Q14

D15

D16

Q16

Q17

SA

NC

Q4

D3

K

L

NC

Q15

NC

V

NC

SA

V

NC

Q1

DDQ

SS

M

N

P

R

V

SS

D17

NC

V

SA

QVLD

NC

SA

V

NC

D0

SA

TCK

TMS

2

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.

2. NC = Not connected

Rev: 1.03a 11/2011

3/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Pin Description Table

Symbol

Description

Synchronous Address Inputs

Synchronous Read

Type

Input

Comments

—

SA

R

Active Low

W

Synchronous Write

Active Low

x18/x36 only

BW0–BW3

Synchronous Byte Writes

Input

K

Input Clock

Input

Active High

K

Active Low

TMS

TDI

TCK

TDO

V_REF

Test Mode Select

Input

—

Test Data Input

Input

Test Clock Input

Input

Test Data Output

Output

Input

HSTL Input Reference Voltage

Output Impedance Matching Input

Synchronous Data Outputs

Synchronous Data Inputs

Disable DLL when low

Output Echo Clock

ZQ

Qn

Dn

Input

Output

Input

Active Low

D

off

CQ

Output

Supply

—

Output Echo Clock

V_DD

Power Supply

1.8 V Nominal

V_DDQ

V_SS

Isolated Output Buffer Supply

Supply

1.5 or 1.8 V Nominal

Power Supply: Ground

Q Valid Output

Supply

Output

—

QVLD

NC

No Connect

Notes:

1. NC = Not Connected to die or any other pin

2. When ZQ pin is directly connected to V , output impedance is set to minimum value and it cannot be connected to ground or left

DDQ

unconnected.

3. K, K cannot be set to V

voltage

REF

Rev: 1.03a 11/2011

4/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O

SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from

Separate I/O SRAMs can cut the RAM’s bandwidth in half.

SigmaQuad-II+ B4 SRAM DDR Read

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. .

Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.

SigmaQuad-II+ B4 SRAM DDR Write

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous

command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge

of K, and finally by the next rising edge of K. and by the rising edge of the K that follows.

Rev: 1.03a 11/2011

5/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Power-Up Sequence for SigmaQuad-II+ SRAMs

For compatibility across all vendors it is recommended that SigmaQuad-II+ SRAMs be powered-up in a specific sequence in order to avoid unde-

fined operations

Power-Up Sequence

1. Power-up and maintain Doff at low state.

1a. Apply V_DD

.

1b. Apply V_DDQ

.

1c. Apply V_REF(may also be applied at the same time as V_DDQ).

2. After voltages are within specification range, and clocks (K, K) are stablized, change Doff to high.

3. An additional 2048 clock cycles are required to lock the DLL after it has been enabled.

Note:

The DLL may be reset by driving the Doff pin low or by stopping the K clocks for at least 30ns. 2048 cycles of clean K clocks are

always required to re-lock the DLL after reset.

DLL Constraints

The DLL synchronizes to either K clock. These clocks should have low phase jitter (t_KCVar).

• The DLL cannot operate at a frequency lower than that specified by the t_KHKHmaximum specification for the desired operating clock

frequency.

• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or

failures during the initial stage.

Special Functions

Byte Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18

version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

Example x18 RAM Write Sequence using Byte Write Enables

Data In Sample Time

BW0

BW1

D0–D8

Data In

D9–D17

Don’t Care

Data In

Beat 1

Beat 2

Beat 3

Beat 4

0

1

0

1

0

Don’t Care

Data In

Don’t Care

Data In

Resulting Write Operation

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Written

Unchanged

Written

Unchanged

Written

Beat 1

Beat 2

Beat 3

Beat 4

Rev: 1.03a 11/2011

6/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

FLXDrive-II Output Driver Impedance Control

HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to

VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be

5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is

between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts

in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and

temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance

evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is

implemented with discrete binary weighted impedance steps.

Separate I/O SigmaQuad II+ B4 SRAM Truth Table

Current

Operation

A

R

W

D

Q

K

↑

(t_n)

K

↑

(t_n)

K

↑

(t_n)

K ↑

(t_n)

K ↑

(t_n+1½

K ↑

(t_n+2

K ↑

t(_n+2½

K ↑

(t_n+2)

K ↑

t(_n+2½

K ↑

t(_n+3½)

(t_n-1

)

(t_n+1

)

t(_n+3

)

Deselect

Write

X

V

1

X

1

0

X

0

1

X

1

Deselect

Write

X

D2

X

D3

X

—

D2

—

D2

—

D3

—

D3

—

Hi-Z

Q2

Hi-Z

Q3

—

Read

—

Deselect

Read

0

D0

X

D1

X

Hi-Z

Q0

Hi-Z

Q1

—

X

0

Read

Q2

—

Q3

—

Write

D0

D2

D1

D3

Q2

Q3

Write

X

Read

Q0

Q1

Q2

Q3

Notes:

1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”

2. “—” indicates that the input requirement or output state is determined by the next operation.

3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.

4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.

5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-

ceded by a Read command.

6. Users should not clock in metastable addresses.

Rev: 1.03a 11/2011

7/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Byte Write Clock Truth Table

BW

Current Operation

D

K ↑

(t_n+1½

K ↑

(t_n+2½

K ↑

(t_n)

K ↑

(t_n+1½

K ↑

(t_n+2½)

(t_n+1

)

(t_n+2

)

(t_n+1

)

(t_n+2

)

Write

T

F

T

F

T

F

T

F

D0

X

D2

X

D3

X

D4

X

Dx stored if BWn = 0 in all four data transfers

Write

T

F

T

F

Dx stored if BWn = 0 in 1st data transfer only

Write

D1

X

Dx stored if BWn = 0 in 2nd data transfer only

Write

X

D2

X

Dx stored if BWn = 0 in 3rd data transfer only

Write

X

D3

X

Dx stored if BWn = 0 in 4th data transfer only

Write Abort

F

X

No Dx stored in any of the four data transfers

Notes:

1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

2. If one or more BWn = 0, then BW = “T”, else BW = “F”.

Rev: 1.03a 11/2011

8/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

x36 Byte Write Enable (BWn) Truth Table

BW0

BW1

BW2

BW3

D0–D8

Don’t Care

Data In

D9–D17

Don’t Care

Data In

D18–D26

Don’t Care

Data In

D27–D35

Don’t Care

Data In

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

x18 Byte Write Enable (BWn) Truth Table

BW0

BW1

D0–D8

Don’t Care

Data In

D9–D17

Don’t Care

Data In

1

0

1

0

1

0

Don’t Care

Data In

Rev: 1.03a 11/2011

9/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

V_DD

Description

Value

–0.5 to 2.9

Unit

Voltage on V_DDPins

Voltage in V_DDQPins

Voltage in V_REFPins

V

V_DDQ

V_REF

V_I/O

–0.5 to V_DD

V

–0.5 to V_DDQ

–0.5 to V_DDQ+0.5 (≤ 2.9 V max.)

Voltage on I/O Pins

V

V_IN

Voltage on Other Input Pins

Input Current on Any Pin

V

I_IN

+/–100

125

mA dc

I_OUT

Output Current on Any I/O Pin

Maximum Junction Temperature

Storage Temperature

^oC

T_J

T_STG

–55 to 125

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect

reliability of this component.

Recommended Operating Conditions

Power Supplies

Parameter

Supply Voltage

Symbol

V_DD

Min.

1.7

Typ.

1.8

—

Max.

1.9

Unit

V

V_DDQ

V_REF

I/O Supply Voltage

Reference Voltage

1.4

1.9

V

0.68

—

0.95

V

Notes:

1. The power supplies need to be powered up simultaneously or in the following sequence: V , V , V , followed by signal inputs. The

DD DDQ REF

power down sequence must be the reverse. V

must not exceed V .

DD

DDQ

2. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of

Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated

for worst case in the temperature range marked on the device.

Operating Temperature

Parameter

Symbol

Min.

Typ.

Max.

Unit

Ambient Temperature

(Commercial Range Versions)

T_A

0

25

70

°C

Ambient Temperature

(Industrial Range Versions)

T_A

–40

25

85

°C

Rev: 1.03a 11/2011

10/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Thermal Impedance

Test PCB

Substrate

θ JA (C°/W)

Airflow = 0 m/s

θ JA (C°/W)

Airflow = 1 m/s

θ JA (C°/W)

Airflow = 2 m/s

θ JB (C°/W)

θ JC (C°/W)

Package

165 BGA

4-layer

19.1

15.9

14.9

7.2

2.3

Notes:

1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.

2. Please refer to JEDEC standard JESD51-6.

3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to

the PCB can result in cooling or heating of the RAM depending on PCB temperature.

HSTL I/O DC Input Characteristics

Parameter

Symbol

V_IH(dc)

V_IL(dc)

Min

Max

Units

Notes

1, 4

V_REF+ 0.1

V_DD+ 0.3

V_REF– 0.1

DC Input Logic High

V

–0.3

1, 3

DC Input Logic Low

Notes:

1. Compatible with both 1.8 V and 1.5 V I/O drivers

2. These are DC test criteria. DC design criteria is V

± 50 mV. The AC V /V levels are defined separately for measuring timing param-

REF

IH IL

eters.

3. V (Min)DC = –0.3 V, V (Min)AC = –1.5 V (pulse width ≤ 3 ns).

IL

4.

V

(Max)DC = V

+ 0.3 V, V (Max)AC = V

+ 0.85 V (pulse width ≤ 3 ns).

IH

DDQ

IH

DDQ

HSTL I/O AC Input Characteristics

Parameter

AC Input Logic High

Symbol

V_IH(ac)

V_IL(ac)

Min

Max

—

Units

mV

Notes

2, 3

1

V_REF+ 200

V_REF– 200

5% V_REF(DC)

AC Input Logic Low

—

mV

V

Peak to Peak AC Voltage

V_REF(ac)

mV

REF

Notes:

1. The peak to peak AC component superimposed on V

may not exceed 5% of the DC component of V

.

REF

2. To guarantee AC characteristics, V ,V , Trise, and Tfall of inputs and clocks must be within 10% of each other.

IH IL

3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.

Rev: 1.03a 11/2011

11/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKHKH

V

+ 1.0 V

DD

V

SS

50%

V

DD

V

– 1.0 V

SS

20% tKHKH

V

IL

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 1.8 V)

A

DD

Parameter

Symbol

C_IN

Test conditions

V_IN= 0 V

Typ.

Max.

Unit

pF

Input Capacitance

Output Capacitance

Clock Capacitance

4

6

5

7

6

C_OUT

C_CLK

V_OUT= 0 V

V_IN= 0 V

pF

Note:

This parameter is sample tested.

AC Test Conditions

Parameter

Input high level

Input low level

Conditions

1.25 V

0.25 V

Max. input slew rate

Input reference level

Output reference level

2 V/ns

0.75 V

V_DDQ/2

Note:

Test conditions as specified with output loading as shown unless otherwise noted.

AC Test Load Diagram

DQ

RQ = 250 Ω (HSTL I/O)

= 0.75 V

V

REF

50Ω

VT = V /2

DDQ

Rev: 1.03a 11/2011

12/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Input and Output Leakage Characteristics

Parameter

Symbol

Test Conditions

Min.

Max

Notes

Input Leakage Current

(except mode pins)

I_IL

V_IN= 0 to V_DD

–2 uA

2 uA

V_DD≥ V_IN≥ V_IL

0 V ≤ V_IN≤ V_IL

–2 uA

2 uA

I_INDOFF

Doff

Output Disable,

I_OL

Output Leakage Current

–2 uA

2 uA

V

_OUT= 0 to V_DDQ

Programmable Impedance HSTL Output Driver DC Electrical Characteristics

Parameter

Symbol

V_OH1

Min.

Max.

Units

Notes

V_DDQ/2 – 0.12

V_DDQ– 0.2

V_DDQ/2 + 0.12

V_DDQ

V

1, 3

2, 3

4, 5

4, 6

Output High Voltage

Output Low Voltage

Output High Voltage

V_OL1

V_OH2

V_OL2

Vss

0.2

Output Low Voltage

Notes:

1.

I

= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).

DDQ OH DDQ

OH

2.

I

= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).

OL

DDQ

OL

DDQ

3. Parameter tested with RQ = 250Ω and V

4. 0Ω ≤ RQ ≤ ∞Ω

= 1.5 V or 1.8 V

DDQ

5.

I

= –1.0 mA

OH

OL

6.

I

= 1.0 mA

Rev: 1.03a 11/2011

13/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D09/37BD-435/400/375/333/300

Rev: 1.03a 11/2011

14/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

AC Electrical Characteristics

-435

-400

-375

-333

-300

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Clock

t_KHKH

t_KVar

K, K Clock Cycle Time

2.3

—

8.4

0.2

—

2.5

—

8.4

0.2

—

2.67

—

8.4

0.2

—

3.0

—

8.4

0.2

—

3.3

—

8.4

0.2

—

ns

tKC Variable

4

t_KHKL

t_KLKH

t_KHKH

t_KLock

t_KReset

K, K Clock High Pulse Width

K, K Clock Low Pulse Width

K to K High

0.4

1.4

2048

30

ns

0.4

ns

1.00

2048

30

1.06

2048

30

1.13

2048

30

1.28

2048

30

ns

K to K High

ns

DLL Lock Time

cycle

ns

6

K Static to DLL reset

Output Times

t_KHQV

t_KHQX

t_KHCQV

t_KHCQX

K, K Clock High to Data Output Valid

—

–0.45

—

0.45

—

–0.45

—

0.45

—

0.45

—

0.45

—

0.45

—

ns

K, K Clock High to Data Output Hold

K, K Clock High to Echo Clock Valid

–0.45

—

–0.45

—

–0.45

—

0.45

K, K Clock High to Echo Clock Hold

–0.45

—

–0.45

—

–0.45

—

–0.45

—

–0.45

—

ns

t_CQHQV

t_CQHQX

t_QVLD

CQ, CQ High Output Valid

CQ, CQ High Output Hold

CQ, CQ High to QLVD

—

–0.2

-0.2

0.8

0.2

—

–0.2

-0.2

0.86

—

0.2

—

–0.2

-0.2

0.88

—

0.2

—

–0.2

-0.2

1.03

—

0.2

—

–0.2

-0.2

1.15

—

0.2

—

ns

7

t_CQHCQH

t_KHQZ

CQ Phase Distortion

—

0.45

—

0.45

—

0.45

—

0.45

—

0.45

—

ns

K Clock High to Data Output High-Z

—

5

t_KHQX1

K Clock High to Data Output Low-Z

Setup Times

–0.45

t_AVKH

t_IVKH

Address Input Setup Time

0.4

—

0.4

—

0.4

—

0.4

—

0.4

—

ns

1

2

Control Input Setup Time

(R, W)

Control Input Setup Time

(BWX) (NWX)

t_IVKH

0.28

—

0.28

—

0.28

—

0.28

—

0.28

—

ns

3

t_DVKH

Data Input Setup Time

Notes:

1. All Address inputs must meet the specified setup and hold times for all latching clock edges.

2. Control singles are R, W,

3. Control singles are BW0, BW1 and (BW2, BW3 for x36).

4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

5. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus conten-

tion because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX

parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and tempera-

tures.

6.

V

slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V and input clock are stable.

D

7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet

parameters reflect tester guard bands and test setup variations.

Rev: 1.03a 11/2011

15/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

AC Electrical Characteristics (Continued)

-435

-400

-375

-333

-300

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Hold Times

t_KHAX

t_KHIX

Address Input Hold Time

0.4

—

0.4

—

0.4

—

0.4

—

0.4

—

ns

1

2

Control Input Hold Time

(R, W)

Control Input Hold Time

(BWX) (NWX)

t_KHIX

0.28

—

0.28

—

0.28

—

0.28

—

0.28

—

ns

3

t_KHDX

Data Input Hold Time

Notes:

1. All Address inputs must meet the specified setup and hold times for all latching clock edges.

2. Control singles are R, W,

3. Control singles are BW0, BW1 and (BW2, BW3 for x36).

4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

5. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus conten-

tion because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX

parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and tempera-

tures.

6.

V

slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V and input clock are stable.

D

7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet

parameters reflect tester guard bands and test setup variations.

Rev: 1.03a 11/2011

16/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Read No-Op K-Based Timing Diagram

Read A0

Write NOOP

READ A1

WRITE NOOP

NOOP

K

nK

tKHAX

tAVKH

Addr

A0

A1

tKHIX

tIVKH

R

tKHIX

tIVKH

W

QVLD

tKHQV

tKHQX

tKHQV

Q0

tKHQX

Q0+2

tKHQX

Q1+1

tKHQX

Q1+3

Q

Q0+1

Q0+3

Q1

Q1+2

tKHCQH

t K HCQL

CQ

t K H CQ

tQVLD

H

tQVLD

tKH CQ

L

CQ

Rev: 1.03a 11/2011

17/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D09/37BD-435/400/375/333/300

Rev: 1.03a 11/2011

18/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output

DD

drivers are powered by V

.

DD

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

DD

SS

JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the

falling edge of TCK.

TCK

Test Clock

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state

machine. An undriven TMS input will produce the same result as a logic one input level.

TMS

TDI

Test Mode Select

Test Data In

In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed

between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP

In Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to

the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input

level.

Output that is active depending on the state of the TAP state machine. Output changes in response to the

falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.

TDO

Test Data Out

Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Rev: 1.03a 11/2011

19/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

·

Boundary Scan Register

·

0

Bypass Register

2

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1

0

·

· · ·

Control Signals

Test Access Port (TAP) Controller

TMS

TCK

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

GSI Technology

Not Used

JEDEC Vendor

ID Code

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

0

8

1

7

1

6

0

5

1

4

1

3

0

2

0

1

0

1

Bit #

X

0

Rev: 1.03a 11/2011

20/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

1

Run Test Idle

Select DR

Select IR

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This

occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-

tate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is

Rev: 1.03a 11/2011

21/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and

I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and

are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because

the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will

not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the

TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP

operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then

places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with

all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is

still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.

Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output

drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-

tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-

ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR

state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-

ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction

EXTEST

IDCODE

Code

000

Description

Notes

1

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

001

1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z

RFU

010

011

TDO.

1

Forces all RAM output drivers to High-Z except CQ.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

Rev: 1.03a 11/2011

22/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

JTAG TAP Instruction Set Summary

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

100

101

110

111

1

GSI

RFU

GSI private instruction.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

V_ILJ

Min.

–0.3

Max.

Unit Notes

0.3 * V_DD

V_DD+0.3

Test Port Input Low Voltage

V

1

V_IHJ

0.6 * V_DD

Test Port Input High Voltage

I_INHJ

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

Test Port Output CMOS High

Test Port Output CMOS Low

–300

1

100

1

uA

V

2

I_INLJ

–1

3

I_OLJ

4

V_OHJ

V_OLJ

V_OHJC

V_OLJC

V_DD– 200 mV

—

5, 6

5, 7

5, 8

5, 9

—

0.4

V

V_DD– 100 mV

—

V

—

100 mV

V

Notes:

1. Input Under/overshoot voltage must be –1 V < Vi < V

+1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

2.

V

≤ V ≤ V

ILJ

IN

DDn

3. 0 V ≤ V ≤ V

IN

ILJn

4. Output Disable, V

= 0 to V

DDn

OUT

5. The TDO output driver is served by the V supply.

DD

6.

7.

8.

9.

I

= –2 mA

OHJ

= + 2 mA

OLJ

= –100 uA

= +100 uA

OHJC

OLJC

Rev: 1.03a 11/2011

23/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

JTAG Port AC Test Conditions

Parameter

Input high level

Input low level

Conditions

JTAG Port AC Test Load

V_DD– 0.2 V

TDO

0.2 V

1 V/ns

V_DD/2

*

Input slew rate

50Ω

30pF

Input reference level

V

/2

DD

V_DD/2

Output reference level

* Distributed Test Jig Capacitance

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

JTAG Port Timing Diagram

tTKC

tTKH

tTKL

TCK

tTH

tTS

TDI

tTH

tTS

TMS

tTKQ

TDO

tTH

tTS

Parallel SRAM input

JTAG Port AC Electrical Characteristics

Parameter

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

50

—

Max

—

Unit

ns

TCK Cycle Time

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

20

—

ns

20

10

ns

—

ns

—

ns

tTH

—

ns

Rev: 1.03a 11/2011

24/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Package Dimensions—165-Bump FPBGA (Package D)

A1 CORNER

TOP VIEW

BOTTOM VIEW

A1 CORNER

M

Ø0.10

C

Ø0.25 C A B

Ø0.40~0.60 (165x)

1

2 3 4 5 6 7 8 9 10 11

11 10 9 8

7 6 5 4 3 2 1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

M

N

P

R

A

1.0

10.0

1.0

13±0.05

B

0.20(4x)

SEATING PLANE

C

Rev: 1.03a 11/2011

25/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Ordering Information–GSI SigmaQuad-II+ SRAM

2

Org

Part Number1

Type

Package

Speed (MHz)

T

A

1M x 18

GS8182D19BD-435

GS8182D19BD-400

GS8182D19BD-375

GS8182D19BD-333

GS8182D19BD-300

GS8182D19BD-435I

GS8182D19BD-400I

GS8182D19BD-375I

GS8182D19BD-333I

GS8182D19BD-300I

GS8182D19BGD-435

GS8182D19BGD-400

GS8182D19BGD-375

GS8182D19BGD-333

GS8182D19BGD-300

GS8182D19BGD-435I

GS8182D19BGD-400I

GS8182D19BGD-375I

GS8182D19BGD-333I

GS8182D19BGD-300I

GS8182D37BD-435

GS8182D37BD-400

GS8182D37BD-375

GS8182D37BD-333

GS8182D37BD-300

GS8182D37BD-435I

GS8182D37BD-400I

GS8182D37BD-375I

GS8182D37BD-333I

GS8182D37BD-300I

GS8182D37BGD-435

GS8182D37BGD-400

SigmaQuad II+ SRAM

Sigma Quad II+ SRAM

SigmaQuad II+ SRAM

165-bump BGA

435

400

375

333

300

435

400

375

333

300

435

400

375

333

300

435

400

375

333

300

435

400

375

333

300

435

400

375

333

300

435

400

C

I

1M x 18

165-bump BGA

1M x 18

165-bump BGA

1M x 18

165-bump BGA

1M x 18

165-bump BGA

1M x 18

165-bump BGA

I

1M x 18

165-bump BGA

I

1M x 18

165-bump BGA

I

1M x 18

165-bump BGA

I

1M x 18

RoHS-compliant 165-bump BGA

165-bump BGA

C

I

1M x 18

I

1M x 18

I

1M x 18

I

1M x 18

I

512K x 36

Notes:

C

I

165-bump BGA

I

165-bump BGA

I

165-bump BGA

I

165-bump BGA

I

RoHS-compliant 165-bump BGA

C

1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8182D37BD-300T.

2. C = Commercial Temperature Range. I = Industrial Temperature Range.

Rev: 1.03a 11/2011

26/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182D19/37BD-435/400/375/333/300

Ordering Information–GSI SigmaQuad-II+ SRAM

2

Org

Part Number1

Type

Package

Speed (MHz)

T

A

512K x 36

Notes:

GS8182D37BGD-375

GS8182D37BGD-333

GS8182D37BGD-300

GS8182D37BGD-435I

GS8182D37BGD-400I

GS8182D37BGD-375I

GS8182D37BGD-333I

GS8182D37BGD-300I

SigmaQuad II+ SRAM

RoHS-compliant 165-bump BGA

375

333

300

435

400

375

333

300

C

I

1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8182D37BD-300T.

2. C = Commercial Temperature Range. I = Industrial Temperature Range.

SigmaQuad-II+ SRAM Revision History

File Name

Format/Content

Description of changes

Creation of datasheet

8182DxxBD_r1

(Rev1.00a: Removed extra pages)

8182DxxBD_r1_01

8182DxxBD_r1_02

Content

Added 450 and 435 MHz speed bins

Removed Preliminary banner due to MP status

Removed 450 MHz speed bin due to lack of orders

(Rev1.03a: Editorial updates)

8182DxxBD_r1_03

Content

Rev: 1.03a 11/2011

27/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS8182D37BGD-375
厂家：	GSI TECHNOLOGY
描述：	18Mb SigmaQuad-II Burst of 4 SRAM 静态存储器
文件：	总27页 (文件大小：554K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS8182D37BGD-375 [GSI]

相关型号：

GS8182D37BGD-375I

GS8182D37BGD-435I

GS8182D37BGD-435IT

GS8182D37BGD-450

GS8182D37BGD-450I

GS8182D37BGD-450IT

GS8182Q08BD-133

GS8182Q08BD-167I

GS8182Q08BD-167T

GS8182Q08BD-200

GS8182Q08BD-200I

GS8182Q08BD-250T