GS82032Q-138I [GSI]
Cache SRAM, 64KX32, 9.7ns, CMOS, PQFP100, QFP-100;
| 型号： | GS82032Q-138I |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Cache SRAM, 64KX32, 9.7ns, CMOS, PQFP100, QFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总23页 (文件大小：760K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS82032T/Q-150/138/133/117/100/66
150 MHz–66 MHz
9 ns–18 ns
TQFP, QFP
Commercial Temp
Industrial Temp
64K x 32
2M Synchronous Burst SRAM
Flow Through/Pipeline Reads
3.3 V V
DD
3.3 V and 2.5 V I/O
Features
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (Pin 14 in the TQFP, Bump
1F in the FP-BGA). Holding the FT mode pin/bump low,
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered
Data Output Register.
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
SCD Pipelined Reads
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP or QFP package
The GS82032 is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
Byte Write and Global Write
-150 -138 -133 -117 -100 -66 Unit
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Pipeline tCycle 6.6 7.25 7.5 8.5
10 12.5 ns
ns
270 245 240 210 180 150 mA
3-1-1-1
tKQ
IDD
3.8
4
4
4.5
5
6
Flow tCycle 10.5 15
Through tKQ 9.7
2-1-1-1
15
10
15
11
15
12
20
18
ns
ns
9
Sleep Mode
IDD
170 120 120 120 120 95
mA
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Functional Description
Applications
The GS82032 is a 2,097,152-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications
ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS82032 operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- and 2.5 V-compatible. Separate output
power (VDDQ) pins are used to decouple output noise from the
internal circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Rev: 1.04 2/2001
1/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Preliminary
GS82032T/Q-150/138/133/117/100/66
GS82032 100-Pin TQFP and QFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
DQC8
DQC7
VDDQ
2
3
4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
NC
VSS
DQD1
DQD2
VDDQ
5
6
7
8
9
64K x 32
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.04 2/2001
2/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
TQFP Pin Description
Pin Location
Symbol
Type
Description
37, 36
A0, A1
I
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49
A2–A15
I
Address Inputs
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8
I/O
Data Input and Output pins
18, 19, 22, 23, 24, 25, 28, 29
16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30
NC
BW
No Connect
87
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Byte Write Enable for DQC, DQD Data I/Os; active low
Clock Input Signal; active high
93, 94
BA, BB
BC, BD
CK
95, 96
89
88
GW
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
98, 92
E1, E3
E2
97
Chip Enable; active high
86
G
Output Enable; active low
83
ADV
ADSP, ADSC
ZZ
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
84, 85
64
14
31
FT
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
LBO
VDD
15, 41, 65, 91
VSS
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
I
I
I/O and Core Ground
VDDQ
Output driver power supply
Rev: 1.04 2/2001
3/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
GS82032 Block Diagram
Register
A0–An
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
32
32
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E2
E3
D
Q
Register
D
Q
FT
G
1
Power Down
Control
DQx1–DQx8
ZZ
Rev: 1.04 2/2001
4/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Mode Pin Functions
Mode Name
Pin
Name
State
Function
L
Linear Burst
Burst Order Control
LBO
H or NC
L
Interleaved Burst
Flow Through
Pipeline
Output Register Control
FT
H or NC
L or NC
H
Active
Power Down Control
ZZ
Standby, IDD = ISB
Note:
There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
B
A
B
B
B
C
B
D
Notes
1
X
H
L
X
H
H
L
X
H
H
H
L
X
H
H
H
H
L
Read
H
1
Write byte A
Write byte B
Write byte C
Write byte D
Write all bytes
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Rev: 1.04 2/2001
5/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Synchronous Truth Table
Operation
State
Address
Used
2
3
4
Diagram
E1
ADSP ADSC ADV
E
W
DQ
5
Key
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
None
None
X
X
H
L
X
X
L
L
X
L
X
X
X
X
X
X
L
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
F
F
T
T
T
X
X
X
X
X
X
X
X
High-Z
None
X
L
L
H
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
R
L
L
X
H
X
H
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
1. X = Don’t Care, H = High, L = Low.
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.04 2/2001
6/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CR
CW
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW, and GW) control
inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.04 2/2001
7/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CR
CW
CW
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.04 2/2001
8/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Absolute Maximum Ratings
(All voltages reference to VSS
)
Symbol
VDD
Description
Value
–0.5 to 4.6
–0.5 to VDD
–0.5 to 6
Unit
Voltage on VDD Pins
V
V
V
VDDQ
VCK
Voltage in VDDQ Pins
Voltage on Clock Input Pin
Voltage on I/O Pins
VI/O
–0.5 to VDDQ+0.5 (£ 4.6 V max.)
V
V
VIN
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
–0.5 to VDD+0.5 (£ 4.6 V max.)
IIN
+/–20
+/–20
mA
mA
W
IOUT
PD
TSTG
TBIAS
1.5
oC
oC
–55 to 125
–55 to 125
Temperature Under Bias
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be
restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings,
for an extended period of time, may affect reliability of this component.
Recommended Operating Conditions
Parameter
Symbol
VDD
VDDQ
VIH
Min.
Typ.
Max.
Unit
Notes
Supply Voltage
3.135
2.375
1.7
3.3
2.5
—
3.6
VDD
V
V
I/O Supply Voltage
Input High Voltage
Input Low Voltage
1
2
2
3
3
VDD +0.3
V
VIL
–0.3
0
—
0.8
70
85
V
TA
Ambient Temperature (Commercial Range Versions)
25
25
°C
°C
TA
Ambient Temperature (Industrial Range Versions)
–40
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V £ VDDQ £ 2.375 V (i.e., 2.5 V I/O)
and 3.6 V £ VDDQ £ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < VDD+2 V with a pulse width not to exceed 20% tKC.
Rev: 1.04 2/2001
9/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD+-2.0V
VSS
50%
VDD
50%
VSS-2.0V
20% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Symbol
Test conditions
VDD = 3.3 V
VIN = 0 V
Typ.
Max.
Unit
CI
Control Input Capacitance
Input Capacitance
3
4
6
4
5
7
pF
pF
pF
CIN
COUT
VOUT = 0 V
Output Capacitance
Note: This parameter is sample tested.
Package Thermal Characteristics
Rating
Layer Board
Symbol
RQJA
TQFP Max
QFP Max
Unit
Notes
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
single
four
40
24
9
TBD
TBD
TBD
°C/W
°C/W
°C/W
1,2,4
1,2,4
3,4
RQJA
RQJC
Junction to Case (TOP)
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient.
Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
4. For x18 configuration, consult factory.
Rev: 1.04 2/2001
10/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
AC Test Conditions
Parameter
Conditions
Input high level
Input low level
2. 3V
0.2 V
Input slew rate
1 V/ns
1.25 V
1.25 V
Fig. 1& 2
Input reference level
Output reference level
Output load
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ
.
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225W
225W
DQ
30pF*
50W
VT = 1.25 V
5pF*
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
VDD ³ VIN ³ VIH
0 V £ VIN £ VIH
–1 uA
–1 uA
1 uA
300 uA
IINZZ
ZZ Input Current
VDD ³ VIN ³ VIL
0 V £ VIN £ VIL
–300 uA
–1 uA
1 uA
1 uA
IINM
IOL
Mode Pin Input Current
Output Leakage Current
Output Disable,
VOUT = 0 to VDD
–1 uA
1 uA
VOH
VOH
VOL
IOH = –4 mA, VDDQ = 2.375 V
IOH = –4 mA, VDDQ = 3.135 V
IOL = 4 mA
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
0.4 V
Rev: 1.04 2/2001
11/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Rev: 1.04 2/2001
12/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
AC Electrical Characteristics
-150
-138
-133
-117
-100
-66
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock Cycle Time
tKC
tKQ
6.6
—
—
3.8
—
—
—
9.0
—
—
—
—
7.25
—
2
—
4
7.5
—
2
—
4
8.5
—
2
—
4.5
—
—
—
11
—
—
—
—
4
10
—
2
—
5
12.5
—
2
—
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pipeline
tKQX
1.5
1.5
10.5
—
—
—
—
9.7
—
—
—
—
4
—
—
—
10
—
—
—
—
4
—
—
—
12
—
—
—
—
5
—
—
—
18
—
—
—
—
6
tLZ1
tKC
2
2
2
2
2
15
—
3
15
—
3
15
—
3
15
—
3
20
—
3
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKQ
Flow
Through
tKQX
3
tLZ1
tKH
tKL
3
3
3
3
3
3
1.8
1.8
1.9
1.9
1.9
1.9
1.5
—
0
2
3
4
Clock LOW Time
2
3
4
tHZ1
tOE
Clock to Output in High-Z
G to Output Valid
1.5 3.8 1.5
1.5
—
0
—
—
0
—
—
0
—
0
3.8
—
—
0
4
4
4
5
6
tOLZ1
G to output in Low-Z
—
—
—
—
—
tOHZ1
tS
G to output in High-Z
Setup time
—
1.7
0.5
5
4
—
2
4
—
2
4
—
2
4
—
2
5
—
2
6
ns
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Hold time
tH
0.5
5
0.5
5
0.5
5
0.5
5
0.5
5
tZZS2
ZZ setup time
tZZH2
tZZR
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
20
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.04 2/2001
13/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Write Cycle Timing
Single Write
Burst Write
Deselected
Write
CK
tH
tS
ADSP is blocked by E1 inactive
tKC
tKL
tKH
ADSP
tS tH
ADSC initiated write
ADSC
tH
tS
ADV
ADV must be inactive for ADSP Write
tH
tS
WR2
WR3
WR1
A0–An
tS tH
GW
BW
tH
tS
tS
tH
WR3
WR1
WR2
BA–BD
tS
tH
tH
E1 masks ADSP
E1
tS
Deselected with E2
E2
tS tH
E2 and E3 only sampled with ADSP or ADSC
E3
G
tS
Write specified byte for 2A and all bytes for 2B, 2C& 2D
tH
Hi-Z
D2C
D2D
D3A
DQA–DQD
D1A
D2A
D2B
Rev: 1.04 2/2001
14/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tS
tKH
tH
ADSP is blocked by E1 inactive
tKC
ADSP
ADSC
ADV
tS tH
ADSC initiated read
tH
tS
Suspend Burst
Suspend Burst
tS
tH
RD1
RD2
RD3
A0–An
GW
tS
tS
tH
tH
BW
BA–BD
E1
tH
tS
E1 masks ADSP
tS tH
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
tS
tH
E3
G
tOHZ
tOE
tKQX
tKQX
tOLZ
Q2B
Q2C
Q3A
Q1A
Q2A
Q2D
DQA–DQD
Hi-Z
tLZ
tHZ
tKQ
Rev: 1.04 2/2001
15/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Flow Through Read-Write Cycle Timing
Single Write
Burst Read
Single Read
CK
tS tH
tKC
ADSP is blocked by E inactive
ADSC initiated read
tKH tKL
ADSP
ADSC
tS tH
tS tH
ADV
tS
tH
RD2
RD1
WR1
A0–An
tS
tS
tH
GW
tH
BW
tS
tH
BA–BD
WR1
tS
tS
tS
tH
E1 masks ADSP
E1
tH
tH
E2 and E3 only sampled with ADSP and ADSC
E2
E3
Deselected with E3
tOHZ
tOE
G
tS
tH
tKQ
Hi-Z
DQA–DQD
Q1A
D1A
Q2A
Q2A
Q2B
Q2C
Q2D
Burst wrap around to its initial state
Rev: 1.04 2/2001
16/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Pipelined SCD Read Cycle Timing
Single Read
Burst Read
tKC
CK
tKL
tKH
tH
tH
tS
ADSP is blocked by E1 inactive
ADSP
ADSC
tS
ADSC initiated read
tS tH
Suspend Burst
ADV
tH
tS
RD2
RD3
RD1
An
GW
BW
tS
tS
tH
tH
BWA–BWD
E1
tH
tS
E1 masks ADSP
tS tH
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
E3
tS
tH
tOE
G
tOHZ
tKQX
tKQX
tOLZ
tLZ
Hi-Z
DQA–DQD
Q1A
Q2A
Q2B
Q3A
tHZ
Q2D
Q2C
tKQ
Rev: 1.04 2/2001
17/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Pipelined SCD Read-Write Cycle Timing
Single Write
Single Read
Burst Read
tKL
CK
tH
tS
tKH
tKC
ADSP is blocked by E inactive
ADSC initiated read
ADSP
ADSC
tS tH
tS tH
ADV
tS
tH
RD2
RD1
WR1
A0–An
tS
tS
tH
GW
tH
BW
tH
tS
WR1
BA–BWD
tS
tH
E1 masks ADSP
E1
tS tH
E2 and E3 only sampled with ADSP and ADSC
E2
E3
tH
tS
Deselected with E3
tOE
tOHZ
G
tS
tH
tKQ
Hi-Z
Q1A
D1A
Q2A
Q2B
Q2C
DQa–DQd
Q2D
Rev: 1.04 2/2001
18/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Sleep Mode Timing Diagram
CK
tH
tS
tKC
tKL
tKH
ADSP
ADSC
ZZ
tZZH
tZZS
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles, and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 1.04 2/2001
19/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
GS 82032 Output Driver Characteristics
60
Pull Down Drivers
40
20
VDDQ
I Out
0
VOut
VSS
-20
-40
Pull Up Drivers
-60
-80
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD LD
3.3V PD LD
3.1V PD LD
3.1V PU LD
3.3V PU LD
3.6V PU LD
Rev: 1.04 2/2001
20/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
TQFP and QFP Package Drawing
q
L
c
L1
e
b
A1
A2
E1
E
TQFP
QFP
Symbol
Description
Min. Nom. Max Min. Nom. Max
A1
Standoff
Body Thickness
Lead Width
0.05
1.35
0.20
0.09
21.9
19.9
15.9
13.9
—
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
0.25
2.55
0.20
0.10
22.95
19.9
17.0
13.9
—
0.35
2.72
0.30
0.15
23.2
20.0
17.2
14.0
0.65
0.80
1.60
—
0.45
2.90
0.40
0.20
23.45
20.1
17.4
14.1
—
A2
b
c
Lead Thickness
Terminal Dimension
Package Body
Terminal Dimension
Package Body
Lead Pitch
D
22.0
20.0
16.0
14.0
0.65
0.60
1.00
—
D1
E
E1
e
L
Foot Length
0.45
—
0.75
.60
1.00
—
L1
Lead Length
—
Y
q
Coplanarity
—
0.10
—
0.10
7°
Lead Angle
0°
—
7°
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion
Rev: 1.04 2/2001
21/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Ordering Information
2
T
3
Speed
A
1
Org
Type
Package
Status
Part Number
(MHz/ns)
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
64K x 32
Notes:
GS82032T-150
GS820322T-138
GS82032T-133
GS82032T-4
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
QFP
150/9
138/9.7
133/10
133/10
100/12
66/18
C
C
C
C
C
C
I
GS82032T-5
GS82032T-6
GS82032T-150I
GS82032T-138I
GS82032T-133I
GS82032T-4I
GS82032T-5I
GS82032T-6I
GS82032Q-150
GS82032Q-138
GS82032Q-133
GS82032Q-4
150/9
Not Available
138/9.7
133/10
133/10
100/12
66/18
I
I
I
I
I
150/9
C
C
C
C
C
C
I
QFP
138/9.7
133/10
133/10
100/12
66/18
QFP
QFP
GS82032Q-5
QFP
GS82032Q-6
QFP
GS82032Q-150I
GS82032Q-138I
GS82032Q-133I
GS82032Q-4I
GS82032Q-5I
GS82032Q-6I
QFP
150/9
Not Available
QFP
138/9.7
133/10
133/10
100/12
66/18
I
QFP
I
QFP
I
QFP
I
QFP
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS82032T-100IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site(www.gsitechnology.com)for a complete listing of current offerings.
Rev: 1.04 2/2001
22/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Revisions
New
• This was the first release of 2 Meg Burst Datasheets in the
new format. They included information for the Fine Pitch BGA
package.
GSGS82032 Rev 1.00 9/
Format
1999A
• Took out the Fine Pitch BGA information.
GSGS82032 Rev 1.00 9/
1999A; 1.01 11/1999B
Content
• Ordering information. Changed 128K x 32 to 64K x 32; Typo
• Ordering information. Changed “0” to go before “H” or “E” in
part number.
GSGS82032 Rev 1.01 11/
Content
1999B; 1.02 1/2000C
• Ordering information. Changed - 117 to -4, -100 to -5. and -66
to -6.
• New GSI Logo
• Switched TKQ with TCycle in Flow Through part of table on
page 1.
GS820321.02 1/
2000C;820321.03 2/2000D
Format/Content
Format/Content
• Updated format to comply with Technical Publication
Standards
• Changed all -4 references in ordering information table on
page 22 from 117/11 to 133/10.
820321.03 2/2000D;
82032_r1_04
Rev: 1.04 2/2001
23/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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