GS8322Z18E-166IV
更新时间:2024-09-18 07:15:53
品牌:GSI
描述:36Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8322Z18E-166IV 概述
36Mb Pipelined and Flow Through Synchronous NBT SRAM 36MB流水线和流量通过同步NBT SRAM SRAM
GS8322Z18E-166IV 规格参数
是否无铅: | 含铅 | 是否Rohs认证: | 不符合 |
生命周期: | Obsolete | 零件包装代码: | BGA |
包装说明: | 15 X 17 MM, 1 MM PITCH, FPBGA-165 | 针数: | 165 |
Reach Compliance Code: | compliant | ECCN代码: | 3A991.B.2.B |
HTS代码: | 8542.32.00.41 | 风险等级: | 5.68 |
最长访问时间: | 8 ns | 其他特性: | FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY |
JESD-30 代码: | R-PBGA-B165 | 长度: | 17 mm |
内存密度: | 37748736 bit | 内存集成电路类型: | ZBT SRAM |
内存宽度: | 18 | 功能数量: | 1 |
端子数量: | 165 | 字数: | 2097152 words |
字数代码: | 2000000 | 工作模式: | SYNCHRONOUS |
最高工作温度: | 85 °C | 最低工作温度: | -40 °C |
组织: | 2MX18 | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | LBGA | 封装形状: | RECTANGULAR |
封装形式: | GRID ARRAY, LOW PROFILE | 并行/串行: | PARALLEL |
峰值回流温度(摄氏度): | NOT SPECIFIED | 认证状态: | Not Qualified |
座面最大高度: | 1.5 mm | 最大供电电压 (Vsup): | 2 V |
最小供电电压 (Vsup): | 1.7 V | 标称供电电压 (Vsup): | 1.8 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | INDUSTRIAL | 端子形式: | BALL |
端子节距: | 1 mm | 端子位置: | BOTTOM |
处于峰值回流温度下的最长时间: | NOT SPECIFIED | 宽度: | 15 mm |
Base Number Matches: | 1 |
GS8322Z18E-166IV 数据手册
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PDF下载GS8322Z18/36/72(B/E/C)-xxxV
250 MHz–133 MHz
119, 165 & 209 BGA
Commercial Temp
Industrial Temp
36Mb Pipelined and Flow Through
Synchronous NBT SRAM
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Features
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-, 165- or 209-Bump BGA package
• RoHS-compliant packages available
The GS8322Z18/36/72-xxxV may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
Functional Description
The GS8322Z18/36/72-xxxV is a 36Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
The GS8322Z18/36/72-xxxV is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump, 165-bump or 209-bump BGA package.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
t
3.0 3.0 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
KQ
tCycle
Pipeline
3-1-1-1
Curr (x18)
Curr (x36)
Curr (x72)
275 255 240 215 205 180 mA
330 300 280 245 230 205 mA
415 385 340 305 285 255 mA
t
6.5 7.0 7.5 8.0 8.5 8.5 ns
6.5 7.0 7.5 8.0 8.5 8.5 ns
KQ
Flow
tCycle
Through
2-1-1-1
Curr (x18)
Curr (x36)
Curr (x72)
200 190 180 170 160 150 mA
225 215 205 195 185 170 mA
300 280 255 245 230 225 mA
Rev: 1.05 6/2006
1/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
GS8322Z72C-xxxV Pad Out—209-Bump BGA—Top View (Package C)
1
2
3
4
5
6
ADV
W
7
A
8
9
10
11
A
B
C
D
DQG
DQG
DQG
DQG
DQG
DQG
DQG
DQG
A
E2
BG
BD
NC
A
E3
BB
BE
NC
A
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
A
B
C
D
BC
BH
NC
NC
NC
A
BF
BA
E1
G
NC
NC
V
V
SS
SS
V
V
V
V
V
V
V
V
V
V
V
E
F
DQPG
DQC
DQC
DQC
DQC
NC
DQPC
DQC
DQC
DQC
DQC
NC
DQPF
DQF
DQF
DQF
DQF
NC
DQPB
DQF
DQF
DQF
DQF
NC
E
F
DDQ
DDQ
DD
DD
DD
DDQ
DDQ
V
V
V
V
V
V
SS
ZQ
MCH
MCL
MCH
CKE
FT
SS
SS
SS
DD
SS
DD
SS
V
V
V
V
V
V
G
H
J
G
H
J
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
DDQ
DDQ
DD
DD
DDQ
DDQ
V
V
K
L
CK
NC
NC
NC
K
L
SS
DD
SS
DD
V
V
V
V
V
V
DDQ
DQH
DQH
DQH
DQH
DQPD
DQH
DQH
DQH
DQH
DQPH
DQA
DQA
DQA
DQA
DQPA
DQA
DQA
DQA
DQA
DQPE
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
SS
M
N
P
R
MCL
MCH
ZZ
M
N
P
R
SS
SS
SS
SS
SS
V
V
V
V
DDQ
DDQ
DD
DD
DDQ
DDQ
V
V
V
V
V
V
SS
SS
SS
DD
SS
DD
SS
SS
V
V
V
V
V
V
V
DDQ
DDQ
DD
DDQ
DDQ
V
V
SS
T
U
V
DQD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
NC
A
NC
NC
A
LBO
A
NC
A
NC
A
DQE
DQE
DQE
DQE
DQE
DQE
DQE
DQE
T
U
V
SS
NC
A
NC
A
A
A1
A0
A
A
W
TMS
TDI
A
A
TDO
TCK
W
2
11 x 19 Bump BGA—14 x 22 mm Body—1 mm Bump Pitch
Rev: 1.05 6/2006
2/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
GS8322Z72C-xxxV 209-Bump BGA Pin Description
Symbol
A0, A1
An
Type
Description
I
I
Address field LSBs and Address Counter Preset Inputs
Address Inputs
DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH
I/O
Data Input and Output pins
I
I
Byte Write Enable for DQA, DQB I/Os; active low
Byte Write Enable for DQC, DQD I/Os; active low
Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low
No Connect
BA, BB
BC,BD
I
BE, BF, BG,BH
NC
CK
E1
—
I
Clock Input Signal; active high
Chip Enable; active low
I
I
Chip Enable; active low
E3
I
Chip Enable; active high
E2
I
Output Enable; active low
G
I
Burst address counter advance enable
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Must Connect High
ADV
ZZ
I
I
FT
I
LBO
MCH
MCH
MCL
W
I
I
Must Connect High
Must Connect Low
I
I
I
Write Enable; active low
FLXDrive Output Impedance Control
Low = Low Impedance [High Drive],
High = High Impedance [Low Drive]
ZQ
Clock Enable; active low
CKE
Rev: 1.05 6/2006
3/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
GS8322Z72C-xxxV 209-Bump BGA Pin Description
Symbol
TMS
Type
Description
I
I
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
TDI
O
I
TDO
TCK
V
I
Core power supply
DD
V
I
I
I/O and Core Ground
SS
V
Output driver power supply
DDQ
Rev: 1.05 6/2006
4/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
GS8322Z36B-xxxV Pad Out—119-Bump BGA—Top View (Package B)
1
2
A
3
A
A
A
4
A
5
A
A
A
6
A
7
V
V
DDQ
A
B
C
D
E
F
A
B
C
D
E
F
DDQ
NC
NC
E2
ADV
E3
NC
NC
V
A
A
DD
V
V
DQC
DQC
DQPC
DQC
DQC
DQC
DQC
ZQ
E1
G
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
DDQ
DDQ
G
H
J
DQC
DQC
BC
A
BB
DQB
DQB
G
H
J
V
V
SS
W
SS
V
V
V
V
V
NC
NC
DDQ
DD
DD
DD
DDQ
V
V
K
L
DQD
DQD
DQD
DQD
DQD
DQD
DQPD
A
CK
NC
CKE
A1
DQA
DQA
DQA
DQA
DQPA
A
DQA
DQA
K
L
SS
SS
BD
BA
V
V
V
V
M
N
P
R
T
M
N
P
R
T
DDQ
SS
SS
DDQ
V
V
DQD
DQD
NC
DQA
DQA
NC
SS
SS
V
V
A0
SS
SS
V
LBO
A
FT
A
DD
NC
NC
A
TCK
2
A
ZZ
V
V
U
TMS
TDI
TDO
NC
U
DDQ
DDQ
7 x 17 Bump BGA—14 x 22 mm Body—1.27 mm Bump Pitch
Rev: 1.05 6/2006
5/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
GS8322Z18B-xxxV Pad Out—119-Bump BGA—Top View (Package B)
1
2
A
3
A
A
A
4
A
5
A
A
A
6
A
7
V
V
DDQ
A
B
C
D
E
F
A
B
C
D
E
F
DDQ
NC
NC
E2
ADV
E3
NC
NC
V
A
A
DD
V
V
DQB
NC
NC
DQB
NC
DQB
NC
ZQ
E1
G
DQPA
NC
DQA
NC
DQA
NC
SS
SS
SS
SS
SS
SS
V
V
V
V
DQA
V
V
DDQ
DDQ
G
H
J
NC
BB
A
NC
DQA
NC
G
H
J
V
V
DQB
W
SS
SS
V
V
V
V
V
NC
NC
DDQ
DD
DD
DD
DDQ
V
V
K
L
NC
DQB
NC
CK
NC
CKE
A1
NC
DQA
NC
DQA
NC
A
DQA
NC
K
L
SS
SS
DQB
NC
BA
V
V
V
V
M
N
P
R
T
DQB
NC
M
N
P
R
T
DDQ
SS
SS
DDQ
V
V
DQB
NC
NC
DQA
NC
SS
SS
V
V
DQPB
A
A0
SS
SS
V
NC
LBO
A
FT
A
DD
NC
A
A
TCK
2
A
ZZ
V
V
U
TMS
TDI
TDO
NC
U
DDQ
DDQ
7 x 17 Bump BGA—14 x 22 mm Body—1.27 mm Bump Pitch
Rev: 1.05 6/2006
6/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
GS8322Z18/36B-xxxV 119-Bump BGA Pin Description
Symbol
A0, A1
An
Type
Description
I
I
Address field LSBs and Address Counter Preset Inputs
Address Inputs
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA, BB, BC, BD
I
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
NC
CK
CKE
W
Clock Input Signal; active high
Clock Enable; active low
I
I
Write Enable; active low
E1
I
Chip Enable; active low
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
ZZ
I
Burst address counter advance enable
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
I
FT
I
LBO
I
FLXDrive Output Impedance Control
Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
ZQ
I
I
I
Scan Test Mode Select
Scan Test Data In
TMS
TDI
O
I
Scan Test Data Out
Scan Test Clock
TDO
TCK
V
I
Core power supply
DD
V
I
I/O and Core Ground
Output driver power supply
SS
V
I
DDQ
BPR1999.05.18
Rev: 1.05 6/2006
7/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
165 Bump BGA—x18 Common I/O—Top View (Package E)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
E1
BB
NC
E3
CKE
ADV
A
A
A
A
B
C
D
E
F
NC
NC
A
E2
NC
BA
CK
W
G
A
A
NC
NC
NC
NC
NC
ZQ
NC
DQPA
DQA
DQA
DQA
DQA
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DQB
DQB
DQB
DQB
MCH
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
NC
G
H
J
NC
G
H
J
FT
NC
NC
DQB
DQB
DQB
DQB
DQPB
NC
V
V
DQA
DQA
DQA
DQA
NC
A
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
NC
V
V
V
V
V
V
V
V
NC
K
L
NC
NC
M
N
P
R
NC
NC
M
N
P
R
NC
V
NC
TDI
NC
A1
A0
NC
V
NC
DDQ
SS
SS
DDQ
NC
A
A
A
TDO
TCK
A
A
A
NC
LBO
A
A
TMS
A
A
A
11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch
Rev: 1.05 6/2006
8/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
165 Bump BGA—x36 Common I/O—Top View (Package E)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
E1
BC
BB
E3
CKE
ADV
A
A
NC
A
B
C
D
E
F
NC
DQPC
DQC
DQC
DQC
DQC
FT
A
E2
BD
BA
CK
W
G
A
A
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
DQC
DQC
DQC
DQC
MCH
DQD
DQD
DQD
DQD
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQB
DQB
DQB
DQB
ZQ
G
H
J
G
H
J
NC
NC
DQD
DQD
DQD
DQD
DQPD
NC
V
V
DQA
DQA
DQA
DQA
NC
DQA
DQA
DQA
DQA
DQPA
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
V
V
V
V
V
V
V
V
K
L
M
N
P
R
M
N
P
R
V
NC
TDI
NC
A1
A0
NC
V
SS
DDQ
SS
DDQ
NC
A
A
A
TDO
TCK
A
A
A
A
LBO
A
A
TMS
A
A
A
11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch
Rev: 1.05 6/2006
9/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
GS8322Z18/36E-xxxV 165-Bump BGA Pin Description
Symbol
A0, A1
An
Type
Description
I
I
I
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Address Input
A18
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA, BB, BC, BD
I
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
NC
CK
CKE
W
Clock Input Signal; active high
Clock Enable; active low
I
I
Write Enable; active low
E1
I
Chip Enable; active low
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
FT
I
Flow Through / Pipeline Mode Control
Output Enable; active low
G
I
ADV
I
Burst address counter advance enable; active high
FLXDrive Output Impedance Control
Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
ZQ
I
ZZ
I
I
Sleep mode control; active high
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
LBO
TMS
TDI
I
I
O
I
Scan Test Data Out
TDO
TCK
MCH
Scan Test Clock
—
I
Must Connect High
V
Core power supply
DD
V
I
I
I/O and Core Ground
SS
V
Output driver power supply
DDQ
Rev: 1.05 6/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
W
H
L
BA
X
BB
X
BC
X
BD
X
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.05 6/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Synchronous Truth Table
Operation
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
R
B
R
B
W
B
B
D
D
D
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L
L
L
L
L
L
L
L
L
L
L
H
L
H
X
H
X
L
X
X
X
X
L
L
X
L
H
X
H
X
H
X
X
X
X
L
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
Q
Q
1,10
2
External
Next
H
H
X
X
X
X
X
X
High-Z
Dummy Read, Continue Burst
Write Cycle, Begin Burst
H
L
X
L
X
L
High-Z 1,2,10
External
Next
D
D
3
Write Cycle, Continue Burst
Write Abort, Continue Burst
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
H
H
L
X
X
X
X
X
L
X
X
H
X
X
X
X
X
H
X
1,3,10
Next
H
X
X
X
High-Z 1,2,3,10
High-Z
None
None
L
High-Z
None
L
High-Z
1
Deselect Cycle
D
D
None
L-H
L
L
L
H
L
H
L
X
L
High-Z
Deselect Cycle, Continue
Sleep Mode
None
None
L-H
X
L
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
High-Z
High-Z
-
1
4
Clock Edge Ignore, Stall
Current
L-H
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.05 6/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Pipelined and Flow Through Read Write Control State Diagram
D
B
Deselect
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
W
R
Burst Read
Burst Write
B
B
D
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
R
B
W
B
Intermediate
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
Intermediate
D
Intermediate
W
R
High Z
B
D
Intermediate
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+2)
Intermediate State (N+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Intermediate
State
Current State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
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GS8322Z18/36/72(B/E/C)-xxxV
Flow Through Mode Data I/O State Diagram
R
B
W
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
D
W
R
High Z
B
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
FLXDrive™
The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
L
Burst Order Control
LBO
H
L
Output Register Control
Power Down Control
FT
ZZ
ZQ
H or NC
L or NC
H
Active
Standby, I = I
DD SB
L
High Drive (Low Impedance)
Low Drive (High Impedance)
FLXDrive Output Impedance Control
H or NC
Note:
There are pull-up devices on the ZQ and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
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GS8322Z18/36/72(B/E/C)-xxxV
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note:
Note:
The burst counter wraps to initial state on the 5th clock.
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
ZZ
tZZR
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal. Not
all vendors offer this option, however most mark the pin V or V on pipelined parts and V on flow through parts. GSI NBT
DD
DDQ
SS
SRAMs are fully compatible with these sockets. Other vendors mark the pin as a No Connect (NC). GSI RAMs have an internal
pull-up device on the FT pin so a floating FT pin will result in pipelined operation. If the part being replaced is a pipelined mode
part, the GSI RAM is fully compatible with these sockets. In the unlikely event the part being replaced is a Flow Through device,
the pin will need to be pulled low for correct operation.
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GS8322Z18/36/72(B/E/C)-xxxV
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 4.6
DD
DD
V
Voltage on V
Pins
–0.5 to V
V
DDQ
DDQ
DD
V
–0.5 to V
+0.5 (≤ 4.6 V max.)
DDQ
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
I/O
V
–0.5 to V +0.5 (≤ 4.6 V max.)
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges (1.8 V/2.5 V Version)
Parameter
Symbol
Min.
1.7
Typ.
1.8
Max.
2.0
Unit
Notes
V
1.8 V Supply Voltage
2.5 V Supply Voltage
V
V
V
V
DD1
V
2.3
2.5
2.7
DD2
1.8 V V
I/O Supply Voltage
V
V
1.7
1.8
DDQ
DDQ
DDQ1
DD
2.5 V V
I/O Supply Voltage
V
V
2.3
2.5
DDQ2
DD
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
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GS8322Z18/36/72(B/E/C)-xxxV
V
& V
Range Logic Levels
DDQ2
DDQ1
Parameter
Symbol
Min.
Typ.
—
Max.
Unit
V
Notes
V
V
Input High Voltage
V
0.6*V
V
+ 0.3
DD
1
1
DD
IH
DD
Input Low Voltage
V
0.3*V
DD
–0.3
—
V
DD
IL
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Recommended Operating Temperatures
Parameter
Symbol
Min.
0
Typ.
25
Max.
70
Unit
°C
Notes
T
Ambient Temperature (Commercial Range Versions)
2
2
A
T
Ambient Temperature (Industrial Range Versions)
–40
25
85
°C
A
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
DD
V
SS
50%
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V
= 0 V
Input Capacitance
4
6
5
7
IN
IN
C
V
OUT
= 0 V
Input/Output Capacitance
pF
I/O
Note:
These parameters are sample tested.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
AC Test Conditions
Parameter
Conditions
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
/2
Figure 1
Output Load 1
Input slew rate
DQ
V
Input reference level
DD
V
/2
Output reference level
Output load
DDQ
*
50Ω
30pF
Fig. 1
Notes:
V
DDQ/2
* Distributed Test Jig Capacitance
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
I
V
≥ V ≥ 0 V
DD IN
FT, ZQ, ZZ Input Current
Output Leakage Current
–100 uA
–1 uA
100 uA
1 uA
IN
I
Output Disable, V
= 0 to V
OL
OUT DD
DC Output Characteristics (1.8 V/2.5 V Version)
Parameter
Symbol
Test Conditions
Min
Max
—
V
I
= –4 mA, V
= 1.6 V
V
– 0.4 V
DDQ
1.8 V Output High Voltage
2.5 V Output High Voltage
1.8 V Output Low Voltage
2.5 V Output Low Voltage
OH1
OH
DDQ
V
I
= –8 mA, V
= 2.375 V
DDQ
1.7 V
—
OH2
OH
V
I
I
= 4 mA
= 8 mA
—
—
0.4 V
0.4 V
OL1
OL
OL
V
OL2
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GS8322Z18/36/72(B/E/C)-xxxV
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
AC Electrical Characteristics
-250
-225
-200
-166
-150
-133
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
tKC
tKQ
4.0
—
—
3.0
—
—
—
—
6.5
—
—
—
—
—
—
4.4
—
—
3.0
—
—
—
—
7.0
—
—
—
—
—
—
5.0
—
—
3.0
—
—
—
—
7.5
—
—
—
—
—
—
6.0
—
—
3.5
—
—
—
—
8.0
—
—
—
—
—
—
6.7
—
—
3.8
—
—
—
—
8.5
—
—
—
—
—
—
7.5
—
1.5
1.5
1.5
8.5
—
3.0
3.0
1.5
0.5
1.7
2
—
4.0
—
—
—
—
8.5
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKQX
1.5
1.5
1.5
6.5
—
1.5
1.5
1.5
7.0
—
1.5
1.5
1.5
7.5
—
1.5
1.5
1.5
8.0
—
1.5
1.5
1.5
8.5
—
Pipeline
1
tLZ
tS
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKC
tKQ
tKQX
3.0
3.0
1.5
0.5
1.3
1.7
3.0
3.0
1.5
0.5
1.3
1.7
3.0
3.0
1.5
0.5
1.3
1.7
3.0
3.0
1.5
0.5
1.3
1.7
3.0
3.0
1.5
0.5
1.5
1.7
Flow
Through
1
tLZ
tS
tH
Hold time
Clock HIGH Time
Clock LOW Time
tKH
tKL
Clock to Output in
High-Z
1
1.5
2.5
1.5
2.7
1.5
3.0
1.5
3.0 1.5 3.0 1.5 3.0
3.0 1.5 3.0 1.5 3.0
ns
tHZ
(x18/x36)
Clock to Output in
High-Z
1
1.5
3.0
2.5
1.5
3.0
2.7
1.5
3.0
3.0
1.5
ns
ns
tHZ
(x72)
G to Output Valid
(x18/x36)
tOE
tOE
—
—
—
—
3.5
—
3.8
—
4.0
G to Output Valid
(x72)
—
0
3.0
—
2.5
—
0
3.0
—
2.7
—
0
3.0
—
3.0
—
0
3.5
—
3.0
—
0
3.8
—
3.0
—
0
4.0
—
3.0
ns
ns
ns
1
G to output in Low-Z
tOLZ
G to output in High-Z
(x18/x36)
1
—
—
—
—
—
—
tOHZ
G to output in High-Z
(x72)
1
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
ns
tOHZ
2
ZZ setup time
ZZ hold time
ZZ recovery
5
1
—
—
—
5
1
—
—
—
5
1
—
—
—
5
1
—
—
—
5
1
—
—
—
5
1
—
—
—
ns
ns
ns
tZZS
2
tZZH
tZZR
20
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.05 6/2006
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© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Pipeline Mode Timing (NBT)
Write A
Read B
Suspend
tKH
Read C
tKC
Write D
writeno-op
Read E
Deselect
tKL
CK
A
tH
tH
tH
tH
tH
tH
tS
A
B
C
D
E
tS
tS
tS
tS
tS
CKE
E*
ADV
W
tH
tS
Bn
tH
tLZ
tHZ
tS
tKQ
tKQX
D(A)
Q(B)
Q(C)
D(D)
Q(E)
DQ
Rev: 1.05 6/2006
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© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Flow Through Mode Timing (NBT)
Write A
Write B
Write B+1 Read C
tKL
Cont
Read D
Write E
Read F
Write G
tKH
tKC
CK
CKE
E
tH
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
ADV
W
Bn
A0–An
A
B
C
D
E
F
G
tKQ
tLZ
tH
tKQ
tLZ
D(B+1)
tKQX
tS
D(A)
tHZ
Q(D)
tKQX
D(G)
DQ
D(B)
Q(C)
D(E)
Q(F)
tOLZ
tOE
tOHZ
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DDQ
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
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© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Rev: 1.05 6/2006
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© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
·
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1
0
·
· · ·
Control Signals
Test Access Port (TAP) Controller
TMS
TCK
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
GSI Technology
Not Used
JEDEC Vendor
ID Code
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0 1 1 0 1 1 0 0 1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
Rev: 1.05 6/2006
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© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
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© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
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© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
1
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
010
011
TDO.
1
1
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
100
101
110
111
1
1
1
1
GSI
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.05 6/2006
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© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
JTAG Port Recommended Operating Conditions and DC Characteristics (1.8/2.5 V Version)
Parameter
Symbol
Min.
–0.3
Max.
Unit Notes
V
0.3 * V
1.8 V Test Port Input Low Voltage
2.5 V Test Port Input Low Voltage
1.8 V Test Port Input High Voltage
2.5 V Test Port Input High Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
V
V
1
1
ILJ1
DD1
V
0.3 * V
DD2
–0.3
ILJ2
V
0.6 * V
V
V
+0.3
+0.3
V
1
IHJ1
DD1
DD1
DD2
V
0.6 * V
DD2
V
1
IHJ2
I
–300
–1
1
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
Test Port Output High Voltage
1.7
—
0.4
—
5, 6
5, 7
5, 8
5, 9
OHJ
V
Test Port Output Low Voltage
—
V
OLJ
V
V
– 100 mV
DDQ
Test Port Output CMOS High
V
OHJC
V
Test Port Output CMOS Low
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –2 V < Vi < V
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
3. 0 V ≤ V ≤ V
IN
ILJn
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V
supply.
DDQ
6.
7.
8.
9.
I
I
I
I
= –4 mA
OHJ
= + 4 mA
OLJ
= –100 uA
= +100 uA
OHJC
OLJC
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
DQ
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
*
50Ω
30pF
Input slew rate
V
V
/2
Input reference level
DDQ
V
/2
DDQ
/2
Output reference level
* Distributed Test Jig Capacitance
DDQ
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.05 6/2006
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© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
TDI
tTH
tTH
tTS
tTS
TMS
TDO
tTKQ
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
Max
—
Unit
TCK Cycle Time
50
—
ns
ns
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
20
20
10
10
—
—
tTH
—
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
Rev: 1.05 6/2006
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© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
209 BGA Package Drawing (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
A1
C
A
Side View
D
aaa
D1
e
Bottom View
∅b
e
Symbol
Min
Typ
Max
1.70
0.60
0.70
0.38
22.1
Units
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
A
A1
∅b
c
0.40
0.50
0.31
21.9
0.50
0.60
0.36
D
22.0
D1
E
18.0 (BSC)
14.0
13.9
14.1
E1
e
10.0 (BSC)
1.00 (BSC)
0.15
aaa
Rev 1.0
Rev: 1.05 6/2006
32/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Package Dimensions—165-Bump FPBGA (Package E)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.60 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
1.0
15±0.05
B
0.20(4x)
SEATING PLANE
C
Rev: 1.05 6/2006
33/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
TOP VIEW
BOTTOM VIEW
A1
A1
S
Ø0.10
C
S
S
S
Ø0.30 C A
B
Ø0.60~0.90 (119x)
1
2
3
4
5
6
7
7
6
5
4 3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
M
N
P
R
T
U
K
L
M
N
P
R
T
U
B
1.27
7.62
14±0.10
A
0.20(4x)
SEATING PLANE
C
BPR 1999.05.18
Rev: 1.05 6/2006
34/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Ordering Information for GSI Synchronous Burst RAMs
2
Voltage
Option
Speed
3
1
4
Org
Type
Package
T
Part Number
Status
A
(MHz/ns)
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
GS8322Z18B-250V
GS8322Z18B-225V
GS8322Z18B-200V
GS8322Z18B-166V
GS8322Z18B-150V
GS8322Z18B-133V
GS8322Z18E-250V
GS8322Z18E-225V
GS8322Z18E-200V
GS8322Z18E-166V
GS8322Z18E-150V
GS8322Z18E-133V
GS8322Z36B-250V
GS8322Z36B-225V
GS8322Z36B-200V
GS8322Z36B-166V
GS8322Z36B-150V
GS8322Z36B-133V
GS8322Z36E-250V
GS8322Z36E-225V
GS8322Z36E-200V
GS8322Z36E-166V
GS8322Z36E-150V
GS8322Z36E-133V
GS8322Z72C-250V
GS8322Z72C-225V
GS8322Z72C-200V
GS8322Z72C-166V
GS8322Z72C-150V
GS8322Z72C-133V
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
165 BGA
250/6.5
225/7
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
200/7.5
166/8
150/8.5
133/8.5
250/6.5
225/7
165 BGA
165 BGA
200/7.5
166/8
165 BGA
165 BGA
150/8.5
133/8.5
250/6.5
225/7
165 BGA
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
165 BGA
200/7.5
166/8
150/8.5
133/8.5
250/6.5
225/7
165 BGA
165 BGA
200/7.5
166/8
165 BGA
165 BGA
150/8.5
133/8.5
250/6.5
225/7
165 BGA
209 BGA
209 BGA
209 BGA
200/7.5
166/8
209 BGA
209 BGA
150/8.5
133/8.5
209 BGA
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IVT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. MP = Mass Production. PQ = Pre-Qualification.
5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.05 6/2006
35/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Ordering Information for GSI Synchronous Burst RAMs (Cont.)
2
Voltage
Option
Speed
3
1
4
Org
Type
Package
T
Part Number
Status
A
(MHz/ns)
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
2M x 18
GS8322Z18B-250IV
GS8322Z18B-225IV
GS8322Z18B-200IV
GS8322Z18B-166IV
GS8322Z18B-150IV
GS8322Z18B-133IV
GS8322Z18E-250IV
GS8322Z18E-225IV
GS8322Z18E-200IV
GS8322Z18E-166IV
GS8322Z18E-150IV
GS8322Z18E-133IV
GS8322Z36B-250IV
GS8322Z36B-225IV
GS8322Z36B-200IV
GS8322Z36B-166IV
GS8322Z36B-150IV
GS8322Z36B-133IV
GS8322Z36E-250IV
GS8322Z36E-225IV
GS8322Z36E-200IV
GS8322Z36E-166IV
GS8322Z36E-150IV
GS8322Z36E-133IV
GS8322Z72C-250IV
GS8322Z72C-225IV
GS8322Z72C-200IV
GS8322Z72C-166IV
GS8322Z72C-150IV
GS8322Z72C-133IV
GS8322Z18GB-250V
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
165 BGA
250/6.5
225/7
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
C
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
MP
PQ
200/7.5
166/8
150/8.5
133/8.5
250/6.5
225/7
165 BGA
165 BGA
200/7.5
166/8
165 BGA
165 BGA
150/8.5
133/8.5
250/6.5
225/7
165 BGA
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
165 BGA
200/7.5
166/8
150/8.5
133/8.5
250/6.5
225/7
165 BGA
165 BGA
200/7.5
166/8
165 BGA
165 BGA
150/8.5
133/8.5
250/6.5
225/7
165 BGA
209 BGA
209 BGA
209 BGA
200/7.5
166/8
209 BGA
209 BGA
150/8.5
133/8.5
250/6.5
209 BGA
RoHS-compliant 119 BGA (var. 2)
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IVT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. MP = Mass Production. PQ = Pre-Qualification.
5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.05 6/2006
36/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Ordering Information for GSI Synchronous Burst RAMs (Cont.)
2
Voltage
Option
Speed
3
1
4
Org
Type
Package
T
Part Number
Status
A
(MHz/ns)
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
2M x 18
2M x 18
GS8322Z18GB-225V
GS8322Z18GB-200V
GS8322Z18GB-166V
GS8322Z18GB-150V
GS8322Z18GB-133V
GS8322Z18GE-250V
GS8322Z18GE-225V
GS8322Z18GE-200V
GS8322Z18GE-166V
GS8322Z18GE-150V
GS8322Z18GE-133V
GS8322Z36GB-250V
GS8322Z36GB-225V
GS8322Z36GB-200V
GS8322Z36GB-166V
GS8322Z36GB-150V
GS8322Z36GB-133V
GS8322Z36GE-250V
GS8322Z36GE-225V
GS8322Z36GE-200V
GS8322Z36GE-166V
GS8322Z36GE-150V
GS8322Z36GE-133V
GS8322Z72GC-250V
GS8322Z72GC-225V
GS8322Z72GC-200V
GS8322Z72GC-166V
GS8322Z72GC-150V
GS8322Z72GC-133V
GS8322Z18GB-250IV
GS8322Z18GB-225IV
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 165 BGA
225/7
200/7.5
166/8
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
150/8.5
133/8.5
250/6.5
225/7
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
200/7.5
166/8
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
150/8.5
133/8.5
250/6.5
225/7
RoHS-compliant 165 BGA
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 165 BGA
200/7.5
166/8
150/8.5
133/8.5
250/6.5
225/7
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
200/7.5
166/8
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
150/8.5
133/8.5
250/6.5
225/7
RoHS-compliant 165 BGA
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
200/7.5
166/8
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
150/8.5
133/8.5
250/6.5
225/7
RoHS-compliant 209 BGA
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IVT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. MP = Mass Production. PQ = Pre-Qualification.
5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.05 6/2006
37/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
Ordering Information for GSI Synchronous Burst RAMs (Cont.)
2
Voltage
Option
Speed
3
1
4
Org
Type
Package
T
Part Number
Status
A
(MHz/ns)
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
2M x 18
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
1M x 36
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
512K x 72
GS8322Z18GB-200IV
GS8322Z18GB-166IV
GS8322Z18GB-150IV
GS8322Z18GB-133IV
GS8322Z18GE-250IV
GS8322Z18GE-225IV
GS8322Z18GE-200IV
GS8322Z18GE-166IV
GS8322Z18GE-150IV
GS8322Z18GE-133IV
GS8322Z36GB-250IV
GS8322Z36GB-225IV
GS8322Z36GB-200IV
GS8322Z36GB-166IV
GS8322Z36GB-150IV
GS8322Z36GB-133IV
GS8322Z36GE-250IV
GS8322Z36GE-225IV
GS8322Z36GE-200IV
GS8322Z36GE-166IV
GS8322Z36GE-150IV
GS8322Z36GE-133IV
GS8322Z72GC-250IV
GS8322Z72GC-225IV
GS8322Z72GC-200IV
GS8322Z72GC-166IV
GS8322Z72GC-150IV
GS8322Z72GC-133IV
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
NBT
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
1.8 V or 2.5 V
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 165 BGA
200/7.5
166/8
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
150/8.5
133/8.5
250/6.5
225/7
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
200/7.5
166/8
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
150/8.5
133/8.5
250/6.5
225/7
RoHS-compliant 165 BGA
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 165 BGA
200/7.5
166/8
150/8.5
133/8.5
250/6.5
225/7
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
200/7.5
166/8
RoHS-compliant 165 BGA
RoHS-compliant 165 BGA
150/8.5
133/8.5
250/6.5
225/7
RoHS-compliant 165 BGA
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
200/7.5
166/8
RoHS-compliant 209 BGA
RoHS-compliant 209 BGA
150/8.5
133/8.5
RoHS-compliant 209 BGA
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IVT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. MP = Mass Production. PQ = Pre-Qualification.
5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.05 6/2006
38/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18/36/72(B/E/C)-xxxV
36Mb Sync SRAM Datasheet Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Page;Revisions;Reason
New
• Creation of new datasheet
8322ZV18_r1
• Removed erroneous overbars from address pins on the x18
165 BGA pinout
• Corrected thickness of “E” package to 1.4 mm
8322ZVxx_r1;
8322ZVxx_r1_01
Content
• Updated format
• Updated mechanicals
8322ZVxx_r1_01;
8322ZVxx_r1_02
Content/Format
Content
• Pb-free information added
• (r1.03a) Corrected incorrect voltage in title bar
8322ZVxx_r1_02;
8322ZVxx_r1_03
• Updated IDDQ information in Operating Currents table
8322ZVxx_r1_03;
8322ZVxx_r1_04
Content
• Updated entire datasheet to reflect new ordering information
and new AC specs for 1.8 V/2.5 V part
8322ZVxx_r1_04;
8322Zxx_V_r1_05
Content
Rev: 1.05 6/2006
39/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8322Z18E-166IV 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
GS8322Z18E-166IVT | GSI | 暂无描述 | 获取价格 | |
GS8322Z18E-166T | GSI | 36Mb Pipelined and Flow Through Synchronous NBT SRAM | 获取价格 | |
GS8322Z18E-166V | GSI | 36Mb Pipelined and Flow Through Synchronous NBT SRAM | 获取价格 | |
GS8322Z18E-200 | GSI | 36Mb Pipelined and Flow Through Synchronous NBT SRAM | 获取价格 | |
GS8322Z18E-200I | GSI | 36Mb Pipelined and Flow Through Synchronous NBT SRAM | 获取价格 | |
GS8322Z18E-200IT | GSI | 36Mb Pipelined and Flow Through Synchronous NBT SRAM | 获取价格 | |
GS8322Z18E-200IV | GSI | 36Mb Pipelined and Flow Through Synchronous NBT SRAM | 获取价格 | |
GS8322Z18E-200IVT | GSI | ZBT SRAM, 2MX18, 7.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165 | 获取价格 | |
GS8322Z18E-200T | GSI | 36Mb Pipelined and Flow Through Synchronous NBT SRAM | 获取价格 | |
GS8322Z18E-200V | GSI | 36Mb Pipelined and Flow Through Synchronous NBT SRAM | 获取价格 |
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