GS8342Q09GE-250I_技术文档

Preliminary

GS8342Q08/09/18/36E-300/250/200/167

167 MHz–300 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

36Mb SigmaQuad-II

Burst of 2 SRAM

1.8 V V

DD

1.8 V and 1.5 V I/O

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

• Pin-compatible with present 9Mb and 18Mb and future 72Mb

and 144Mb devices

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaQuad™ Family Overview

The GSQ8342Q08/09/18/36E are built in compliance with

the SigmaQuad-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. The GSQ8342Q08/09/18/36E SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Because Separate I/O SigmaQuad-II B2 RAMs always transfer

data in two packets, A0 is internally set to 0 for the first read or

write transfer, and automatically incremented by 1 for the next

transfer. Because the LSB is tied off internally, the address

field of a SigmaQuad-II B2 RAM is always one address pin

less than the advertised index depth (e.g., the 2M x 18 has a

1024K addressable index).

Clocking and Addressing Schemes

The GSQ8342Q08/09/18/36E SigmaQuad-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

Parameter Synopsis

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

tKHKH

tKHQV

6.0 ns

0.5 ns

Rev: 1.02 8/2005

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8342Q08/09/18/36E-300/250/200/167

1M x 36 SigmaQuad-II SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

MCL/SA

(256Mb) (72Mb)

NC/SA

MCL/SA

(144Mb)

A

CQ

W

BW2

K

BW1

R

SA

CQ

B

C

D

E

F

Q27

D27

D28

Q29

Q30

D30

Doff

D31

Q32

Q33

D33

D34

Q35

TDO

Q18

Q28

D20

D29

Q21

D22

D18

D19

Q19

Q20

D21

Q22

SA

BW3

SA

K

BW0

SA

D17

D16

Q16

Q15

D14

Q13

Q17

Q7

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

V

SA

V

SS

V

D15

D6

SS

DD

SS

DD

V

DDQ

V

Q14

D13

DDQ

G

H

J

V

REF

DDQ

Q31

D23

Q23

D24

D25

Q25

Q26

SA

D12

Q12

D11

D10

Q10

Q9

Q4

D3

K

L

D32

Q24

Q34

D26

D35

TCK

V

Q11

Q1

DDQ

SS

M

N

P

R

V

SS

V

SA

C

SA

V

D9

SA

D0

C

SA

TMS

2

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35

2. MCL = Must Connect Low

Rev: 1.02 8/2005

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8342Q08/09/18/36E-300/250/200/167

2M x 18 SigmaQuad-II SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

MCL/SA

(144Mb)

MCL/SA

(72Mb)

A

CQ

SA

W

BW1

K

NC

R

SA

CQ

B

C

D

E

F

NC

Doff

NC

TDO

Q9

NC

D9

SA

NC

SA

K

BW0

SA

NC

Q7

NC

D6

NC

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

D10

Q10

Q11

D12

Q13

V

SA

V

SS

D11

NC

V

SS

DD

SS

DD

V

DDQ

Q12

D13

V

DDQ

G

H

J

V

REF

DDQ

NC

D14

Q14

D15

D16

Q16

Q17

SA

NC

Q4

D3

K

L

V

NC

SA

Q15

NC

V

NC

Q1

DDQ

SS

M

N

P

R

V

SS

D17

NC

V

SA

C

SA

V

NC

D0

SA

TCK

C

TMS

2

11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.

2. MCL = Must Connect Low

Rev: 1.02 8/2005

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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4M x 8 SigmaQuad-II SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

MCL/SA

(72Mb)

A

CQ

SA

W

NW1

K

NC

R

SA

CQ

B

C

D

E

F

NC

Doff

NC

TDO

NC

D4

NC

D5

NC

Q4

NC

Q5

SA

NC

SA

K

NW0

SA

NC

D2

Q3

D3

NC

Q2

NC

ZQ

D1

NC

Q0

D0

NC

TDI

V

SA

V

SS

V

SS

DD

SS

DD

V

DDQ

V

NC

DDQ

G

H

J

V

REF

DDQ

NC

Q6

NC

Q1

K

L

NC

D6

NC

Q7

SA

V

NC

SA

NC

V

DDQ

SS

M

N

P

R

NC

D7

V

NC

SS

V

SA

C

SA

V

NC

TCK

SA

NC

C

TMS

2

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Notes:

1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.

2. MCL = Must Connect Low

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8342Q08/09/18/36E-300/250/200/167

4M x 9 SigmaQuad-II SRAM — Top View

1

2

3

4

5

6

7

8

9

10

11

MCL/SA

(72Mb)

A

CQ

SA

W

NC

K

NC

R

SA

CQ

B

C

D

E

F

NC

Doff

NC

TDO

NC

D5

NC

D6

NC

Q5

NC

Q6

SA

NC

SA

K

BW

SA

NC

D3

Q4

D4

NC

Q3

NC

ZQ

D2

NC

Q1

D1

NC

Q0

TDI

V

SA

V

SS

V

SS

DD

SS

DD

V

DDQ

V

NC

DDQ

G

H

J

V

REF

DDQ

NC

Q7

NC

Q2

K

L

NC

D7

NC

Q8

SA

V

NC

SA

NC

D0

V

DDQ

SS

M

N

P

R

NC

D8

V

SS

V

SA

C

SA

V

NC

TCK

SA

C

TMS

2

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Note: MCL = Must Connect Low

Rev: 1.02 8/2005

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8342Q08/09/18/36E-300/250/200/167

Pin Description Table

Symbol

Description

Synchronous Address Inputs

No Connect

Type

Input

—

Comments

—

SA

NC

R

—

Synchronous Read

Synchronous Write

Input

Active High

Active Low

W

Active Low

x9 only

BW

Synchronous Byte Write

Synchronous Byte Writes

Nybble Write Control Pin

Input

Active Low

x18/x36 only

BW0–BW3

NW0–NW1

Active Low

x8 only

K

Input Clock

Input

Active High

Active Low

C

Output Clock

Input

Active High

C

Output Clock

Input

Active Low

TMS

TDI

TCK

TDO

Test Mode Select

Input

—

Test Data Input

Input

Test Clock Input

Input

Test Data Output

Output

Input

V

HSTL Input Reference Voltage

Output Impedance Matching Input

Synchronous Data Outputs

Synchronous Data Inputs

Disable DLL when low

Output Echo Clock

Power Supply

REF

ZQ

Qn

Dn

Input

Output

Input

D

Input

Active Low

off

CQ

Output

Supply

—

V

1.8 V Nominal

DD

V

Isolated Output Buffer Supply

Power Supply: Ground

Supply

1.5 or 1.8 V Nominal

—

DDQ

V

SS

Note:

NC = Not Connected to die or any other pin

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8342Q08/09/18/36E-300/250/200/167

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O

SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from

Separate I/O SRAMs can cut the RAM’s bandwidth in half.

Alternating Read-Write Operations

SigmaQuad-II SRAMs follow a few simple rules of operation.

- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.

- Read or Write data transfers in progress may not be interrupted and re-started.

- R and W high always deselects the RAM.

- All address, data, and control inputs are sampled on clock edges.

In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for

details.

SigmaQuad-II B2 SRAM DDR Read

The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R,

begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied

high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high). Clocking in a high on the

Read Enable-bar pin, R, begins a read port deselect cycle.

SigmaQuad-II B2 Double Data Rate SRAM Read First

Read A

NOP

Write B

Read C Write D

Read E Write F

Read G Write H

K

Address

A

B

C

D

E

F

G

H

R

W

BWx

D

B

B+1

D

D+1

F

F+1

H

H+1

D

D+1

F

F+1

H+1

C

Q

A

A+1

C

C+1

E

CQ

Rev: 1.02 8/2005

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8342Q08/09/18/36E-300/250/200/167

SigmaQuad-II B2 SRAM DDR Write

The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of

K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is

clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on

the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle.

SigmaQuad-II B2 Double Data Rate SRAM Write First

Write A

Read B

Read C Write D

NOP

Read E Write F

Read G Write H

NOP

K

Address

A

B

C

D

E

F

G

H

R

W

BWx

D

A

A+1

D

D+1

F

F+1

H

H+1

C

Q

B

B+1

C

C+1

E

E+1

CQ

SigmaQuad-II B4 SRAM DDR Read

Special Functions

Byte Write and Nybble Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18

version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble

Write Enable” and “NBx” may be substituted in all the discussion above.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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Example x18 RAM Write Sequence using Byte Write Enables

Data In Sample

BW0

BW1

D0–D8

D9–D17

Time

Beat 1

Beat 2

0

1

0

Data In

Don’t Care

Data In

Don’t Care

Resulting Write Operation

Byte 1

D0–D8

Byte 2

D9–D17

Byte 3

D0–D8

Byte 4

D9–D17

Written

Unchanged

Written

Beat 1

Beat 2

Output Register Control

SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output

Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the

output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K

and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to

function as a conventional pipelined read SRAM.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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Example Four Bank Depth Expansion Schematic

R

3

W

3

R

2

W

2

1

0

R

1

W

R

0

W

A –A

0

n

K

D –D

1

n

Bank 3

Bank 1

Bank 2

Bank 0

A

W

R

W

R

CQ

K

CQ

K

CQ

K

D

C

K

D

C

D

C

Q

D

C

Q

C

Q –Q

1

n

CQ

0

CQ

1

CQ

2

3

Note:

For simplicity BWn, NWn, K, and C are not shown.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8342Q08/09/18/36E-300/250/200/167

Rev: 1.02 8/2005

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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FLXDrive-II Output Driver Impedance Control

HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to

via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be

V

SS

5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is

between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts

in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and

temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance

evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is

implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is

producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.

SigmaQuad-II B2 Coherency and Pass Through Functions

Because the SigmaQuad-II B2 read and write commands are loaded at the same time, there may be some confusion over what

constitutes “coherent” operation. Normally, one would expect a RAM to produce the just-written data when it is read immediately

after a write. This is true of the SigmaQuad-II B2 except in one case, as is illustrated in the following diagram. If the user holds the

same address value in a given K clock cycle, loading the same address as a read address and then as a matching write address, the

SigmaQuad-II B2 will read or “Pass-thru” the latest data input, rather than the data from the previously completed write operation.

SigmaQuad-II B2 Coherency and Pass Through Functions

Read

Write

Read

Write

Read

Write

Read

Write

Dwg Rev. G

K

/K

A

B

C

D

E

F

G

H

I

OO

OI

OO

OI

IO

OO

Address

/R

/W

/BWx

DB0

5

DB1

6

DD0

8

DD1

2

DF0

7

DF1

1

DH0

9

DH1

3

DI0

4

D

C

PASS-THRU

COHERENT

/C

QA0

QA1

?

QC0

QC1

6

QE0

7

QE1

1

?

5

Q

Rev: 1.02 8/2005

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Read Truth Table

A

R

Output Next State

Q

K ↑

(t )

(t

)

(t

)

n

n+1

n+1½

X

V

1

0

Deselect

Read

Hi-Z

Q0

Hi-Z

Q1

Notes:

1. X = Don’t Care, 1 = High, 0 = Low, V = Valid.

2. R is evaluated on the rising edge of K.

3. Q0 and Q1 are the first and second data output transfers in a read.

Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Write Truth Table

A

W

BWn

Input Next State

D

K ↑

n + ½

K ↑

n

K ↑

n

K ↑

n + ½

K ↑

n

K ↑

K ↑, K ↑

n

(t

)

(t )

(t

)

(t ), (t

)

n + ½

(t )

(t

)

n + ½

D1

X

V

X

0

1

0

1

X

0

1

0

1

X

Write Byte Dx0, Write Byte Dx1

Write Byte Dx0, Write Abort Byte Dx1

Write Abort Byte Dx0, Write Byte Dx1

Write Abort Byte Dx0, Write Abort Byte Dx1

Deselect

D0

X

D1

X

Notes:

1. X = Don’t Care, H = High, L = Low, V = Valid.

2. W is evaluated on the rising edge of K.

3. D0 and D1 are the first and second data input transfers in a write.

4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.).

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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x36 Byte Write Enable (BWn) Truth Table

BW0 BW1 BW2 BW3

D0–D8

Don’t Care

Data In

D9–D17

Don’t Care

Data In

D18–D26

Don’t Care

Data In

D27–D35

Don’t Care

Data In

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

x18 Byte Write Enable (BWn) Truth Table

BW0 BW1

D0–D8

Don’t Care

Data In

D9–D17

Don’t Care

Data In

1

0

1

0

1

0

Don’t Care

Data In

x8 Nybble Write Enable (NWn) Truth Table

NW0 NW1

D0–D3

Don’t Care

Data In

D4–D7

Don’t Care

Data In

1

0

1

0

1

0

Don’t Care

Data In

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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State Diagram

Power-Up

Read NOP

Write NOP

READ

WRITE

READ

WRITE

READ

Load New

Read Address

Load New

Write Address

WRITE

Always

(Fixed)

Always

(Fixed)

READ

WRITE

DDR Read

DDR Write

Notes:

1. Internal burst counter is fixed as 1-bit linear (i.e., when first address is A0+), next internal burst address is A0+1.

2. “READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is

true for “WRITE” and “WRITE”.

3. Read and write state machine can be active simultaneously.

4. State machine control timing sequence is controlled by K.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

Description

Value

Unit

V

Voltage on V Pins

DD

–0.5 to 2.9

V

DD

V

Voltage in V

Pins

–0.5 to V

V

DDQ

REF

DD

V

–0.5 to V

REF

DDQ

V

–0.5 to V

+0.5 (≤ 2.9 V max.)

Voltage on I/O Pins

V

I/O

DDQ

V

+0.5 (≤ 2.9 V max.)

Voltage on Other Input Pins

Input Current on Any Pin

V

IN

I

+/–100

125

mA dc

IN

I

Output Current on Any I/O Pin

Maximum Junction Temperature

Storage Temperature

OUT

o

T

C

J

o

T

–55 to 125

C

STG

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect

reliability of this component.

Recommended Operating Conditions

Power Supplies

Parameter

Supply Voltage

Symbol

Min.

1.7

Typ.

1.8

Max.

Unit

V

1.95

V

DD

V

I/O Supply Voltage

Reference Voltage

1.4

1.5

DDQ

DD

V

0.68

—

0.95

REF

Notes:

1. The power supplies need to be powered up simultaneously or in the following sequence: V , V , V , followed by signal

DD DDQ REF

inputs. The power down sequence must be the reverse. V

must not exceed V .

DD

DDQ

2. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The

part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance

specifications quoted are evaluated for worst case in the temperature range marked on the device.

Operating Temperature

Parameter

Symbol

Min.

Typ.

Max.

Unit

Ambient Temperature

(Commercial Range Versions)

T

0

25

70

°C

A

Ambient Temperature

(Industrial Range Versions)

T

–40

25

85

°C

A

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Preliminary

GS8342Q08/09/18/36E-300/250/200/167

HSTL I/O DC Input Characteristics

Parameter

DC Input Logic High

Symbol

Min

Max

Units

Notes

V

(dc)

V

+ 0.1

V

+ 0.3

DD

V

1

IH

REF

V (dc)

V

– 0.1

REF

DC Input Logic Low

–0.3

IL

Notes:

1. Compatible with both 1.8 V and 1.5 V I/O drivers

2. These are DC test criteria. DC design criteria is V

± 50 mV. The AC V /V levels are defined separately for measuring timing param-

REF

IH IL

eters.

3. V (Min)DC = –0.3 V, V (Min)AC = –1.5 V (pulse width ≤ 3 ns).

IL

4.

V

(Max)DC = V

+ 0.3 V, V (Max)AC = V

+ 0.85 V (pulse width ≤ 3 ns).

DDQ

IH

DDQ

IH

HSTL I/O AC Input Characteristics

Parameter

AC Input Logic High

Symbol

Min

Max

Units

mV

Notes

3,4

V

(ac)

V

+ 200

REF

—

IH

V (ac)

V

– 200

REF

AC Input Logic Low

—

mV

3,4

IL

V

Peak to Peak AC Voltage

V

(ac)

5% V

(DC)

REF

—

mV

1

REF

Notes:

1. The peak to peak AC component superimposed on V

may not exceed 5% of the DC component of V

.

REF

2. To guarantee AC characteristics, V ,V , Trise, and Tfall of inputs and clocks must be within 10% of each other.

IH IL

3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKHKH

V

+ 1.0 V

DD

V

SS

50%

V

DD

V

– 1.0 V

SS

20% tKHKH

V

IL

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Preliminary

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Capacitance

o

(T = 25 C, f = 1 MHZ, V = 1.8 V)

A

DD

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

pF

C

V

= 0 V

Input Capacitance

Output Capacitance

Clock Capacitance

4

6

5

7

6

IN

C

V

OUT

= 0 V

pF

OUT

C

V = 0 V

IN

pF

CLK

Note:

This parameter is sample tested.

AC Test Conditions

Parameter

Conditions

1.25 V

Input high level

Input low level

0.25 V

2 V/ns

0.75 V

Max. input slew rate

Input reference level

Output reference level

V

/2

DDQ

Note:

Test conditions as specified with output loading as shown unless otherwise noted.

AC Test Load Diagram

DQ

RQ = 250 Ω (HSTL I/O)

V

= 0.75 V

REF

50Ω

VT = V /2

DDQ

Input and Output Leakage Characteristics

Parameter

Symbol

Test Conditions

Min.

Max

Notes

Input Leakage Current

(except mode pins)

I

V = 0 to V

IN DD

–2 uA

2 uA

IL

V

≥ V ≥ V

IN

–2 uA

2 uA

DD

IL

I

Doff

INDOFF

0 V ≤ V ≤ V

IN

Output Disable,

= 0 to V

I

Output Leakage Current

–2 uA

2 uA

OL

V

OUT

DDQ

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Preliminary

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Programmable Impedance HSTL Output Driver DC Electrical Characteristics

Parameter

Symbol

Min.

Max.

Units Notes

V

/2 – 0.12

V

/2 + 0.12

DDQ

Output High Voltage

Output Low Voltage

Output High Voltage

V

1, 3

2, 3

4, 5

4, 6

OH1

DDQ

V

/2 – 0.12

– 0.2

/2 + 0.12

DDQ

OL1

DDQ

V

DDQ

OH2

DDQ

V

Output Low Voltage

Vss

0.2

OL2

Notes:

1.

I

= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).

DDQ OH DDQ

OH

2.

I

= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).

OL

DDQ

OL

DDQ

3. Parameter tested with RQ = 250Ω and V

= 1.5 V or 1.8 V

DDQ

4. Minimum Impedance mode, ZQ = V

SS

5.

6.

I

= –1.0 mA

= 1.0 mA

OH

OL

Operating Currents

-300

-250

-200

-167

Parameter

Symbol

Test Conditions

Notes

0

to

–40

to

0

to

–40

to

0

to

–40

to

0

to

–40

to

70°C

85°C

70°C

85°C

70°C

85°C

70°C

85°C

V_DD= Max, I_OUT= 0 mA

I_DD

Operating Current (x36): DDR

Operating Current (x18): DDR

Operating Current (x9): DDR

Operating Current (x8): DDR

900 mA 920 mA 800 mA 820 mA 670 mA 690 mA 590 mA 610 mA

840 mA 860 mA 740 mA 760 mA 620 mA 640 mA 550 mA 570 mA

2, 3

Cycle Time ≥ t_KHKHMin

V_DD= Max, I_OUT= 0 mA

Cycle Time ≥ t_KHKHMin

V_DD= Max, I_OUT= 0 mA

Cycle Time ≥ t_KHKHMin

V_DD= Max, I_OUT= 0 mA

Cycle Time ≥ t_KHKHMin

Device deselected,

I_OUT= 0 mA, f = Max,

I_SB1

Standby Current (NOP): DDR

330 mA 340 mA 300 mA 310 mA 280 mA 290 mA 260 mA 270 mA

2, 4

All Inputs ≤ 0.2 V or ≥ V_DD– 0.2 V

Notes:

1.

2.

Power measured with output pins floating.

Minimum cycle, I_OUT= 0 mA

Operating current is calculated with 50% read cycles and 50% write cycles.

Standby Current is only after all pending read and write burst operations are completed.

3.

4.

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Preliminary

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AC Electrical Characteristics

-300

-250

-200

-167

Parameter

Symbol

Units

Notes

Min

Max

Min

Max

Min

Max

Min

Max

Clock

t_KHKH

t_CHCH

K, K Clock Cycle Time

C, C Clock Cycle Time

3.3

—

4.2

0.2

—

4.0

—

6.3

0.2

—

5.0

—

7.9

0.2

—

6.0

—

8.4

0.2

—

ns

t_KCVar

tKC Variable

5

t_KHKL

t_CHCL

K, K Clock High Pulse Width

C, C Clock High Pulse Width

1.32

1.6

2.0

2.4

t_KLKH

t_CLCH

K, K Clock Low Pulse Width

C, C Clock Low Pulse Width

1.32

1.49

—

1.6

1.8

—

2.0

2.2

—

2.4

2.7

—

ns

K to K High

C to C High

t_KHKH

t_KHCH

t_KCLock

t_KCReset

K, K Clock High to C, C Clock High

DLL Lock Time

0

1.45

—

0

1.8

—

0

2.3

—

0

2.8

—

ns

cycle

ns

1024

30

1024

30

1024

30

1024

30

6

K Static to DLL reset

—

Output Times

t_KHQV

t_CHQV

K, K Clock High to Data Output Valid

C, C Clock High to Data Output Valid

—

0.45

—

0.45

—

0.45

—

–0.5

—

0.5

—

ns

3

t_KHQX

t_CHQX

K, K Clock High to Data Output Hold

C, C Clock High to Data Output Hold

–0.45

—

–0.45

—

–0.45

—

t_KHCQV

t_CHCQV

K, K Clock High to Echo Clock Valid

C, C Clock High to Echo Clock Valid

0.45

—

0.45

—

0.45

—

0.5

—

t_KHCQX

t_CHCQX

K, K Clock High to Echo Clock Hold

C, C Clock High to Echo Clock Hold

–0.45

–0.5

t_CQHQV

t_CQHQX

t_KHQZ

t_CHQZ

t_KHQX1

t_CHQX1

CQ, CQ High Output Valid

CQ, CQ High Output Hold

—

0.27

—

0.30

—

0.35

—

0.40

—

ns

7

–0.27

–0.30

–0.35

–0.40

K Clock High to Data Output High-Z

C Clock High to Data Output High-Z

—

0.45

—

0.45

—

0.45

—

0.5

—

ns

3

K Clock High to Data Output Low-Z

C Clock High to Data Output Low-Z

–0.45

–0.5

Setup Times

t_AVKH

t_IVKH

Address Input Setup Time

0.3

—

0.35

—

0.4

—

0.5

—

ns

Control Input Setup Time

Data Input Setup Time

2

t_DVKH

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Preliminary

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AC Electrical Characteristics (Continued)

-300

-250

-200

-167

Parameter

Symbol

Units

Notes

Min

Max

Min

Max

Min

Max

Min

Max

Hold Times

t_KHAX

t_KHIX

Address Input Hold Time

0.3

—

0.35

—

0.4

—

0.5

—

ns

Control Input Hold Time

t_KHDX

Data Input Hold Time

Notes:

1.

2.

3.

4.

All Address inputs must meet the specified setup and hold times for all latching clock edges.

Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).

If C, C are tied high, K, K become the references for C, C timing parameters

To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN

parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two

SRAMs on the same board to be at such different voltages and temperatures.

5.

6.

Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

V_DDslew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V_DDand input clock are stable.

7.

Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard

bands and test setup variations.

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Preliminary

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Preliminary

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Preliminary

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JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with the current IEEE Standard, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output

DD

drivers are powered by V

.

DD

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

DD

SS

JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TCK

Test Clock

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

TMS

TDI

Test Mode Select

Test Data In

In controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in

Out response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

TDO

Test Data Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up.

JTAG Port Registers

Overview

The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

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Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

·

Boundary Scan Register

·

0

Bypass Register

2

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1

0

·

· · ·

Control Signals

Test Access Port (TAP) Controller

TMS

TCK

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

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Preliminary

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ID Register Contents

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

0

1

x36

x18

x9

X

0

1

0

1

0

1

0

1

0

1

0

1

0

0 1 1 0 1 1 0 0 1

x8

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

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Preliminary

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JTAG Tap Controller State Diagram

Test Logic Reset

0

1

Run Test Idle

Select DR

0

Select IR

0

1

Capture DR

0

Capture IR

0

Shift DR

1

Shift IR

1

0

Exit1 DR

0

Exit1 IR

0

Pause DR

1

Pause IR

1

0

Exit2 DR

1

Exit2 IR

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This

occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-

tate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is

loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and

I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and

are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because

the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will

not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the

TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP

operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then

places the boundary scan register between the TDI and TDO pins.

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EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with

all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is

still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.

Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output

drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-

tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-

ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR

state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-

ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction

EXTEST

Code

000

Description

Notes

1

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

IDCODE

001

1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z

010

TDO.

1

Forces all RAM output drivers to High-Z.

RFU

011

100

Do not use this instruction; Reserved for Future Use.

1

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

RFU

101

110

111

Do not use this instruction; Reserved for Future Use.

Places Bypass Register between TDI and TDO.

1

BYPASS

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

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JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Power Supply Voltage

Input High Voltage

Input Low Voltage

Symbol

Min.

1.7

Typ.

1.8

—

Max.

Unit

V

1.9

V

DDQ

V

+ 0.3

DDQ

1.3

IH

V

–0.3

1.4

—

0.5

IL

Output High Voltage (I = –2 mA)

V

DDQ

—

OH

Output Low Voltage (I = 2 mA)

V

0.4

OL

SS

Note:

The input level of SRAM pin is to follow the SRAM DC specification.

JTAG Port AC Test Conditions

Parameter

Symbol

Min

Unit

V /V

Input High/Low Level

Input Rise/Fall Time

1.3/0.5

1.0/1.0

0.9

V

ns

V

IH IL

TR/TF

Input and Output Timing Reference Level

Notes:

1. Distributed scope and test jig capacitance.

2. Test conditions as shown unless otherwise noted.

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JTAG Port Timing Diagram

tTKC

tTKH

tTKL

TCK

TDI

tTH

tTS

TMS

TDO

tTKQ

tTH

tTS

Parallel SRAM input

JTAG Port AC Electrical Characteristics

Parameter

Symbol

Min.

50

20

5

Max

—

10

Unit

ns

t

TCK Cycle Time

CHCH

t

TCK High Pulse Width

TCK Low Pulse Width

TMS Input Setup Time

TMS Input Hold Time

TDI Input Setup Time

TDI Input Hold Time

SRAM Input Setup Time

SRAM Input Hold Time

Clock Low to Output Valid

CHCL

CLCH

t

MVCH

CHMX

5

t

5

DVCH

CHDX

5

t

5

SVCH

CHSX

5

t

0

CLQV

Rev: 1.02 8/2005

30/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8342Q08/09/18/36E-300/250/200/167

Package Dimensions—165-Bump FPBGA (Package E; Variation 1)

A1

1

TOP VIEW

BOTTOM VIEW

A1

M

Ø0.10

Ø0.25 C AB

C

Ø0.44~0.64(165x)

2

3 4 5 6 7 8 9 10 11

11 10 9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

I

G

H

J

K

L

M

N

P

K

L

M

N

P

R

A

1.0

10.0

1.0

15±0.05

B

0.20(4x)

SEATING PLANE

C

Rev: 1.02 8/2005

31/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8342Q08/09/18/36E-300/250/200/167

Ordering Information—GSI SigmaQuad-II SRAM

Speed

(MHz)

3

1

Org

Type

Package

Status

T

Part Number

A

1M x 36

2M x 18

4M x 9

GS8342Q36E-300

GS8342Q36E-250

GS8342Q36E-200

GS8342Q36E-167

GS8342Q36E-300I

GS8342Q36E-250I

GS8342Q36E-200I

GS8342Q36E-167I

GS8342Q18E-300

GS8342Q18E-250

GS8342Q18E-200

GS8342Q18E-167

GS8342Q18E-300I

GS8342Q18E-250I

GS8342Q18E-200I

GS8342Q18E-167I

GS8342Q09E-300

GS8342Q09E-250

GS8342Q09E-200

GS8342Q09E-167

GS8342Q09E-300I

GS8342Q09E-250I

GS8342Q09E-200I

GS8342Q09E-167I

GS8342Q08E-300

GS8342Q08E-250

GS8342Q08E-200

GS8342Q08E-167

GS8342Q08E-300I

SigmaQuad-II SRAM

165-Pin BGA (E, var. 1)

300

250

200

167

300

250

200

167

300

250

200

167

300

250

200

167

300

250

200

167

300

250

200

167

300

250

200

167

300

C

I

ES

I

C

I

C

I

4M x 9

I

4M x 9

I

4M x 9

I

4M x 8

C

I

4M x 8

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8342x36E-200T.

2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

3. MP = Mass Production. PQ = Pre-Qualification. ES = Engineering Samples.

Rev: 1.02 8/2005

32/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8342Q08/09/18/36E-300/250/200/167

Ordering Information—GSI SigmaQuad-II SRAM

Speed

(MHz)

3

1

Org

Type

Package

Status

T

Part Number

A

4M x 8

GS8342Q08E-250I

GS8342Q08E-200I

GS8342Q08E-167I

SigmaQuad-II SRAM

165-Pin BGA (E, var. 1)

250

200

167

I

ES

RoHS-compliant

165-Pin BGA (E, var. 1)

1M x 36

2M x 18

GS8342Q36GE-300

GS8342Q36GE-250

GS8342Q36GE-200

GS8342Q36GE-167

GS8342Q36GE-300I

GS8342Q36GE-250I

GS8342Q36GE-200I

GS8342Q36GE-167I

GS8342Q18GE-300

GS8342Q18GE-250

GS8342Q18GE-200

GS8342Q18GE-167

GS8342Q18GE-300I

GS8342Q18GE-250I

GS8342Q18GE-200I

GS8342Q18GE-167I

SigmaQuad-II SRAM

300

250

200

167

300

250

200

167

300

250

200

167

300

250

200

167

C

I

ES

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

I

RoHS-compliant

165-Pin BGA (E, var. 1)

I

RoHS-compliant

165-Pin BGA (E, var. 1)

I

RoHS-compliant

165-Pin BGA (E, var. 1)

C

I

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

I

RoHS-compliant

165-Pin BGA (E, var. 1)

I

RoHS-compliant

165-Pin BGA (E, var. 1)

I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8342x36E-200T.

2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

3. MP = Mass Production. PQ = Pre-Qualification. ES = Engineering Samples.

Rev: 1.02 8/2005

33/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8342Q08/09/18/36E-300/250/200/167

Ordering Information—GSI SigmaQuad-II SRAM

Speed

(MHz)

3

1

Org

Type

Package

Status

T

Part Number

A

RoHS-compliant

165-Pin BGA (E, var. 1)

4M x 9

4M x 8

GS8342Q09GE-300

GS8342Q09GE-250

GS8342Q09GE-200

GS8342Q09GE-167

GS8342Q09GE-300I

GS8342Q09GE-250I

GS8342Q09GE-200I

GS8342Q09GE-167I

GS8342Q08GE-300

GS8342Q08GE-250

GS8342Q08GE-200

GS8342Q08GE-167

GS8342Q08GE-300I

GS8342Q08GE-250I

GS8342Q08GE-200I

GS8342Q08GE-167I

SigmaQuad-II SRAM

300

250

200

167

300

250

200

167

300

250

200

167

300

250

200

167

C

I

ES

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

I

RoHS-compliant

165-Pin BGA (E, var. 1)

I

RoHS-compliant

165-Pin BGA (E, var. 1)

I

RoHS-compliant

165-Pin BGA (E, var. 1)

C

I

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

RoHS-compliant

165-Pin BGA (E, var. 1)

I

RoHS-compliant

165-Pin BGA (E, var. 1)

I

RoHS-compliant

165-Pin BGA (E, var. 1)

I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8342x36E-200T.

2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

3. MP = Mass Production. PQ = Pre-Qualification. ES = Engineering Samples.

Rev: 1.02 8/2005

34/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS8342Q09GE-250I
厂家：	GSI TECHNOLOGY
描述：	36Mb SigmaQuad-II Burst of 4 SRAM 4 SRAM 36MB SigmaQuad -II突发静态存储器
文件：	总34页 (文件大小：1718K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS8342Q09GE-250I [GSI]

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