GS840E32AGT-166_技术文档

GS840E18/32/36AT/B-190/180/166/150/100

190 MHz–100 MHz

TQFP, BGA

Commercial Temp

Industrial Temp

256K x 18, 128K x 32, 128K x 36

4Mb Sync Burst SRAMs

3.3 V V

DD

3.3 V and 2.5 V I/O

counter may be configured to count in either linear or

Features

interleave order with the Linear Burst Order (LBO) input. The

burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

• FT pin for user-configurable flow through or pipelined

operation

• Dual Cycle Deselect (DCD) operation

• 3.3 V +10%/–5% core power supply

Flow Through/Pipeline Reads

• 2.5 V or 3.3 V I/O supply

The function of the Data Output register can be controlled by

the user via the FT mode pin/bump (pin 14 in the TQFP and

bump 5R in the BGA). Holding the FT mode pin/bump low

places the RAM in Flow Through mode, causing output data to

bypass the Data Output Register. Holding FT high places the

RAM in Pipelined mode, activating the rising-edge-triggered

Data Output Register.

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock control, registered, address, data, and control

• Internal self-timed write cycle

DCD Pipelined Reads

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP or 119-Bump BGA package

• Pb-Free 100-lead TQFP package available

The GS840E18/32/36A is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. SCD (Single Cycle Deselect)

versions are also available. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of

clock.

Functional Description

Applications

The GS840E18/32/36A is a 4,718,592-bit (4,194,304-bit for

x32 version) high performance synchronous SRAM with a 2-

bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications ranging from DSP main store

to networking chip set support. The GS84018/32/36A is

available in a JEDEC standard 100-lead TQFP or 119-Bump

BGA package.

Byte Write and Global Write

Byte write operation is performed by using byte write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enables (E¹, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

Core and Interface Voltages

The GS840E18/32/36A operates on a 3.3 V power supply and

all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

) pins are used to de-couple output noise

DDQ

from the internal circuit.

Parameter Synopsis

–190

–180

–166

–150

–100

tCycle 5.3 ns 5.5 ns 6.0 ns 6.6 ns

10 ns

Pipeline

3-1-1-1

t^KQ

3.0 ns 3.0 ns 3.5 ns 3.8 ns 4.5 ns

370 mA 335 mA 310 mA 280 mA 190 mA

IDD

Flow

t^KQ

7.5 ns

8 ns

9 ns

8.5 ns

10 ns

12 ns

15 ns

Through tCycle 8.5 ns

2-1-1-1 I^DD

245 mA 210 mA 190 mA 165 mA 135 mA

Rev: 1.12 10/2004

1/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

GS840E18A 100-Pin TQFP Pinout (Package T)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

A

NC

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

V

NC

V

DDQ

SS

V

NC

V

SS

NC

DQPA

DQA

DQB

DQB2

256K x 18

Top View

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

VDDQ

DQ^A

V

DDQ

DQB

FT

DQA

V

SS

NC

V

DD

VDD

ZZ

NC

V

SS

DQ^A

DQA

VDDQ

DQB

V

DDQ

V

SS

DQA

NC

DQB

DQPB

NC

V

VDDQ

NC

V

SS

V

DDQ

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Rev: 1.12 10/2004

2/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

GS840E32A 100-Pin TQFP Pinout (Package T)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

NC

DQB

DQ^B

V

NC

DQC

DQ^C

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V

DDQ

V

SS

DQB

DQC

DQ^C

DQC

128K x 32

Top View

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

DDQ

SS

V

DDQ

DQB

DQC

V

FT

SS

NC

V

DD

V

ZZ

NC

DD

V

SS

DQ^A

DQA

V

DQD

V

DDQ

SS

V

SS

DQA

DQD

V

SS

DDQ

SS

V

DDQ

DQA

NC

DQD

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Rev: 1.12 10/2004

3/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

GS840E36A 100-Pin TQFP Pinout (Package T)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

DQPB

DQB

DQPC

DQC

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQB

DQC

V

DDQ

SS

V

SS

DQB

DQC

128K x 36

Top View

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

DDQ

SS

V

DDQ

DQB

DQC

FT

V

SS

NC

V

DD

V

ZZ

NC

DD

V

SS

DQ^A

DQA

DQD

DDQ

V

DDQ

SS

V

SS

DQA

DQD

V

SS

DDQ

SS

V

DDQ

DQA

DQD

DQA

DQD

DQPA

DQPD

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Rev: 1.12 10/2004

4/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

TQFP Pin Description

Symbol

A0, A1

A

Type

Description

I

Address field LSBs and Address Counter preset Inputs

Address Inputs

DQ^A

DQB

DQC

DQD

I/O

Data Input and Output pins

BW

B^A, BB

B^C, BD

CK

I

Byte Write—Writes all enabled bytes; active low

Byte Write Enable for DQA, DQB Data I/’s; active low

Byte Write Enable for DQC, DQD Data I/Os; active low

Clock Input Signal; active high

GW

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

E¹, E3

E²

Chip Enable; active high

G

Output Enable; active low

ADV

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

ADSP, ADSC

ZZ

FT

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Core power supply

LBO

V

DD

V

I

-

I/O and Core Ground

Output driver power supply

No Connect

SS

V

DDQ

NC

Rev: 1.12 10/2004

5/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

GS840E18A Pad Out—119-Bump BGA—Top View (Package B)

1

2

A

3

A

4

5

A

6

A

7

A

B

C

D

E

F

V

ADSP

ADSC

V

DDQ

NC

E

E3

NC

A

V

A

NC

DD

DQB

NC

DQB

NC

DQB

NC

V

NC

E1

V

DQPA

NC

DQA

NC

DQA

SS

DQA

V

G

V

DDQ

G

H

J

NC

BB

ADV

GW

NC

DQA

DQB

V

NC

SS

V

NC

V

NC

V

DDQ

DD

DDQ

K

L

NC

DQB

NC

DQB

NC

DQPB

A

V

CK

NC

BW

A1

V

NC

DQA

NC

DQA

NC

A

DQA

SS

DQB

NC

BA

NC

V

M

N

P

R

T

DDQ

SS

DDQ

DQB

V

NC

A0

DQA

NC

ZZ

LBO

A

V

FT

A

DD

A

NC

A

V

NC

V

U

DDQ

Rev: 1.12 10/2004

6/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

GS840E32A Pad Out—119-Bump BGA—Top View (Package B)

1

2

A

3

A

4

5

A

6

7

A

B

C

D

E

F

V

ADSP

ADSC

A

V

DDQ

NC

E

E3

NC

A

V

A

NC

DD

DQC

NC

DQC

V

NC

E1

V

NC

DQB

SS

V

G

V

DDQ

G

H

J

DQC

BC

ADV

GW

BB

DQB

DQC

V

DQB

SS

V

NC

V

NC

V

DDQ

DD

DDQ

K

L

DQD

NC

V

CK

NC

BW

A1

V

DQA

NC

DQA

SS

DQD

BD

BA

DQA

V

M

N

P

R

T

DDQ

SS

DDQ

DQD

V

DQA

DQD

NC

A0

DQA

NC

ZZ

A

LBO

A

V

FT

A

DD

NC

A

NC

V

NC

V

U

DDQ

Rev: 1.12 10/2004

7/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

GS840E36APad Out—119-Bump BGA—Top View (Package B)

1

2

A

3

A

4

5

A

6

A

7

A

B

C

D

E

F

V

ADSP

ADSC

V

DDQ

NC

E

E3

NC

A

V

A

NC

DD

DQC

DQPC

DQC

V

NC

E1

V

DQPB

DQB

SS

V

G

V

DDQ

G

H

J

DQC

BC

ADV

GW

BB

DQB

DQC

V

DQB

SS

V

NC

V

NC

V

DDQ

DD

DDQ

K

L

DQD

DQPD

A

V

CK

NC

BW

A1

V

DQA

DQPA

A

DQA

SS

DQD

BD

BA

DQA

V

M

N

P

R

T

DDQ

SS

DDQ

DQD

V

DQA

DQD

NC

A0

DQA

NC

ZZ

LBO

A

V

FT

A

DD

NC

A

NC

V

NC

V

U

DDQ

Rev: 1.12 10/2004

8/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

BGA Pin Description

Symbol

A0, A1

A

Type

Description

I

Address field LSBs and Address Counter Preset Inputs

Address Inputs

DQ^A

DQB

DQC

DQD

I/O

Data Input and Output pins

B^A, BB, BC, BD

I

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

Clock Input Signal; active high

CK

BW

Byte Write—Writes all enabled bytes; active low

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

GW

E¹, E3

E²

Chip Enable; active high

G

ADV

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

ADSP, ADSC

ZZ

FT

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Core power supply

LBO

V

DD

V

I

I/O and Core Ground

Output driver power supply

No Connect

SS

V

DDQ

NC

—

Rev: 1.12 10/2004

9/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

GS840E18/32/36A Block Diagram

^RegisteQ^r

A0–An

D

A0

A1

A0

A1

D0

D1

Counter

Load

Q0

Q1

A

LBO

ADV

CK

Memory

Array

ADSC

ADSP

Q

D

Register

GW

BW

BA

D

Q

Register

36

D

Q

BB

BC

BD

4

Register

D

Q

Register

D

Q

Register

D

Q

Register

E1

E3

E2

D

Q

Register

D

Q

FT

G

1

Power Down

Control

DQx0–DQx9

ZZ

Note: Only x36 version shown for simplicity.

Rev: 1.12 10/2004

10/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Mode Pin Functions

Mode Name

Name

State

Function

L

Linear Burst

Interleaved Burst

Flow Through

Pipeline

Burst Order Control

LBO

H or NC

L

Output Register Control

FT

H or NC

L or NC

H

Active

Power Down Control

ZZ

Standby, I = I

DD SB

Note:

There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will

operate in the default states as specified in the above tables.

Burst Counter Sequences

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

1st address

2nd address

3rd address

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

4th address

Note:

The burst counter wraps to initial state on the 5th clock.

Rev: 1.12 10/2004

11/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Byte Write Truth Table

Function

Read

GW

BW

H

L

B

A

B

C

B

D

Notes

1

H

L

X

H

L

X

H

L

X

H

L

X

H

L

Read

1

Write byte ^A

Write byte ^B

Write byte ^C

Write byte ^D

Write all bytes

L

2, 3

L

H

L

2, 3

L

H

L

2, 3, 4

L

H

L

X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs B^A, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “^C” and “D” are only available on the x32 and x36 versions.

Rev: 1.12 10/2004

12/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Synchronous Truth Table

Operation

State

Address

Used

2

3

4

Diagram

E1

ADSP ADSC ADV

E

W

DQ

5

Key

Deselect Cycle, Power Down

Read Cycle, Begin Burst

None

X

H

L

X

L

X

L

X

L

X

F

T

F

T

F

T

High-Z

F

T

X

High-Z

None

X

L

H

L

High-Z

External

X

L

Q

D

Q

D

Q

D

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

R

L

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

W

L

CR

CW

H

Current

H

Write Cycle, Suspend Burst

Notes:

1. X = Don’t Care, H = High, L = Low.

2. E = T (True) if E²= 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.12 10/2004

13/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Simplified State Diagram

X

Deselect

W

R

W

R

X

R

X

First Write

First Read

CW

CR

W

R

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.

2. The upper portion of the diagram assumes active use of only the Enable (E^1,E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs

and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes

ADSP is tied high and ADV is tied low.

Rev: 1.12 10/2004

14/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Simplified State Diagram with G

X

Deselect

W

R

W

R

X

W

R

X

First Write

First Read

CR

CW

CR

W

R

W

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.12 10/2004

15/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

Description

Value

Unit

V

Voltage on V Pins

–0.5 to 4.6

DD

V

Voltage in V

Pins

–0.5 to V

DD

V

DDQ

V

Voltage on Clock Input Pin

Voltage on I/O Pins

–0.5 to 6

+0.5 (≤ 4.6 V max.)

V

CK

I/O

V

–0.5 to V

V

DDQ

V

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

–0.5 to V +0.5 (≤ 4.6 V max.)

V

IN

DD

I

+/–20

mA

W

I

OUT

P

1.5

D

o

T

–55 to 125

STG

BIAS

C

o

T

Temperature Under Bias

C

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Recommended Operating Conditions

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

V

Supply Voltage

3.135

2.375

1.7

3.3

2.5

—

3.6

V

DD

V

I/O Supply Voltage

Input High Voltage

Input Low Voltage

1

2

3

DDQ

DD

V

+0.3

DD

V

IH

V

–0.3

0

—

0.8

V

IL

T

Ambient Temperature (Commercial Range Versions)

25

70

85

°C

A

T

Ambient Temperature (Industrial Range Versions)

–40

A

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ V

≤ 2.375 V

DDQ

(i.e., 2.5 V I/O) and 3.6 V ≤ V

≤ 3.135 V (i.e., 3.3 V I/O) and quoted at whichever condition is worst case.

DDQ

2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.

3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of

Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated

for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be –2 V > Vi < V +2 V with a pulse width not to exceed 20% tKC.

DD

Rev: 1.12 10/2004

16/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKC

V

+-2.0V

50%

DD

V

SS

50%

V

DD

V

-2.0V

SS

20% tKC

V

IL

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 3.3 V)

A

DD

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

C

V

= 3.3 V

= 0 V

Control Input Capacitance

Input Capacitance

3

4

6

4

5

7

pF

I

DD

C

V

IN

C

V

= 0 V

OUT

Output Capacitance

OUT

Note:

This parameter is sample tested.

Rev: 1.12 10/2004

17/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

AC Test Conditions

Parameter

Conditions

Input high level

Input low level

2.3 V

0.2 V

Input slew rate

1 V/ns

1.25 V

Fig. 1& 2

Input reference level

Output reference level

Output load

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output Load 2 for t , t , t and t

.

OHZ

LZ HZ OLZ

4. Device is deselected as defined by the Truth Table.

Output Load 2

2.5 V

Output Load 1

DQ

225Ω

DQ

*

50Ω

30pF

*

5pF

VT = 1.25 V

* Distributed Test Jig Capacitance

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I

V = 0 to V

IN DD

–1 uA

1uA

IL

V

≥ V ≥ V

–1 uA

1 uA

300 uA

DD

IN

IH

I

ZZ Input Current

INZZ

0V ≤ V ≤ V

IN

V

≥ V ≥ V

–300 uA

–1uA

1 uA

DD

IN

IL

I

Mode Pin Input Current

Output Leakage Current

INM

0V ≤ V ≤ V

IN

Output Disable,

V

I

–1 uA

1 uA

OL

= 0 to V

OUT

DD

V

I

= –4 mA, V

= 2.375 V

Output High Voltage

Output Low Voltage

1.7 V

2.4 V

OH

DDQ

V

= 3.135 V

OH

V

I

= 4 mA

0.4 V

OL

Rev: 1.12 10/2004

18/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Operating Currents

-190

-180

-166

-150

-100

0

to

–40

to

0

to

–40

to

0

to

–40

to

0

to

–40

to

0

to

–40

to

Parameter Test Conditions

Symbol

Unit

70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C

IDD

Pipeline

DeviceSelected;

370

245

20

380

255

30

335

210

20

345

220

30

310

190

20

320

200

30

280

165

20

290

175

30

190

135

20

200

145

30

mA

All other

Operating

Current

inputs

IDD

Flow

Through

≥VIH or ≤ VIL

Output open

ISB

Pipeline

ZZ ≥ VDD –

Standby

Current

ISB

Flow

Through

0.2 V

20

30

20

30

20

30

20

30

20

30

IDD

Pipeline

Device

Deselected;

All other

60

70

55

65

50

60

50

60

40

50

Deselect

Current

IDD

Flow

Through

inputs

45

55

40

50

40

50

35

45

35

45

≥ VIH or ≤ VIL

Rev: 1.12 10/2004

19/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

AC Electrical Characteristics

-190

-180

-166

-150

-100

Parameter

Symbol

Unit

Min

5.3

—

Max

—

Min

5.5

—

Max

—

Min

6.0

—

Max Min Max Min Max

Clock Cycle Time

tKC

tKQ

—

3.5

—

6.7

—

3.8

—

10

—

4.5

—

12.0

—

5

ns

Clock to Output Valid

3.0

—

3.0

—

Pipeline

1.5

Clock to Output Invalid

tKQX

1.5

8.5

—

1.5

9.0

—

1.5

10.0

—

1.5

15.0

—

1

Clock to Output in Low-Z

Clock Cycle Time

—

1.5

12.0

—

tLZ

tKC

tKQ

—

Clock to Output Valid

7.5

—

8.0

—

8.5

—

10.0

—

Flow

Through

Clock to Output Invalid

Clock to Output in Low-Z

Clock HIGH Time

tKQX

3.0

1.3

1.5

—

3.0

1.3

1.5

—

3.0

1.3

1.5

—

3.0

1.3

1.5

—

3.0

1.3

1.5

—

1

—

tLZ

tKH

tKL

—

Clock LOW Time

—

1

Clock to Output in High-Z

G to Output Valid

3.0

—

3.2

—

3.5

—

3.8

—

tHZ

tOE

5

1

G to output in Low-Z

0

—

tOLZ

1

G to output in High-Z

Setup time

—

1.5

0.5

5

3.0

—

1.5

0.5

5

3.2

—

1.5

0.5

5

3.5

—

1.5

0.5

5

3.8

—

2.0

0.5

5

ns

tOHZ

tS

tH

—

Hold time

2

ZZ setup time

tZZS

2

ZZ hold time

ZZ recovery

1

—

1

—

1

—

1

—

1

—

ns

tZZH

tZZR

20

Notes:

1. These parameters are sampled and are not 100% tested

2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Rev: 1.12 10/2004

20/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Pipeline Mode Timing

Begin

Read A Cont

Single Read

Cont

Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont

Deselect

Single Write

tKL

Burst Read

tKH

tKC

CK

ADSP

tS

tH

tS

ADSC initiated read

ADSC

ADV

tH

A

B

C

A0–An

GW

tS

tH

BW

tS

Ba–Bd

E1

tS

Deselected with E1

tH

E1 masks ADSP

tH

E2 and E3 only sampled with ADSP and ADSC

E2

E3

G

tS

D(B)

tKQ

tKQX

tHZ

Q(C+2) Q(C+3)

tOE

tOHZ

Q(A)

tH

tLZ

Q(C)

Q(C+1)

DQa–DQd

Rev: 1.12 10/2004

21/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Flow Through Mode Timing

Begin

Read A Cont

tKH

Cont

Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont

Deselect

tKL

tKC

CK

Fixed High

ADSP

tS

tH

tS

tH

ADSC initiated read

ADSC

ADV

A0–An

GW

tS

tH

tS

tH

A

B

C

tS

tH

tS

tH

BW

tS

tH

Ba–Bd

E1

tS

Deselected with E1

tH

E2 and E3 only sampled with ADSC

E2

tS

tH

E3

G

tH

tS

tKQ

tLZ

tHZ

tOE

tOHZ

D(B)

tKQX

Q(A)

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

Q(C)

DQa–DQd

Rev: 1.12 10/2004

22/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Sleep Mode Timing Diagram

tKH

tKC

tKL

CK

Setup

Hold

ADSP

ADSC

tZZR

tZZS

tZZH

ZZ

Application Tips

Single and Dual Cycle Deselect

SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output

drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there

will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on

dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address

boundary crossings), but greater care must be exercised to avoid excessive bus contention.

Rev: 1.12 10/2004

23/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

GS840E18/32/36A Output Driver Characteristics

60

40

Pull Down Drivers

20

V

DDQ

I Out

0

VOut

V

SS

-20

-40

-60

-80

Pull Up Drivers

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

V Out (Pull Down)

VDDQ - V Out (Pull Up)

3.6V PD LD

3.3V PD LD

3.1V PD LD

3.1V PU LD

3.3V PU LD

3.6V PU LD

Rev: 1.12 10/2004

24/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

TQFP Package Drawing (Package T)

θ

L

c

L1

Symbol

Description

Standoff

Min. Nom. Max

A1

A2

b

0.05

1.35

0.20

0.09

0.10

1.40

0.30

—

0.15

1.45

0.40

0.20

22.1

20.1

16.1

14.1

—

Body Thickness

Lead Width

c

Lead Thickness

D

Terminal Dimension 21.9

Package Body 19.9

Terminal Dimension 15.9

22.0

20.0

16.0

14.0

0.65

0.60

1.00

e

D1

E

b

E1

e

Package Body

Lead Pitch

13.9

—

L

Foot Length

Lead Length

Coplanarity

Lead Angle

0.45

—

0.75

—

L1

Y

A1

A2

E1

E

0.10

7°

θ

0°

—

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

Rev: 1.12 10/2004

25/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Package Dimensions—119-Bump FPBGA (Package B, Variation 1)

Pin #1 Corner

BOTTOM VIEW

S

A1

Ø0.10

C

S

Ø0.30 C A

B

Ø0.60~0.90 (119x)

1

2

3

4 5 6 7

Ø1.00(3x) REF

7

6

5

4 3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

B

0.70 REF

1.27

7.62

12.00

14±0.20

A

0.20(4x)

SEATING PLANE

C

Rev: 1.12 10/2004

26/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Ordering Information for GSI Synchronous Burst RAMS

2

Speed

3

1

Org

Type

Package

Status

T

Part Number

A

(MHz/ns)

256K x 18

128K x 32

128K x 36

256K x 18

128K x 32

128K x 36

GS840E18AT-190

GS840E18AT-180

GS840E18AT-166

GS840E18AT-150

GS840E18AT-100

GS840E32AT-190

GS840E32AT-180

GS840E32AT-166

GS840E32AT-150

GS840E32AT-100

GS840E36AT-190

GS840E36AT-180

GS840E36AT-166

GS840E36AT-150

GS840E36AT-100

GS840E18AT-190I

GS840E18AT-180I

GS840E18AT-166I

GS840E18AT-150I

GS840E18AT-100I

GS840E32AT-190I

GS840E32AT-180I

GS840E32AT-166I

GS840E32AT-150I

GS840E32AT-100I

GS840E36AT-190I

GS840E36AT-180I

GS840E36AT-166I

GS840E36AT-150I

GS840E36AT-100I

DCD Pipeline/Flow Through

TQFP

190/7.5

180/8

C

I

166/8.5

150/10

100/12

190/7.5

180/8

166/8.5

150/10

100/12

190/7.5

180/8

166/8.5

150/10

100/12

190/7.5

180/8

I

166/8.5

150/10

100/12

190/7.5

180/8

I

C

I

166/8.5

150/10

100/12

190/7.5

180/8

I

C

I

166/8.5

150/10

100/12

I

C

128K x 36

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840E32AT-8T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow through mode-selectable by the user.

3. T^A= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.12 10/2004

27/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Ordering Information for GSI Synchronous Burst RAMS (Continued)

2

Speed

3

1

Org

Type

Package

Status

T

Part Number

A

(MHz/ns)

190/7.5

180/8

256K x 18

128K x 32

128K x 36

GS840E18AGT-190

GS840E18AGT-180

GS840E18AGT-166

GS840E18AGT-150

GS840E18AGT-100

GS840E32AGT-190

GS840E32AGT-180

GS840E32AGT-166

GS840E32AGT-150

GS840E32AGT-100

GS840E36AGT-190

GS840E36AGT-180

GS840E36AGT-166

GS840E36AGT-150

GS840E36AGT-100

DCD Pipeline/Flow Through

Pb-free TQFP

119 BGA (var. 1)

C

I

166/8.5

150/10

100/12

190/7.5

180/8

166/8.5

150/10

100/12

190/7.5

180/8

166/8.5

150/10

100/12

190/7.5

180/8

256K x 18 GS840E18AGT-190I

256K x 18 GS840E18AGT-180I

256K x 18 GS840E18AGT-166I

256K x 18 GS840E18AGT-150I

256K x 18 GS840E18AGT-100I

128K x 32 GS840E32AGT-190I

128K x 32 GS840E32AGT-180I

128K x 32 GS840E32AGT-166I

128K x 32 GS840E32AGT-150I

128K x 32 GS840E32AGT-100I

128K x 36 GS840E36AGT-190I

128K x 36 GS840E36AGT-180I

128K x 36 GS840E36AGT-166I

128K x 36 GS840E36AGT-150I

128K x 36 GS840E36AGT-100I

I

166/8.5

150/10

100/12

190/7.5

180/8

I

C

I

166/8.5

150/10

100/12

190/7.5

180/8

I

C

I

166/8.5

150/10

100/12

190/7.5

I

C

256K x 18

GS840E18AB-190

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840E32AT-8T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow through mode-selectable by the user.

3. T^A= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.12 10/2004

28/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

Ordering Information for GSI Synchronous Burst RAMS (Continued)

2

Speed

3

1

Org

Type

Package

Status

T

Part Number

A

(MHz/ns)

256K x 18

128K x 32

128K x 36

256K x 18

128K x 32

128K x 36

GS840E18AB-180

GS840E18AB-166

GS840E18AB-150

GS840E18AB-100

GS840E32AB-190

GS840E32AB-180

GS840E32AB-166

GS840E32AB-150

GS840E32AB-100

GS840E36AB-190

GS840E36AB-180

GS840E36AB-166

GS840E36AB-150

GS840E36AB-100

GS840E18AB-190I

GS840E18AB-180I

GS840E18AB-166I

GS840E18AB-150I

GS840E18AB-100I

GS840E32AB-190I

GS840E32AB-180I

GS840E32AB-166I

GS840E32AB-150I

GS840E32AB-100I

GS840E36AB-190I

GS840E36AB-180I

GS840E36AB-166I

GS840E36AB-150I

GS840E36AB-100I

DCD Pipeline/Flow Through

119 BGA (var. 1)

180/8

C

I

166/8.5

150/10

100/12

190/7.5

180/8

166/8.5

150/10

100/12

190/7.5

180/8

166/8.5

150/10

100/12

190/7.5

180/8

I

166/8.5

150/10

100/12

190/7.5

180/8

I

C

I

166/8.5

150/10

100/12

190/7.5

180/8

I

C

I

166/8.5

150/10

100/12

I

C

128K x 36

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840E32AT-8T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow through mode-selectable by the user.

3. T^A= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.12 10/2004

29/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

4Mb Burst SRAM Revision History

Types of Changes

Rev. Code: Old;

Page /Revisions;Reason

New

Format or Content

Format/Typos

Content

• Document/Continued changing to new format.

• Added Fine Pitch BGA Package.

GS840E18/32/36 Rev 1.02c 5/

1999;

GS840E18/32/36 2.00 8/1999D

• Took “E” out of 840HE...in Core and Interface Voltages.

• Pin outs/New small caps format.

Format/Typos

• Timing Diagrams/New format.

• Block Diagrams/New small caps format.

GS840E18/32/362.00 8/

1999;GS840E18/32/362.01 9/

1999E

• Pin outs/x32 & x36 TQFP/Changed pin 72 from DQA3 to

DQB3.

• Pin Description/Rearranged Address Inputs to match order on

TQFP Pinout.

Content

• TQFP Package Diagram/Corrected Dimension D Max from

20.1 to 22.1.

• Took out Fine Pitch BGA Package. Package change in

progress.

GS840E18/32/362.01 9/

1999E;GS840E18/32/362.02

• New GSI Logo

GS840E18/32/362.0210-11/

1999;GS840E18/32/362.032/

2000G

• Took “Pin” out of heading for consistency.

Format

• Updated pin description table

GS840E18/32/362.032/2000G;

840E18_r1_04

Content

• Updated BGA pin description table to meet JEDEC standard

840E18_r1_04; 840E18_r1_05

• Added “non-A” speed bins to Operating Currents table, AC

Electrical Characteristics table, and Ordering Information

table

840E18A_r1_05; 840E18A_r1_06

Content/Format

• Updated format to fit Technical Documentation standards

• Updated table on page 1

• Updated Operating Currents table on page 18

• Updated Electrical Characteristics table on page 19

• Updated format to comply with present Technical

Documentation standards

840E18A_r1_06; 840E18A_r1_07

Content/Format

• Corrected typos in revision history table on page 31

• Reduced I by 20 mA in table on page 1 and Operating

Currents table

• Removed 200 MHz references from entire datasheet

DD

840E18A_r1_07, 840E18A_r1_08

840E18A_r1_08, 840E18A_r1_09

840E18A_r1_09, 840E18A_r1_10

Content

• Updated format

• Added 190 MHz speed bin

Rev: 1.12 10/2004

30/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840E18/32/36AT/B-190/180/166/150/100

4Mb Burst SRAM Revision History

Types of Changes

Format or Content

Rev. Code: Old;

Page /Revisions;Reason

New

• Updated entire format

840E18A_r1_10, 840E18A_r1_11

840E18A_r1_11, 840E18A_r1_12

Content

• Corrected current numbers to match NBT parts

• Removed Preliminary banner

• Added Pb-free TQFP information

Content

• Added variation number to 119 BGA information

Rev: 1.12 10/2004

31/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS840E32AGT-166
厂家：	GSI TECHNOLOGY
描述：	256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs 256K ×18 ， 128K ×32 ， 128K ×36的4Mb同步突发静态存储器存储静态存储器
文件：	总31页 (文件大小：765K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS840E32AGT-166 [GSI]

相关型号：

GS840E32AGT-166I

GS840E32AGT-166T

GS840E32AGT-180

GS840E32AGT-180I

GS840E32AGT-180T

GS840E32AGT-190

GS840E32AGT-190I

GS840E32AGT-190IT

GS840E32AGT-190T

GS840E32AT-100

GS840E32AT-100I

GS840E32AT-150