GS840FH32AT-12T_技术文档

GS840FH18/32/36AT-8/8.5/10/12

8 ns–12 ns

TQFP

Commercial Temp

Industrial Temp

256K x 18, 128K x 32, 128K x 36

4Mb Sync Burst SRAMs

3.3 V V

DD

3.3 V and 2.5 V I/O

counter may be configured to count in either linear or

Features

• Flow Through mode operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

interleave order with the Linear Burst Order (LBO) input. The

burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

Designing For Compatibility

The JEDEC standard for Burst RAMs calls for a FT mode pin

option (Pin 14 on TQFP). Board sites for flow through Burst

RAMs should be designed with V connected to the FT pin

SS

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP

location to ensure the broadest access to multiple vendor

sources. Boards designed with FT pin pads tied low may be

stuffed with GSI’s pipeline/flow through-configurable Burst

RAMs or any vendor’s flow through or configurable Burst

SRAM. Bumps designed with the FT pin location tied high or

floating must employ a non-configurable flow through Burst

RAM, (e.g., GS840FH18/32/36A), to achieve flow through

functionality.

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS840FH18/32/36A is a 4,718,592-bit (4,194,304-bit for

x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications ranging from DSP main store

to networking chip set support. The GS840FH18/32/36A is

available in a JEDEC-standard 100-lead TQFP package.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the byte write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

Core and Interface Voltages

The GS840FH18/32/36A operates on a 3.3 V power supply

and all inputs/outputs are 3.3 V- and 2.5 V-compatible.

Separate output power (V

) pins are used to decouple

DDQ

output noise from the internal circuit.

Parameter Synopsis

-8

-8.5

-10

-12

Flow

tKQ

8 ns

8.5 ns

10 ns

12 ns

15 ns

Through tCycle 9 ns

2-1-1-1

IDD

210 mA 190 mA 165 mA 135 mA

Rev: 1.08 4/2007

1/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

GS840FH18 100-Pin TQFP Pinout

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

A

NC

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

V

NC

DQPA

DQA

V

DQA

V

NC

V

ZZ

DQ^A

DQA

V

DDQ

V

SS

NC

DQB

256K x 18

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

Top View

V

DDQ

DQB

NC

SS

V

DD

NC

DD

V

SS

DQB

V

DDQ

V

SS

DQA

NC

V

DQB

DQPB

NC

V

SS

V

DDQ

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Note:

Pins marked with NC can be tied to either V or V . These pins can also be left floating.

DD

SS

Rev: 1.08 4/2007

2/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

GS84FH32 100-Pin TQFP Pinout

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

NC

DQB

DQ^B

V

NC

DQC

DQ^C

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V

DDQ

V

SS

DQB

DQC

DQ^C

DQC

128K x 32

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

V

Top View

V

DDQ

DQB

DQC

NC

V

SS

NC

V

DD

V

NC

DD

ZZ

V

SS

DQ^A

DQA

V

DQD

V

DDQ

V

SS

DQA

DQD

V

SS

V

DDQ

DQA

NC

DQD

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Note:

Pins marked with NC can be tied to either V or V . These pins can also be left floating.

DD

SS

Rev: 1.08 4/2007

3/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

GS840FH36 100-Pin TQFP Pinout

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

DQPB

DQB

DQPC

DQC

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V

DDQ

V

SS

DQB

DQC

128K x 36

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

V

Top View

V

DDQ

DQB

DQC

NC

V

SS

NC

V

DD

V

NC

DD

ZZ

DQ^A

DQA

V

SS

DQD

V

DDQ

V

SS

DQA

DQD

V

SS

V

DDQ

DQA

DQPA

DQD

DQPD

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Note:

Pins marked with NC can be tied to either V or V . These pins can also be left floating.

DD

SS

Rev: 1.08 4/2007

4/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

TQFP Pin Description

Symbol

A0, A1

A

Type

Description

I

Address field LSBs and Address Counter preset Inputs

Address Inputs

BA

In

I

Byte Write signal for data inputs DQA; active low

Byte Write signal for data inputs DQB; active low

Byte Write signal for data inputs DQC; active low

Byte Write signal for data inputs DQD; active low

Byte Write—Writes all enabled bytes; active low

Clock Input Signal; active high

BB

BC

BD

BW

CK

I

GW

I

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

E1, E3

E2

I

Chip Enable; active high

G

I

Output Enable; active low

ADV

ADSP, ADSC

DQA

DQB

DQ

I

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Byte A Data Input and Output pins

Byte B Data Input and Output pins

Byte C Data Input and Output pins

Byte D Data Input and Output pins

9th Data I/O Pin; Byte A

I

I/O

I

DQD

DQPA

DQPB

DQPC

DQPD

ZZ

9th Data I/O Pin; Byte B

9th Data I/O Pin; Byte C

9th Data I/O Pin; Byte D

Sleep Mode control; active high

LBO

I

Linear Burst Order mode; active low

Core power supply

V

I

DD

V

I

I/O and Core Ground

Output driver power supply

No Connect

SS

V

DDQ

NC

—

Rev: 1.08 4/2007

5/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

GS840FH18/32/36A Block Diagram

Register

A0–An

D

Q

A0

A1

D0

D1

Q0

Q1

A1

Counter

Load

A

LBO

ADV

Memory

Array

CK

ADSC

ADSP

Q

D

Register

GW

BW

BA

D

Q

Register

36

D

Q

BB

BC

BD

4

Register

D

Q

Register

D

Q

Register

D

Q

Register

E1

E3

E2

D

Q

Register

D

Q

0

G

1

Power Down

Control

DQxn–DQxn

ZZ

Note: Only x36 version shown for simplicity.

Rev: 1.08 4/2007

6/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

Mode Pin Functions

Mode Name

Name

State

Function

L

Linear Burst

Interleaved Burst

Active

Burst Order Control

LBO

H or NC

L or NC

H

Power Down Control

ZZ

Standby, I = I

DD SB

Note:

There is a pull-up device on the LBO pin and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate

in the default states as specified in the above tables.

Burst Counter Sequences

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

1st address

2nd address

3rd address

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

4th address

Note:

The burst counter wraps to initial state on the 5th clock.

Byte Write Truth Table

Function

Read

GW

H

BW

H

L

B

A

B

C

B

D

Notes

1

X

H

L

X

H

L

X

H

L

X

H

L

Read

H

1

Write byte A

Write byte B

Write byte C

Write byte D

Write all bytes

H

L

2, 3

H

L

H

L

2, 3

H

L

H

L

2, 3, 4

H

L

H

L

H

L

X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x32 and x36 versions.

Rev: 1.08 4/2007

7/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

Synchronous Truth Table

Operation

State

Address

Used

2

3

4

Diagram

E1

ADSP ADSC ADV

E

W

DQ

5

Key

Deselect Cycle, Power Down

Read Cycle, Begin Burst

None

X

H

L

X

L

X

L

X

L

X

F

T

F

T

F

T

High-Z

F

T

X

High-Z

None

X

L

H

L

High-Z

External

X

L

Q

D

Q

D

Q

D

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

R

L

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

W

L

CR

CW

H

Current

H

Write Cycle, Suspend Burst

Notes:

1. X = Don’t Care, H = High, L = Low.

2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.08 4/2007

8/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

Simplified State Diagram

X

Deselect

W

R

W

R

X

R

X

CR

First Write

First Read

CW

CR

W

R

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E^1,E2, E3) and Write (BA, BB, BC, BD, BW, and GW) control

inputs and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and

assumes ADSP is tied high and ADV is tied low.

Rev: 1.08 4/2007

9/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

Simplified State Diagram with G

X

Deselect

W

R

W

R

X

W

R

X

CR

First Write

First Read

CR

CW

W

R

W

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.08 4/2007

10/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

Description

Value

Unit

V

Voltage on V Pins

–0.5 to 4.6

DD

V

Voltage in V

Pins

DDQ

–0.5 to 4.6

V

DDQ

V

–0.5 to V

+0.5 (≤ 4.6 V max.)

DDQ

Voltage on I/O Pins

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

V

I/O

V

–0.5 to V +0.5 (≤ 4.6 V max.)

V

IN

DD

I

+/–20

mA

W

IN

I

OUT

P

1.5

D

o

T

–55 to 125

C

STG

o

T

Temperature Under Bias

C

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Power Supply Voltage Ranges

Parameter

Symbol

Min.

3.0

Typ.

3.3

Max.

3.6

Unit

Notes

V

3.3 V Supply Voltage

V

DD

3.3 V V

I/O Supply Voltage

V

3.0

3.3

3.6

DDQ

DDQ3

2.5 V V

I/O Supply Voltage

V

2.3

2.5

2.7

DDQ2

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

Rev: 1.08 4/2007

11/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

Logic Levels

Parameter

Symbol

Min.

2.0

Typ.

—

Max.

Unit

V

Notes

1

V

Input High Voltage

Input Low Voltage

V

+ 0.3

DD

IH

V

–0.3

2.0

—

0.8

V

1

DD

IL

V

I/O Input High Voltage

I/O Input Low Voltage

I/O Input High Voltage

I/O Input Low Voltage

V

+ 0.3

—

V

1,3

DDQ3

IHQ3

DDQ

V

–0.3

0.6*V

—

0.8

V

DDQ3

ILQ3

V

+ 0.3

—

V

DDQ2

IHQ2

DD

DDQ

V

0.3*V

DD

–0.3

—

V

DDQ2

ILQ2

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

3.

V

(max) is voltage on V

pins plus 0.3 V.

DDQ

IHQ

Recommended Operating Temperatures

Parameter

Symbol

Min.

0

Typ.

25

Max.

70

Unit

°C

Notes

T

Ambient Temperature (Commercial Range Versions)

2

A

T

Ambient Temperature (Industrial Range Versions)

–40

25

85

°C

A

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

50% tKC

V

+ 2.0 V

DD

V

SS

50%

V

DD

V

– 2.0 V

SS

50% tKC

V

IL

Rev: 1.08 4/2007

12/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 2.5 V)

A

DD

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

pF

C

V

= 0 V

Input Capacitance

4

6

5

7

IN

C

V

OUT

= 0 V

Input/Output Capacitance

pF

I/O

Note:

These parameters are sample tested.

AC Test Conditions

Parameter

Conditions

V

– 0.2 V

Input high level

Input low level

DD

0.2 V

1 V/ns

/2

Input slew rate

V

Input reference level

DD

V

/2

Output reference level

Output load

DDQ

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

Output Load 1

DQ

*

50Ω

30pF

V

DDQ/2

* Distributed Test Jig Capacitance

Rev: 1.08 4/2007

13/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I

V = 0 to V

IN DD

–1 uA

1 uA

IL

V

≥ V ≥ V

IN

–1 uA

1 uA

100 uA

DD

IH

I

ZZ Input Current

IN1

0 V ≤ V ≤ V

IN

V

≥ V ≥ V

IN

–100 uA

–1 uA

1 uA

DD

IL

I

FT, SCD, ZQ Input Current

IN2

0 V ≤ V ≤ V

IN

I

Output Disable, V

= 0 to V

DD

Output Leakage Current

Output High Voltage

Output Low Voltage

–1 uA

1.7 V

2.4 V

—

1 uA

—

OL

OUT

DDQ

V

I

= –8 mA, V

= 2.375 V

= 3.135 V

OH2

OH

V

—

OH3

V

I

= 8 mA

OL

0.4 V

OL

Rev: 1.08 4/2007

14/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

Operating Currents

-8

-8.5

-10

-12

0

to

-40

to

0

to

-40

to

0

to

-40

to

0

to

-40

to

Parameter

Test Conditions

Symbol

Unit

70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C

All other inputs

≥VIH or ≤ VIL

Output open

Operating

Current

IDD

210

20

40

220

30

50

190

20

40

200

30

50

165

20

35

175

30

45

135

20

35

145

30

45

mA

Flow Through

Standby

Current

ISB

ZZ ≥ V – 0.2 V

DD

Flow Through

Device Deselected;

All other inputs

≥ VIH or ≤ VIL

Deselect

Current

IDD

Flow Through

AC Electrical Characteristics

-8

-8.5

-10

-12

Parameter

Symbol

Unit

Min

9.0

—

Max

—

Min

Max

Min

Max

Min

Max

—

12

—

5

Clock Cycle Time

tKC

tKQ

10.0

—

8.5

—

10.0

—

10

—

15.0

—

ns

Clock to Output Valid

8.0

—

Flow

Through

Clock to Output Invalid

Clock to Output in Low-Z

Clock HIGH Time

tKQX

3.0

1.3

1.5

—

3.0

1.3

1.5

—

3.0

1.3

1.5

—

3.0

1.3

1.5

—

1

—

tLZ

tKH

tKL

—

Clock LOW Time

—

1

Clock to Output in High-Z

G to Output Valid

3.2

—

3.5

—

3.8

—

tHZ

tOE

5

1

G to output in Low-Z

0

—

tOLZ

1

G to output in High-Z

Setup time

—

1.5

0.5

5

3.2

—

1.5

0.5

5

3.5

—

1.5

0.5

5

3.8

—

1.5

0.5

5

ns

tOHZ

tS

tH

—

Hold time

2

ZZ setup time

tZZS

2

ZZ hold time

ZZ recovery

1

—

1

—

1

—

1

—

ns

tZZH

tZZR

20

Notes:

1. These parameters are sampled and are not 100% tested

2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Rev: 1.08 4/2007

15/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

Flow Through Mode Timing

Begin

Read A Cont

tKH

Cont

Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont

Deselect

tKL

tKC

CK

Fixed High

ADSP

tS

tH

tS

tH

ADSC initiated read

ADSC

ADV

A0–An

GW

tS

tH

tS

tH

A

B

C

tS

tH

tS

tH

BW

tS

tH

Ba–Bd

E1

tS

Deselected with E1

tH

E2 and E3 only sampled with ADSC

E2

tS

tH

E3

G

tH

tS

tKQ

tLZ

tHZ

tOE

tOHZ

D(B)

tKQX

Q(A)

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

Q(C)

DQa–DQd

Rev: 1.08 4/2007

16/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

Sleep Mode Timing Diagram

tKH

tKC

tKL

CK

Setup

Hold

ADSP

ADSC

tZZR

tZZS

tZZH

ZZ

Rev: 1.08 4/2007

17/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

GS840FH18/32/36A Output Driver Characteristics

120.0

100.0

80.0

Pull Down Drivers

60.0

40.0

VDDQ

20.0

I Out

0.0

VOut

VSS

-20.0

-40.0

-60.0

-80.0

-100.0

-120.0

-140.0

Pull Up Drivers

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

V Out (Pull Down)

VDDQ - V Out (Pull Up)

3.6V PD HD

3.3V PD HD

3.1V PD HD

3.1V PU HD

3.3V PU HD

3.6V PU HD

Rev: 1.08 4/2007

18/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

TQFP Package Drawing (Package T)

θ

L

c

L1

Symbol

Description

Standoff

Min. Nom. Max

A1

A2

b

0.05

1.35

0.20

0.09

0.10

1.40

0.30

—

0.15

1.45

0.40

0.20

22.1

20.1

16.1

14.1

—

Body Thickness

Lead Width

c

Lead Thickness

D

Terminal Dimension 21.9

Package Body 19.9

Terminal Dimension 15.9

22.0

20.0

16.0

14.0

0.65

0.60

1.00

e

D1

E

b

E1

e

Package Body

Lead Pitch

13.9

—

L

Foot Length

Lead Length

Coplanarity

Lead Angle

0.45

—

0.75

—

L1

Y

A1

A2

E1

E

0.10

7°

θ

0°

—

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

Rev: 1.08 4/2007

19/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

Ordering Information for GSI Synchronous Burst RAMS

2

Speed

3

1

Org

Type

Package

Status

T

Part Number

A

(MHz/ns)

256K x 18

128K x 32

128K x 36

256K x 18

128K x 32

128K x 36

256K x 18

128K x 32

GS840FH18AT-8

GS840FH18AT-8.5

GS840FH18AT-10

GS840FH18AT-12

GS840FH32AT-8

Flow Through

TQFP

8

8.5

10

12

8

C

I

TQFP

GS840FH32AT-8.5

GS840FH32AT-10

GS840FH32AT-12

GS840FH36AT-8

TQFP

8.5

10

12

8

TQFP

GS840FH36AT-8.5

GS840FH36AT-10

GS840FH36AT-12

GS840FH18AT-8I

GS840FH18AT-8.5I

GS840FH18AT-10I

GS840FH18AT-12I

GS840FH32AT-8I

GS840FH32AT-8.5I

GS840FH32AT-10I

GS840FH32AT-12I

GS840FH36AT-8I

GS840FH36AT-8.5I

GS840FH36AT-10I

GS840FH36AT-12I

GS840FH18AGT-8

GS840FH18AGT-8.5

GS840FH18AGT-10

GS840FH18AGT-12

GS840FH32AGT-8

GS840FH32AGT-8.5

TQFP

8.5

10

12

8

TQFP

8.5

10

12

8

I

TQFP

I

TQFP

I

TQFP

8.5

10

12

8

I

TQFP

I

TQFP

I

TQFP

I

TQFP

8.5

10

12

8

I

TQFP

I

TQFP

I

RoHS-compliant TQFP

C

8.5

10

12

8

8.5

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840FH32AT-7.5T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.08 4/2007

20/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

2

Speed

3

1

Org

Type

Package

Status

T

Part Number

A

(MHz/ns)

128K x 32

128K x 36

256K x 18

128K x 32

128K x 36

GS840FH32AGT-10

GS840FH32AGT-12

GS840FH36AGT-8

GS840FH36AGT-8.5

GS840FH36AGT-10

GS840FH36AGT-12

GS840FH18AGT-8I

GS840FH18AGT-8.5I

GS840FH18AGT-10I

GS840FH18AGT-12I

GS840FH32AGT-8I

GS840FH32AGT-8.5I

GS840FH32AGT-10I

GS840FH32AGT-12I

GS840FH36AGT-8I

GS840FH36AGT-8.5I

GS840FH36AGT-10I

GS840FH36AGT-12I

Flow Through

RoHS-compliant TQFP

10

12

8

C

I

8.5

10

12

8

8.5

10

12

8

I

8.5

10

12

8

I

8.5

10

12

I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840FH32AT-7.5T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T^A= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.08 4/2007

21/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS840FH18/32/36AT-8/8.5/10/12

4Mb Burst Datasheet Revision History

Types of Changes

Format or Content

Rev. Code: Old;

Page /Revisions;Reason

New

• Updated pin description table

840FH18A_r1_02

Content

• Updated table on page 1

• Updated Operating Currents table on page 14

• Updated AC Electrical Characteristics table on page 14

• Updated Ordering Information table on page 21

• Updated entire document to comply with Technical

Publications standards

840FH18A_r1_02;

840FH18A_r1_03

Content/Format

• Reduced I by 20 mA in table on page 1 and Operating

840FH18A_r1_03;

840FH18A_r1_04

DD

Content

Currents table

• Removed 7.5 ns references from entire datasheet

840FH18A_r1_04;

840FH18A_r1_05

• Updated format

• Matched current numbers to NBT parts

• Removed Preliminary banner

840FH18A_r1_05;

840FH18A_r1_06

Content

• Added Pb-free information to TQFP

840FH18A_r1_06;

840FH18A_r1_07

• Changed Pb-free to RoHS-compliant (entire document)

• Updated Power Supply Voltage Ranges table (pg. 11)

• Updated Logic Level tables (pg. 12)

840FH18A_r1_07;

840FH18A_r1_08

Content

• Added note to TQFP pinout (pg. 2, 3, 4)

Rev: 1.08 4/2007

22/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS840FH32AT-12T
厂家：	GSI TECHNOLOGY
描述：	Cache SRAM, 128KX32, 12ns, CMOS, PQFP100, TQFP-100 时钟静态存储器内存集成电路
文件：	总22页 (文件大小：884K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS840FH32AT-12T [GSI]

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