GS840Z18CGT-200IT [GSI]
ZBT SRAM, 256KX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100;
| 型号： | GS840Z18CGT-200IT |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | ZBT SRAM, 256KX18, 6.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总22页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS840Z18CGT/GS840Z36CGT
250 MHz–100 MHz
100-Pin TQFP
Commercial Temp
Industrial Temp
4Mb Pipelined and Flow Through
Synchronous NBT SRAMs
3.3 V V
DD
2.5 V and 3.3 V V
DDQ
Because it is a synchronous device, address, data inputs, and
Features
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
• 256K x 18 and 128K x 36 configurations
• User configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• Pin-compatible with 2Mb, 9Mb and 18Mb devices
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered address, data, and control
• ZZ Pin for automatic power-down
The GS840Z18/36CGT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
• RoHS-compliant 100-lead TQFP package
Functional Description
The GS840Z18/36CGT is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
The GS840Z18/36CGT is implemented with GSI's high
performance CMOS technology and is available in a 6/6
RoHS-compliant, JEDEC-standard 100-pin TQFP package.
Parameter Synopsis
–250
–200
–166
–150
–100
tCycle
tKQ
IDD
4.0 ns
2.5 ns
TBD
5.5 ns
3.0 ns
TBD
6.0 ns
3.5 ns
TBD
6.7 ns
3.8 ns
TBD
10 ns
4.5 ns
TBD
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tKQ
tCycle
IDD
5.5 ns
5.5 ns
TBD
6.5 ns
6.5 ns
TBD
7.0 ns
7.0 ns
TBD
7.5 ns
7.5 ns
TBD
12 ns
12 ns
TBD
Rev: 1.01 8/2011
1/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
GS840Z18CGT Pinout (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
NC
NC
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
V
V
NC
DQPA
DQA
DQA
V
V
DQA
DQA
V
NC
V
ZZ
DQA
DQA
V
V
V
DDQ
DDQ
V
SS
SS
NC
NC
DQB
DQB
256K x 18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
Top View
V
DDQ
DDQ
DQB
DQB
FT
SS
V
DD
NC
DD
V
SS
DQB
DQB
V
DDQ
DDQ
V
SS
SS
DQA
DQA
NC
NC
V
DQB
DQB
DQPB
NC
V
SS
SS
V
V
DDQ
DDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
Rev: 1.01 8/2011
2/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
GS840Z36CGT Pinout (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPB
DQB
DQB
DQPC
DQC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
V
DDQ
DDQ
V
V
SS
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
128K x 36
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
Top View
V
DDQ
DDQ
DQB
DQB
DQC
DQC
FT
V
SS
NC
V
DD
V
NC
DD
ZZ
DQA
DQA
V
SS
DQD
DQD
V
V
DDQ
DDQ
V
V
SS
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
SS
V
V
DDQ
DDQ
DQA
DQA
DQPA
DQD
DQD
DQPD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either V or V . These pins can also be left floating.
DD
SS
Rev: 1.01 8/2011
3/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
100-Pin TQFP Pin Descriptions
Symbol
A0, A1
A
Type
In
Description
Burst Address Inputs; preload the burst counter
Address Inputs
In
CK
In
Clock Input Signal
BA
In
Byte Write signal for data inputs DQA1-DQA9; active low
Byte Write signal for data inputs DQB1-DQB9; active low
Byte Write signal for data inputs DQC1-DQC9; active low
Byte Write signal for data inputs DQD1-DQD9; active low
Write Enable; active low
BB
In
BC
In
BD
In
W
In
E1
In
Chip Enable; active low
E2
In
Chip Enable; active high; for self decoded depth expansion
Chip Enable; active low, for self decoded depth expansion
Output Enable; active low
E3
In
G
In
ADV
CKE
DQA
DQB
DQC
DQD
ZZ
In
Advance / Load—Burst address counter control pin
Clock Input Buffer Enable; active low
Byte A Data Input and Output pins
In
I/O
I/O
I/O
I/O
In
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
FT
In
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
LBO
VDD
In
In
3.3 V power supply
VSS
VDDQ
NC
In
In
Ground
3.3 V output power supply for noise reduction
No Connect
—
Rev: 1.01 8/2011
4/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
GS840Z18/36C NBT SRAM Functional Block Diagram
s p
n s e S e A m
s r e i v r D e i t r W
Rev: 1.01 8/2011
5/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipelined Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
W
H
L
BA
X
BB
X
BC
X
BD
X
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle
with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.
Flow through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving
the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a
double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode,
address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising
edge of clock.
Rev: 1.01 8/2011
6/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
Synchronous Truth Table
Operation
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Abort, Begin Burst
Write Cycle, Continue Burst
Write Abort, Continue Burst
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Continue
Sleep Mode
Type
R
Address
External
Next
CK CKE ADV
W
H
X
H
X
L
Bx E1 E2 E3
G
L
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
H
L
DQ
Q
Notes
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
H
L
X
X
X
X
L
L
X
L
H
X
H
X
H
H
X
X
X
X
L
L
X
L
B
L
Q
1,10
2
1,2,10
3
R
External
Next
H
H
X
X
X
X
X
X
X
X
X
X
High-Z
High-Z
D
B
H
L
X
L
X
L
W
D
External
None
1
L
L
H
L
L
L
High-Z
D
1,3,10
B
Next
H
H
L
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
B
Next
H
X
X
X
X
X
X
High-Z 1,2,3,10
High-Z
D
None
D
None
L
High-Z
D
None
L
High-Z
1
4
D
None
H
X
X
X
X
X
High-Z
High-Z
-
None
Clock Edge Ignore, Stall
Current
L-H
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect
cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is
sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write
cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.01 8/2011
7/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
Pipelined and Flow Through Read-Write Control State Diagram
D
B
Deselect
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
W
R
Burst Read
Burst Write
B
B
D
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram
Rev: 1.01 8/2011
8/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
R
B
W
B
Intermediate
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
Intermediate
D
Intermediate
W
R
High Z
B
D
Intermediate
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+2)
Intermediate State (N+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Intermediate
State
Current State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.01 8/2011
9/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
Flow Through Mode Data I/O State Diagram
R
B
W
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
D
W
R
High Z
B
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
Current State
Next State
Current State and Next State Definition for: Pipelined and Flow Through Read Write Control State Diagram
Rev: 1.01 8/2011
10/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
Read to Write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
L
Burst Order Control
LBO
H
L
Output Register Control
Power Down Control
FT
ZZ
H or NC
L or NC
H
Active
Standby, IDD = ISB
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0]
00
A[1:0]
01
A[1:0]
10
A[1:0]
11
A[1:0]
A[1:0]
01
A[1:0]
10
A[1:0]
11
1st address
2nd address
3rd address
4th address
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
10
11
00
00
11
10
11
00
01
11
00
01
00
01
10
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.01 8/2011
11/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep Mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
ZZ
tZZR
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Pin 14. Not all vendors offer this option, however, most mark Pin 14 as V or V
on pipelined parts and V on flow
DD
DDQ
SS
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Pin 66, a No Connect (NC) on GSI’s GS840Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36 NBT
SRAM, is often marked as a power pin on other vendor’s NBT-compatible SRAMs. Specifically, it is marked V or V on
DD
DDQ
pipelined parts and V on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity feature
SS
may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode applications or
tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By using the pull-up
resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT SRAMs
(GS881Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active low, open
drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs.
Rev: 1.01 8/2011
12/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
VDD
VDDQ
VI/O
Description
Value
Unit
V
Voltage on VDD Pins
Voltage in VDDQ Pins
–0.5 to 4.6
–0.5 to 4.6
V
–0.5 to VDDQ +0.5 ( 4.6 V max.)
–0.5 to VDD +0.5 ( 4.6 V max.)
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
VIN
V
IIN
+/–20
+/–20
mA
mA
W
IOUT
PD
1.5
oC
oC
TSTG
–55 to 125
–55 to 125
TBIAS
Temperature Under Bias
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter
Symbol
VDD3
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
V
3.3 V Supply Voltage
VDD2
2.5 V Supply Voltage
2.3
2.5
2.7
V
3.3 V VDDQ I/O Supply Voltage
2.5 V VDDQ I/O Supply Voltage
VDDQ3
VDDQ2
3.0
3.3
3.6
V
2.3
2.5
2.7
V
V
Range Logic Levels
DD3
Parameter
Symbol
VIH
Min.
2.0
Typ.
—
Max.
Unit
V
VDD + 0.3
Input High Voltage
Input Low Voltage
VIL
–0.3
—
0.8
V
Note:
(max) is voltage on V
V
pins plus 0.3 V.
DDQ
IHQ
Rev: 1.01 8/2011
13/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
V
Range Logic Levels
DD2
Parameter
Symbol
VIH
Min.
Typ.
—
Max.
Unit
V
0.6*VDD
VDD + 0.3
0.3*VDD
Input High Voltage
Input Low Voltage
VIL
–0.3
—
V
Note:
(max) is voltage on V
V
pins plus 0.3 V.
DDQ
IHQ
Operating Temperature
Parameter
Symbol
Min.
Typ.
Max.
Unit
Junction Temperature
(Commercial Range Versions)
TJ
0
25
25
85
C
C
Junction Temperature
(Industrial Range Versions)*
TJ
–40
100
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Thermal Impedance
Test PCB
Substrate
JA (C°/W)
Airflow = 0 m/s
JA (C°/W)
Airflow = 1 m/s
JA (C°/W)
Airflow = 2 m/s
Package
JB (C°/W)
JC (C°/W)
100 TQFP
4-layer
28.3
27.2
25.4
—
7.1
Notes:
1. Thermal Impedance data is based on a number of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
DD
V
SS
50%
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Note:
Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Rev: 1.01 8/2011
14/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
Typ.
Max.
Unit
pF
Input Capacitance
4
6
5
7
CI/O
VOUT = 0 V
Input/Output Capacitance
pF
Note:
These parameters are sample tested.
AC Test Conditions
Parameter
Conditions
VDD – 0.2 V
Input high level
Input low level
0.2 V
1 V/ns
VDD/2
Input slew rate
Input reference level
VDDQ/2
Output reference level
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
*
50
30pF
V
DDQ/2
* Distributed Test Jig Capacitance
Rev: 1.01 8/2011
15/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
VDD VIN VIH
0 V VIN VIH
–1 uA
–1 uA
1 uA
100 uA
IIN1
ZZ Input Current
FT Input Current
VDD VIN VIL
0 V VIN VIL
–100 uA
–1 uA
1 uA
1 uA
IIN2
IOL
Output Disable, VOUT = 0 to VDD
IOH = –8 mA, VDDQ = 2.375 V
IOH = –8 mA, VDDQ = 3.135 V
IOL = 8 mA
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
–1 uA
1.7 V
2.4 V
—
1 uA
—
VOH2
VOH3
VOL
—
0.4 V
Operating Currents
-250
-200
-166
-150
-100
0
to
–40
to
0
to
–40
to
0
to
–40
to
0
to
–40
to
0
to
–40
to
Parameter Test Conditions
Mode
Symbol
70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C
IDD
195
30
215
30
170
25
190
25
160
25
180
25
140
20
160
20
120
15
140
15
Pipeline
mA
mA
mA
mA
IDDQ
(x32/
x36)
IDD
Flow
Through
155
25
175
25
140
20
160
20
135
20
155
20
130
15
150
15
110
15
130
15
Device Selected;
IDDQ
All other inputs
VIH or VIL
Operating
Current
IDD
180
15
200
15
155
15
175
15
140
10
160
10
130
10
150
10
110
10
130
10
Pipeline
Output open
IDDQ
(x18)
IDD
Flow
Through
145
15
165
15
130
10
150
10
125
15
145
15
120
8
140
8
110
10
130
10
IDDQ
ISB
ISB
IDD
IDD
Pipeline
25
25
65
65
45
45
85
85
25
25
65
65
45
45
85
85
25
25
65
65
45
45
85
85
25
25
60
60
45
45
80
80
25
25
60
60
45
45
80
80
mA
mA
mA
mA
Standby
Current
ZZ VDD – 0.2 V
—
—
Flow
Through
Pipeline
Device Deselected;
All other inputs
VIH or VIL
Deselect
Current
Flow
Through
Rev: 1.01 8/2011
16/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
AC Electrical Characteristics
-250
-200
-166
-150
-100
Parameter
Symbol
Min
4.0
—
Max
—
Min
5.5
—
Max
—
Min
6.0
—
Max
—
Min Max Min Max
Clock Cycle Time
tKC
tKQ
6.7
—
—
3.8
—
10
—
—
4.5
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
Clock to Output Valid
2.5
—
3.0
—
3.5
—
Clock to Output Invalid
Pipeline
tKQX
1.5
1.5
1.2
0.2
5.5
—
1.5
1.5
1.4
0.4
6.5
—
1.5
1.5
1.5
0.5
7.0
—
1.5
1.5
1.5
0.5
7.5
—
1.5
1.5
2.0
0.5
12.0
—
tLZ1
tS
Clock to Output in Low-Z
—
—
—
—
Setup time
Hold time
—
—
—
—
tH
—
—
—
—
Clock Cycle Time
Clock to Output Valid
tKC
tKQ
tKQX
—
—
—
—
5.5
—
6.5
—
7.0
—
7.5
—
12.0 ns
Clock to Output Invalid
2.0
2.0
1.5
0.5
1.3
1.5
1.5
—
2.0
2.0
1.5
0.5
1.3
1.5
1.5
—
2.0
2.0
1.5
0.5
1.3
1.5
1.5
—
2.0
2.0
1.5
0.5
1.3
1.5
1.5
—
2.0
2.0
2.0
0.5
1.3
1.5
1.5
—
—
—
—
—
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Flow
Through
tLZ1
tS
Clock to Output in Low-Z
Setup time
—
—
—
—
—
—
—
—
Hold time
tH
—
—
—
—
Clock HIGH Time
Clock LOW Time
Clock to Output in High-Z
G to Output Valid
G to output in Low-Z
tKH
tKL
—
—
—
—
—
—
—
—
tHZ1
tOE
2.5
2.5
—
3.0
3.0
—
3.0
3.5
—
3.0
3.8
—
5
tOLZ1
tOHZ1
tZZS2
0
0
0
0
0
—
G to output in High-Z
ZZ setup time
ZZ hold time
—
5
2.5
—
—
—
—
5
3.0
—
—
—
—
5
3.0
—
—
—
—
5
3.0
—
—
—
—
5
5
ns
ns
ns
ns
—
—
—
tZZH2
tZZR
1
1
1
1
1
ZZ recovery
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.01 8/2011
17/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
Pipeline Mode Timing
Write A
Read B
Suspend
tKH
Read C
tKC
Write D
Write No-op Read E
Deselect
tKL
CK
A
tH
tH
tH
tH
tH
tH
tS
A
B
C
D
E
tS
tS
tS
tS
tS
CKE
E*
ADV
W
tH
tS
Bn
tH
tLZ
tHZ
tS
tKQ
tKQX
D(A)
Q(B)
Q(C)
D(D)
Q(E)
DQ
Rev: 1.01 8/2011
18/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
Flow Through Mode Timing
Write A
Write B
Write B+1 Read C
tKL
Cont
Read D
Write E
Read F
Write G
tKH
tKC
CK
CKE
E
tH
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
ADV
W
Bn
A0–An
A
B
C
D
E
F
G
tKQ
tLZ
tH
tKQ
tLZ
D(B+1)
tKQX
tS
D(A)
tHZ
Q(D)
tKQX
D(G)
DQ
D(B)
Q(C)
D(E)
Q(F)
tOLZ
tOE
tOHZ
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 1.01 8/2011
19/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
TQFP Package Drawing (Package T)
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
0.10
7
0
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
BPR 1999.05.18
Rev: 1.01 8/2011
20/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
Ordering Information—GSI NBT Synchronous SRAMs
2
Speed
3
1
Org
Type
Package
T
Part Number
J
(MHz/ns)
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
GS840Z18CGT-250
GS840Z18CGT-200
GS840Z18CGT-166
GS840Z18CGT-150
GS840Z18CGT-100
GS840Z36CGT-250
GS840Z36CGT-200
GS840Z36CGT-166
GS840Z36CGT-150
GS840Z36CGT-100
GS840Z18CGT-250I
GS840Z18CGT-200I
GS840Z18CGT-166I
GS840Z18CGT-150I
GS840Z18CGT-100I
GS840Z36CGT-250I
GS840Z36CGT-200I
GS840Z36CGT-166I
GS840Z36CGT-150I
GS840Z36CGT-100I
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
250/5.5
200/6.5
166/7.0
150/7.5
100/12
250/5.5
200/6.5
166/7.0
150/7.5
100/12
250/5.5
200/6.5
166/7.0
150/7.5
100/12
250/5.5
200/6.5
166/7.0
150/7.5
100/12
C
C
C
C
C
C
C
C
C
C
I
I
I
I
I
I
I
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840Z36CGT-100IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. C = Commercial Temperature Range. I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.01 8/2011
21/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
4Mb Synchronous NBT Datasheet Revision History
Types of Changes
File Name
Revision
Format or Content
• Creation of new datasheet
840ZxxC_r1
• Updated Operating Currents table
840ZxxC_r1_01
Content
Rev: 1.01 8/2011
22/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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