GS840Z36AT-188IT [GSI]
SRAM;
| 型号： | GS840Z36AT-188IT |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | SRAM 静态存储器 |
| 文件： | 总25页 (文件大小：708K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS840Z18/36AT-180/166/150/100
100-Pin TQFP
Commercial Temp
Industrial Temp
180 MHz–100 MHz
3.3 V VDD
2.5 V and 3.3 V VDDQ
4Mb Pipelined and Flow Through
Synchronous NBT SRAMs
Features
Functional Description
The GS840Z18/36AT is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
• 256K x 18 and 128K x 36 configurations
• User configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• Pin-compatible with 2M, 8M and 16M devices
• 3.3 V +10%/–5% core power supply
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered address, data, and control
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
–180
–166
–150
–100
tCycle
tKQ
IDD
5.5 ns
3.2 ns
6.0 ns
3.5 ns
6.6 ns
3.8 ns
10 ns
4.5 ns
190 mA
Pipeline
3-1-1-1
The GS840Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
335 mA 310 mA 280 mA
Flow
Through tCycle
2-1-1-1 IDD
tKQ
8 ns
9.1 ns
8.5 ns
10 ns
10 ns
12 ns
12 ns
15 ns
135 mA
210 mA 190 mA 165 mA
The GS840Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
A
R
B
C
R
D
E
R
F
Read/Write
W
W
W
Flow Through
Data I/O
Q
D
Q
D
D
Q
E
A
B
C
D
Pipelined
Data I/O
Q
Q
D
Q
E
A
B
C
D
Rev: 1.02 11/2002
1/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS840Z18/36AT-180/166/150/100
GS840Z18AT Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A17
NC
NC
V
SS
NC
DQA9
DQA8
DQA7
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
V
4
DDQ
DDQ
V
V
5
SS
NC
NC
6
7
8
DQB1
DQB2
9
256K x 18
Top View
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
DDQ
SS
V
V
DDQ
DQA6
DQB3
DQB4
FT
DQA5
V
SS
NC
V
V
DD
DD
SS
V
DD
ZZ
V
DQA4
DQA3
DQB5
DQB6
V
V
V
DDQ
DDQ
SS
V
SS
DQA2
DQA1
NC
DQB7
DQB8
DQB9
NC
NC
V
V
V
SS
DDQ
SS
V
DDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.02 11/2002
2/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
GS840Z36AT Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQB9
DQB8
DQB7
DQC9
DQC8
DQC7
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
V
V
4
DDQ
DDQ
SS
V
V
5
SS
DQB6
DQB5
DQB4
DQB3
DQC6
DQC5
DQC4
DQC3
6
7
8
9
128K x 36
Top View
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
DDQ
SS
V
V
DDQ
DQB2
DQC2
DQC1
FT
DQB1
V
SS
NC
V
V
DD
DD
SS
V
DD
ZZ
V
DQA1
DQA2
DQD1
DQD2
DDQ
V
V
V
DDQ
SS
V
SS
DQA3
DQA4
DQA5
DQA6
DQD3
DQD4
DQD5
DQD6
V
V
V
SS
DDQ
SS
V
DDQ
DQA7
DQA8
DQA9
DQD7
DQD8
DQD9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.02 11/2002
3/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
100-Pin TQFP Pin Descriptions
Symbol
Type
In
Description
A0, A1
Burst Address Inputs; preload the burst counter
Address Inputs
A2–A17
In
CK
In
Clock Input Signal
BA
In
Byte Write signal for data inputs DQA1-DQA9; active low
Byte Write signal for data inputs DQB1-DQB9; active low
Byte Write signal for data inputs DQC1-DQC9; active low
Byte Write signal for data inputs DQD1-DQD9; active low
Write Enable; active low
BB
In
BC
In
BD
In
W
In
E1
In
Chip Enable; active low
E2
E3
In
Chip Enable; active high; for self decoded depth expansion
Chip Enable; active low, for self decoded depth expansion
Output Enable; active low
In
G
In
ADV
In
Advance / Load—Burst address counter control pin
Clock Input Buffer Enable; active low
Byte A Data Input and Output pins
CKE
In
DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
ZZ
I/O
I/O
I/O
I/O
In
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
FT
In
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
LBO
In
V
In
3.3 V power supply
DD
V
In
In
—
Ground
3.3 V output power supply for noise reduction
No Connect
SS
V
DDQ
NC
Rev: 1.02 11/2002
4/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
GS840Z18/36A NBT SRAM Functional Block Diagram
n s e e S A m p s
i t r e W D r i v e r
s
Rev: 1.02 11/2002
5/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipelined Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
W
H
L
BA
X
BB
X
BC
X
BD
X
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle
with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.
Flow through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving
the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a
double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode,
address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising
edge of clock.
Rev: 1.02 11/2002
6/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Synchronous Truth Table
Operation
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Continue
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
Write Abort, Continue Burst
Clock Edge Ignore, Stall
Sleep Mode
Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes
D
D
D
D
R
B
None
None
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
None
X
H
X
H
X
H
X
H
X
X
X
H
L
1
External
Next
L-H
L-H
Q
Q
X
L
X
L
H
L
L
1,10
2
R
B
External
Next
H
H
X
X
X
X
X
X
L-H High-Z
X
L
X
L
H
L
L-H High-Z 1,2,10
W
B
External
Next
L-H
L-H
D
D
3
X
L
X
L
H
L
X
L
L
1,3,10
2,3
W
B
None
H
H
X
X
L-H High-Z
Next
X
X
X
X
X
X
H
X
X
X
X
X
L-H High-Z 1,2,3,10
Current
None
L-H
X
-
4
High-Z
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect
cycle is executed first
2. Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A write abort occurs when the W pin is
sampled low, but no byte write pins are active, so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write
cycles.
4. If CKE high occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE high occurs during a write cycle, the bus will
remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are low
6. All inputs, except G and ZZ, must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.02 11/2002
7/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Pipelined and Flow Through Read-Write Control State Diagram
D
B
Deselect
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
W
R
Burst Read
Burst Write
B
B
D
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram
Rev: 1.02 11/2002
8/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
R
B
W
B
Intermediate
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
Intermediate
D
Intermediate
W
R
High Z
B
D
Intermediate
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+2)
Intermediate State (N+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Intermediate
State
Current State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.02 11/2002
9/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Flow Through Mode Data I/O State Diagram
R
B
W
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
D
W
R
High Z
B
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
Current State
Next State
Current State and Next State Definition for: Pipelined and Flow Through Read Write Control State Diagram
Rev: 1.02 11/2002
10/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
Read to Write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin Name
State
L
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Burst Order Control
LBO
H or NC
L
Output Register Control
Power Down Control
FT
ZZ
H or NC
L or NC
H
Active
Standby, I = I
DD SB
Note:
There is a are pull-up devices on the LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above table.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or x32) mode. Holding
the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high deactivates the 9th I/O of each byte, although
the bit in each byte of the memory array remains active to store and recall parity bits generated and read into the ByteSafe parity circuits.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.02 11/2002
11/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep Mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
CK
tZZR
ZZ
Sleep
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found
on Pin 14. Not all vendors offer this option, however, most mark Pin 14 as V or V
on pipelined parts and V on flow
SS
DD
DDQ
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Pin 66, a No Connect (NC) on GSI’s GS840Z18/36A NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36 NBT
SRAM, is often marked as a power pin on other vendor’s NBT-compatible SRAMs. Specifically, it is marked V or V on
DD
DDQ
pipelined parts and V on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity feature
SS
may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode applications or
tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By using the pull-up
resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT SRAMs
(GS881Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active low, open
drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs.
Rev: 1.02 11/2002
12/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 4.6
DD
DD
V
Voltage in V
Pins
–0.5 to V
V
DDQ
DDQ
DD
V
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 6
V
CK
V
–0.5 to V
+0.5 (≤ 4.6 V max.)
DDQ
V
I/O
V
–0.5 to V +0.5 (≤ 4.6 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended
period of time, may affect reliability of this component.
Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
Min.
3.135
2.375
1.7
Typ.
3.3
2.5
—
Max.
Unit
V
Notes
V
3.6
DD
V
V
I/O Supply Voltage
V
1
2
2
3
3
DDQ
DD
V
V
+0.3
DD
Input High Voltage
V
IH
V
Input Low Voltage
–0.3
0
—
0.8
V
IL
T
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
25
70
85
°C
°C
A
T
–40
25
A
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ V
≤ 2.375 V
DDQ
(i.e., 2.5 V I/O) and 3.6 V ≤ V
≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.
DDQ
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < V +2 V with a pulse width not to exceed 20% tKC.
DD
Rev: 1.02 11/2002
13/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
50%
DD
V
SS
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 3.3 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V
= 0 V
Input Capacitance
4
6
5
7
IN
IN
C
V
OUT
= 0 V
Input/Output Capacitance
pF
I/O
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
Max
40
Unit
Notes
1,2
R
R
R
single
four
—
°C/W
°C/W
°C/W
ΘJA
ΘJA
ΘJC
24
1,2
9
3
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient.
Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.02 11/2002
14/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
AC Test Conditions
Parameter
Input high level
Input low level
Conditions
2.3 V
0.2 V
Input slew rate
1 V/ns
Input reference level
Output reference level
Output load
1.25 V
1.25 V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t , t , t and t
LZ HZ OLZ
OHZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225Ω
DQ
*
50Ω
VT = 1.25 V
30pF
*
225Ω
5pF
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
V
≥ V ≥ V
IN
–1 uA
–1 uA
1 uA
300 uA
DD
IH
IH
I
ZZ Input Current
INZZ
0 V ≤ V ≤ V
IN
V
≥ V ≥ V
IN
–300 uA
–1 uA
1 uA
1 uA
DD
IL
IL
I
Mode Pin Input Current
Output Leakage Current
INM
0 V ≤ V ≤ V
IN
Output Disable,
V
I
–1 uA
1 uA
OL
= 0 to V
OUT
DD
V
I
I
= –8 mA, V
= –8 mA, V
= 2.375 V
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
—
—
—
OH
OH
OH
DDQ
DDQ
V
= 3.135 V
OH
V
I
= 8 mA
OL
0.4 V
OL
Rev: 1.02 11/2002
15/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Operating Currents
-180
-166
-150
-100
Parameter Test Conditions Symbol
Unit
0 to
–40 to
0 to
–40 to
0 to
–40 to
0 to
–40 to
70°C
85°C
70°C
85°C
70°C
85°C
70°C
85°C
IDD
Pipeline
Device Selected;
All other inputs
≥VIH or ≤ VIL
335
210
20
345
310
190
20
320
280
165
20
290
190
135
20
200
mA
mA
mA
mA
mA
mA
Operating
Current
IDD
Flow-Thru
220
30
200
30
175
30
145
30
Output open
ISB
Pipeline
ZZ ≥ VDD –
Standby
Current
0.2 V
ISB
Flow-Thru
20
30
20
30
20
30
20
30
IDD
Pipeline
55
65
50
60
50
60
40
50
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
Deselect
Current
IDD
Flow-Thru
40
50
40
50
35
45
35
45
Rev: 1.02 11/2002
16/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
AC Electrical Characteristics
-180
-166
-150
-100
Parameter
Symbol
Unit
Min
5.5
—
Max
—
Min
6.0
—
Max
—
Min
6.7
—
Max
—
Min
10
Max
—
Clock Cycle Time
tKC
tKQ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock to Output Valid
3.2
—
3.5
—
3.8
—
—
4.5
—
Pipeline
Clock to Output Invalid
tKQX
1.5
1.5
9.1
—
1.5
1.5
10.0
—
1.5
1.5
12.0
—
1.5
1.5
15.0
—
1
Clock to Output in Low-Z
Clock Cycle Time
—
—
—
—
tLZ
tKC
tKQ
—
—
—
—
Clock to Output Valid
8.0
—
8.5
—
10.0
—
12.0
—
Flow
Through
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKQX
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
1
—
—
—
—
tLZ
tKH
tKL
—
—
—
—
Clock LOW Time
—
—
—
—
1
Clock to Output in High-Z
G to Output Valid
3.2
3.2
—
3.5
3.5
—
3.8
3.8
—
5
tHZ
tOE
5
1
G to output in Low-Z
0
0
0
0
—
tOLZ
1
G to output in High-Z
Setup time
—
1.5
0.5
5
3.2
—
—
—
—
1.5
0.5
5
3.5
—
—
—
—
1.5
0.5
5
3.8
—
—
—
—
2.0
0.5
5
5
ns
ns
ns
ns
tOHZ
tS
tH
—
—
—
Hold time
2
ZZ setup time
tZZS
2
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
tZZH
tZZR
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.02 11/2002
17/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Pipeline Mode Read/Write Cycle Timing
1
2
3
4
5
6
7
8
9
10
CK
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
tKH tKL tKC
CKE
E*
ADV
W
Bn
tH
A1
A2
A3
A4
A5
A6
A7
A0–An
tKQ
tHZ
tOE
tKQX
tLZ
D
Q
DQA–DQD
Q(A3)
Q(A4)
Q(A6)
D(A2)
D(A1)
D(A5)
(A2+1)
(A4+1)
tKQX
tH
tS
tOHZ
tOLZ
G
Write
Write
BURST Read
Q(A3)
Read
Q(A4) Read
Q(A4+1)
BURST
Read
DESELECT
Write
Write
D(A5)
D(A2) Write
Q(A6)
COMMAND
D(A1)
D(A7)
D(A2+1)
DON’T CARE
UNDEFINED
*Note: E = High (False) if E = 1 or E = 0 or E = 1
1
2
3
Rev: 1.02 11/2002
18/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Pipeline Mode No-Op, Stall and Deselect Timing
2
8
4
3
5
6
10
7
9
1
CK
tH
tH
tH
tS
tS
tS
CKE
E*
ADV
tS
tH
W
Bn
A0–An
DQ
A1
A2
A3
A4
A5
tHZ
Q(A2)
D(A1)
Q(A3)
D(A4)
Q(A5)
tKQX
NOP
Read
STALL Read
Q(A3)
Write
STALL
Read
CONTINUE
DESELECT
Write
DESELECT
Q(A2)
D(A4)
Q(A5)
D(A1)
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E = 1 or E = 0 or E = 1
1
2
3
Rev: 1.02 11/2002
19/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Flow Through Mode Read/Write Cycle Timing
4
3
5
6
8
10
7
9
1
2
CK
CKE
E*
tH
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
tKH tKL
tKC
ADV
W
Bn
A7
A0–An
DQ
A1
A2
A3
A4
A5
A6
tKQ
tHZ
tOE
tKQX
tLZ
D
Q
Q(A3)
Q(A4)
Q(A6)
D(A2)
D(A1)
D(A5)
(A2+1)
(A4+1)
tKQX
tOHZ
tH
tS
tOLZ
G
Write
D(A5)
Write
BURST Read
Read
BURST
Read
DESELECT
Write
Write
COMMAND
D(A2)
Write
Q(A3)
Q(A4) Read
Q(A4+1)
Q(A6)
D(A1)
D(A7)
D(A2+1)
DON’T CARE
UNDEFINED
*Note: E = High (False) if E = 1 or E = 0 or E = 1
1
2
3
Rev: 1.02 11/2002
20/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Flow Through Mode No-Op, Stall and Deselect Timing
4
3
5
6
8
10
7
9
1
2
CK
tH
tS
tS
tS
CKE
E*
tH
tH
ADV
W
Bn
A1
A2
A3
A4
A5
A0–An
DQ
tHZ
Q(A2)
D(A1)
Q(A5)
Q(A3)
D(A4)
NOP
tKQX
Read
STALL Read
Q(A3)
Write
STALL
Read
CONTINUE
DESELECT
DESELECT
Write
COMMAND
Q(A2)
D(A4)
Q(A5)
D(A1)
DON’T CARE
UNDEFINED
*Note: E = High (False) if E = 1 or E = 0 or E = 1
1
2
3
Rev: 1.02 11/2002
21/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Output Driver Characteristics
TBD
Rev: 1.02 11/2002
22/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
TQFP Package Drawing
θ
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
—
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
—
0.10
7°
θ
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
BPR 1999.05.18
Rev: 1.02 11/2002
23/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
Ordering Information—GSI NBT Synchronous SRAM
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
256K x 18
256K x 18
256K x 18
256K x 18
128K x 36
128K x 36
128K x 36
128K x 36
256K x 18
256K x 18
256K x 18
256K x 18
128K x 36
128K x 36
128K x 36
128K x 36
Notes:
GS840Z18AT-180
GS840Z18AT-166
GS840Z18AT-150
GS840Z18AT-100
GS840Z36AT-180
GS840Z36AT-166
GS840Z36AT-150
GS840Z36AT-100
GS840Z18AT-180I
GS840Z18AT-166I
GS840Z18AT-150I
GS840Z18AT-100I
GS840Z36AT-180I
GS840Z36AT-166I
GS840Z36AT-150I
GS840Z36AT-100I
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
180/8
166/8.5
150/10
100/12
180/8
C
C
C
C
C
C
C
C
I
166/8.5
150/10
100/12
180/8
166/8.5
150/10
100/12
180/8
I
I
I
I
166/8.5
150/10
100/12
I
I
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840Z36AT-100IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some
of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.02 11/2002
24/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS840Z18/36AT-180/166/150/100
4Mb Synchronous NBT Datasheet Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Page /Revisions/Reason
New
• Creation of new datasheet
840Z18A_r1
• Updated power numbers in table on page 1 and Operating
Currents table
840Z18A_r1;
Content
Content
840Z18A_r1_01
• Removed 200 MHz speed bin from entire document
• Removed pin locations from pin description table
840Z18A_r1_01;
840Z18A_r1_02
Rev: 1.02 11/2002
25/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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