GS84118GT-166T [GSI]
Cache Tag SRAM, 256KX18, 8.5ns, CMOS, PQFP100, TQFP-100;
| 型号： | GS84118GT-166T |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Cache Tag SRAM, 256KX18, 8.5ns, CMOS, PQFP100, TQFP-100 静态存储器 |
| 文件： | 总30页 (文件大小：719K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS84118T/B-166/150/133/100
166 MHz–100 MHz
8.5 ns–12 ns
TQFP, BGA
Commercial Temp
Industrial Temp
256K x 18 Sync
Cache Tag
3.3 V V
DD
3.3 V and 2.5 V I/O
Features
Output registers and the Match output register are provided and
controlled by the FT mode pin (Pin 14). Through use of the FT
mode pin, I/O registers can be programmed to perform pipeline
or flow through operation. Flow Through mode reduces
latency.
• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O
supply
• Intergrated data comparator for Tag RAM application
• FT mode pin for flow through or pipeline operation
• LBO pin for Linear or Interleave (PentiumTM and X86) Burst
Byte write operation is performed by using Byte Write Enable
(BWE) input combined with two individual byte write signals
BW1-2. In addition, Global Write (GW) is available for
writing all bytes at one time.
mode
• Synchronous address, data I/O, and control inputs
• Synchronous Data Enable (DE)
• Asynchronous Output Enable (OE)
• Asynchronous Match Output Enable (MOE)
• Byte Write (BWE) and Global Write (GW) operation
• Three chip enable signals for easy depth expansion
• Internal self-timed write cycle
• JTAG Test mode conforms to IEEE standard 1149.1
• JEDEC-standard 100-lead TQFP package and 119-BGA:
T:TQFP or B: BGA
Compare cycles begin as a read cycle with output disabled so
that compare data can be loaded into the data input register.
The comparator compares the read data with the registered
input data and a match signal is generated. The match output
can be either in Pipeline or Flow Through modes controlled by
the FT signal.
Low power (Standby mode) is attained through the assertion of
the ZZ signal, or by stopping the clock (CLK). Memory data is
retained during Standby mode.
-166
-150
-133
-100
tcycle
tKQ
IDD
6.0 ns
3.5 ns
6.6 ns
3.8 ns
7.5 ns
4.0 ns
10 ns
4.5 ns
Pipeline
3-1-1-1
JTAG boundary scan interface is provided using IEEE
standard 1149.1 protocol. Four pins—Test Data In (TDI), Test
Data Out (TDO), Test Clock (TCK) and Test Mode Select
(TMS)—are used to perform JTAG function.
310 mA 275 mA 250 mA 190 mA
tKQ
tcycle
IDD
Flow
Through
2-1-1-1
8.5 ns
10 ns
10 ns
10 ns
11 ns
15 ns
12 ns
15 ns
The GS84118 operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate
output (VDDQ) pins are used to allow both 3.3 V or 2.5 V IO
190 mA 190 mA 140 mA 140 mA
interface.
Functional Description
The GS84118 is a 256K x 18 high performance synchronous
SRAM with integrated Tag RAM comparator. A 2-bit burst
* Pentium is a trademark of Intel Corp.
counter is included to provide burst interface with PentiumTM
and other high performance CPUs. It is designed to be used as
a Cache Tag SRAM, as well as data SRAM. Addresses, data
IOs, match output, chip enables (CE1, CE2, CE3), address
control inputs (ADSP, ADSC, ADV), and write control inputs
(BW1, BW2, BWE, GW, DE) are synchronous and are
controlled by a positive-edge-triggered clock (CLK).
Output Enable (OE), Match Output Enable, and power down
control (ZZ) are asynchronous. Burst can be initiated with
either ADSP or ADSC inputs. Subsequent burst addresses are
generated internally and are controlled by ADV. The burst
sequence is either interleave order (PentiumTM or x86) or
linear order, and is controlled by LBO.
Rev: 1.05 7/2001
1/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Trademark Notice (if any) Trademark of Giga Semiconductor, Inc. (GSI Technology).
GS84118T/B-166/150/130/100
Pin Configuration
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A10
NC
NC
VDDQ
VSS
NC
DQP1
DQ8
DQ7
VSS
VDDQ
DQ6
DQ5
VSS
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
VDDQ
2
3
4
VSS
NC
NC
DQ9
DQ10
VSS
VDDQ
DQ11
DQ12
FT
VDD
NC
VSS
DQ13
DQ14
VDDQ
5
6
7
8
9
256K x 18
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
ZZ
DQ4
DQ3
VDDQ
VSS
DQ2
DQ1
NC
VSS
DQ15
DQ16
DQP2
NC
VSS
VDDQ
NC
NC
VSS
VDDQ
MATCH
DE
NC
NC
MOE
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.05 7/2001
2/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
84118 PadOut
119-Bump BGA—Top View
1
2
3
4
5
6
7
A
B
C
D
E
F
V
A6
A7
A4
A3
ADSP
ADSC
A8
A9
V
DDQ
DDQ
NC
E2
A15
A14
E3
NC
NC
A5
V
A16
NC
NC
DD
DQB1
NC
NC
V
NC
E1
V
DQP1
NC
SS
SS
SS
SS
SS
SS
DQB2
NC
V
V
V
V
DQA8
V
G
DQA7
NC
V
DDQ
DDQ
NC
DQB3
NC
BB
ADV
GW
NC
DQA6
G
H
J
DQB4
V
V
DQA5
NC
SS
SS
V
V
NC
V
NC
V
V
DDQ
DDQ
DD
DD
DD
NC
DQB5
NC
V
CK
NC
BW
A1
V
NC
DQA3
MATCH
DQA2
MOE
A13
DQA4
K
L
SS
SS
DQB6
NC
BA
NC
V
DQB7
NC
V
V
V
DDQ
M
N
P
R
T
DDQ
SS
SS
SS
SS
SS
SS
DQB8
V
V
V
V
DE
NC
NC
NC
DQP2
A2
A0
DQA1
NC
LBO
A11
V
FT
A12
DD
A10
NC
NC
A17
ZZ
V
TMS
TDI
TDO
TCK
V
DDQ
U
DDQ
Rev: 1.05 7/2001
3/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
TQFP Pin Description
Pin Location
Symbol
A0–A17
CLK
Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48,
47, 46, 45, 44, 49, 50
Address Input Signals—Inputs are registered and must meet
setup and hold times, as specified on page 11.
89
Clock Input Signal
Byte Write Enable Signal—The byte write enable signal
needs to be combined with one of the four byte write signals
for a write operation to occur.
87
BWE
93
94
BW1
BW2
Byte Write signal for data outputs 1 thru 8
Byte Write signal for data outputs 9 thru 16
Global Write Enable
88
GW
92, 97, 98
86
CE1,CE2, CE3
OE
Chip Enables
Output Enable
83
ADV
Burst address advance
84, 85
ADSP, ADSC
Address status signals
58, 59, 62 ,63, 68, 69, 72, 73, 8, 9, 12, 13, 18,
19, 22, 23
DQ1–DQ16
Data Input and Output pins
74, 24
53
DQP1–DQP2
MATCH
Parity Input and Output pins
Match Output
51
MOE
Match Output Enable
Data Enable—Data input registers are updated only when DE
is active.
52
64
DE
ZZ
Power down control—Application of ZZ will result in a low
standby power consumption.
14
FT
Flow Through or Pipeline mode
Linear Order Burst mode
Test Mode Select
Test Data In
31
LBO
TMS
TDI
38
39
42
43
TDO
TCK
VDD
Test Data Out
Test Clock
15, 41, 65, 91
3.3 V power supply
5,10,17, 21, 26, 40, 55, 60, 67, 71,
76, 90
VSS
VDDQ
NC
Ground
2.5 V/3.3 V output power supply
No Connect
4, 11, 20, 27, 54, 61, 70, 77
1, 2, 3, 6, 7, 16, 25, 28, 29, 30,56, 57, 66, 75,
78, 79, 95, 96
Rev: 1.05 7/2001
4/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
PBGA Pin Description
Pin Location
Symbol
A0–A17
CLK
Description
P4, N4, R2, C3, B3, C2, A2, A3, A5, A6, T6, C5,
R6, T5, T2, T3, B5, C6
Address Input Signals—Inputs are registered and must meet
setup and hold times, as specified on page 11.
K4
Clock Input Signal
Byte Write Enable Signal—The byte write enable signal needs to
be combined with one of the four byte write signals for a write
operation to occur.
M4
BWE
L5
G3
BW1
BW2
Byte Write signal for data outputs 1 thru 8
Byte Write signal for data outputs 9 thru 16
Global Write Enable
H4
GW
E4, B2, B6
F4
CE1,CE2, CE3
OE
Chip Enables
Output Enable
G4
ADV
Burst address advance
A4, B4
ADSP, ADSC
Address status signals
P7, N6, L6, K7, H6, G7, F6, E7, D1, E2, G2, H1,
K2, L1, M2, N1
DQ1–DQ16
Data Input and Output pins
D6, P2
M6
DQP1–DQP2
MATCH
Parity Input and Output pins
Match Output
P6
MOE
Match Output Enable
Data Enable—Data input registers are updated only when DE is
active.
N7
T7
DE
ZZ
Power down control—Application of ZZ will result in a low
standby power consumption.
R5
FT
Flow Through or Pipeline mode
Linear Order Burst mode
Test Mode Select
Test Data In
R3
LBO
TMS
TDI
U2
U3
U5
U4
TDO
TCK
VDD
Test Data Out
Test Clock
C4, J2, J4, J6, R4
3.3 V power supply
D3, D5, E3, E5, F3, F5, H3, H5, K3, K5, M3, M5,
N3, N5, P3, P5
VSS
Ground
VDDQ
A1, A7, F1, F7, J1, J7, M1, M7, U1, U7
2.5 V/3.3 V output power supply
B1, B7, C1, C7, D2, D4, D7, E1, E6, F2, G1, G5,
G6, H2, H7, J3, J5, K1, K6, L2, L3, L4, L7, N2,
P1, RR1, R7, T1, T4, U6
NC
No Connect
Rev: 1.05 7/2001
5/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Functional Block Diagram
18
REGISTER
A0-17
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
BINARY
18
COUNTER
A
Load
LBO
ADV
256K X 18
Memory
Array
CLK
ADSC
ADSP
Q
D
GW
Register
18
BWE
BW1
18
D
Q
2
Register
D
Q
BW2
DE
Register
D
Q
Register
CE1
CE2
D
Q
CE3
Powerdown
Control
Register
ZZ
D
Q
FT
OE
MOE
A, DQ,
Control
18
54
Boundary Scan
Registers
DQ1-16
DQP1-2
Match
Bypass Reg
ID Reg.
TDI
TDO
Instruction Reg.
TMS
TCK
TAP
Controller
Rev: 1.05 7/2001
6/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Mode Pin Function
LBO
Function
Linear Burst
FT
Function
L
L
Flow Through
H or NC
Interleaved Burst
H or NC
Pipeline
Power Down Control
ZZ
L or NC
H
Function
Active
Standby, IDD = ISB
Note:
There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above tables.
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Byte Write Function
Function
Read
GW BWE BW1 BW2
H
H
L
H
L
X
L
L
L
X
H
X
L
X
H
X
L
Read
Write all bytes
Write all bytes
Write byte 1
Write byte 2
H
H
H
L
H
L
H
Note: H = logic high, L = logic low, NC = no connect
Rev: 1.05 7/2001
7/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Synchronous Truth Table
Operation
Address Used
none
CE1 CE2 CE3 ADSP ADSC ADV Write OE CLK
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
H
L
X
L
X
X
H
X
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
none
none
L
X
L
L
none
L
H
H
L
none
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
external
external
external
external
external
next
L
X
X
L
L-H
L-H High-Z
L-H
L-H High-Z
Q
L
L
L
H
L
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
Q
L
L
L
H
X
L
L
L
L
L-H
L-H
D
Q
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
next
L
H
L
L-H High-Z
L-H
L-H High-Z
next
L
Q
next
L
H
X
X
L
next
L
L-H
L-H
L-H
D
D
Q
next
L
L
current
current
current
current
current
current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H High-Z
L-H
L-H High-Z
Q
H
X
X
L-H
L-H
D
D
L
Notes:
1. X means “don’t care,” H means “logic high,” L means “logic low.”
2. Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
3. All inputs, except OE, must meet setup and hold on rising edge of CLK.
4. Suspending busrt generates a wait cycle.
5. ADSP LOW along with SRAM being selected always initiates a Read cycle at the L-H edge of the clock (CLK).
6. A Write cycle can only be performed by setting Write low for the clock L-H edge of the subsequent wait cycle.
Refer to page 12 for the Write timing diagram.
Rev: 1.05 7/2001
8/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Truth Table For Read/Write/Compare/Fill Write Operation
CE
L
Write
DE
X
MOE
OE
L
Match
—
DQ
Q
Read
Write
H
L
X
X
L
L
L
H
—
D
Compare
Fill Write
L
H
L
L
H
Data Out
—
D
L
H
X
X
L
X
X
Match Deselect
Deselect
H
H
X
X
X
High
High Z
High Z
High Z
X
H
X
Notes:
1. X means “don’t care,” H means “logic high,” L means “logic low.”
2. Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
3. CE is defined as CE1=L, CE2=H and CE3=L
4. All signals are synchronous and are sampled by CLK except OE and MOE. OE and MOE are asynchronous and drive the bus immediately.
Absolute Maximum Ratings (Voltage reference to V = 0 V)
SS
Symbol
VDD
Description
Supply Voltage
Commerical
–0.5 to 4.6
Unit
V
V
V
VDDQ
–0.5 to VDD
Output Supply Voltage
CLK Input Voltage
VCLK
–0.5 to 6
–0.5 to VDD + 0.5
(£ 4.6 V max. )
Vin
Input Voltage
V
V
–0.5 to VDD + 0.5
(£ 4.6 V max. )
Vout
Output Voltage
Iout
PD
Output Current per I/O
Power Dissipation
+/–20
1.5
mA
W
oC
oC
TOPR
TSTG
Operating Temperature
Storage Temperature
0 to 70
–55 to 125
Note: Permanent damage to the device may occur if the Absolute Maximun Ratings are exceeded. Functional operation should be restricted to
the recommended operation conditions. Exposure to higher than recommended voltages, for an extended period of time, could effect the
performance and reliability of this component.
Rev: 1.05 7/2001
9/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Package Thermal Characteristics
Rating
Layer Board
Symbol
RQJA
TQFP max PBGA max Unit
Notes
1,2
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
single
four
—
32
20
7
28
18
4
°C/W
°C/W
°C/W
RQJA
1,2
RQJC
Junction to Case (TOP)
Notes:
3
1. Junction temperature is a function of SRAM power dissapation, package thermal resistance, mounting board temperature, ambient.
Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
AC Test Conditions
Output load 1
(VDD = 3.135 V–3.6 V, TA = 0–70°C)
DQ
Parameter
Conditions
VIH = 2.3 V
VIL = 0.2 V
30pF1
50W
VT = 1.25 V
Input high level
Input low level
Input slew rate
FIG. 1
TR = 1 V/ns
1.25 V
Input reference level
Output reference level
Output load
Output load 2
2.5 V
1.25 V
Fig. 1& 2
225W
225W
DQ
Notes:
5pF1
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
FIG. 2
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
.
4. Device is deselected as defined by the Truth Table.
Rev: 1.05 7/2001
10/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
DC Characteristics and Supply Currents (Voltage reference to V = 0 V)
SS
(VDD = 3.135 V–3.6 V, Ta = 0–70°C for Commercial Temperature Offering)
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except ZZ, FT, LBO pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
VDD ³ VIN ³ VIH
0 V £ VIN £ VIH
–1 uA
–1 uA
1 uA
300 uA
IinZZ
IinM
Iol
ZZ Input Current
VDD ³ VIN ³ VIL
0 V £ VIN £ VIL
Mode Input Current
(FT & LBO pins)
–30 0uA
–1 uA
1 uA
1 uA
Output Disable,
VOUT = 0 to VDD
Output Leakage Current
–1 uA
1 uA
VOH
VOH
VOL
IOH = –4 mA, VDDQ = 2.375 V
IOH = –4 mA, VDDQ = 3.135 V
IOL = +4 mA
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
0.4 V
Rev: 1.05 7/2001
11/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Operating Currents
-166
-150
-133
-100
0
to
–40
to
0
to
–40
to
0
to
–40
to
0
to
–40
to
Parameter
Test Conditions
Symbol
Unit
70°C +85°C 70°C +85°C 70°C +85°C 70°C +85°C
IDD
Pipeline
Device Selected;
All other inputs
³ VIH Or £ VIL
310
190
30
320
200
40
275
190
30
285
200
40
250
140
30
260
150
40
190
140
30
200 mA
150 mA
Operating
Current
IDD
Output open
Flow Through
ISB
Pipeline
40
40
90
75
mA
mA
mA
mA
ZZ ³ VDD – 0.2 V
Standby Current
ISB
30
40
30
40
30
40
30
Flow Through
IDD
Pipeline
110
80
120
90
105
80
115
90
100
65
110
75
80
Device Deselected;
All other inputs
³ VIH OR £ VIL
Deselect Supply
Current
IDD
65
Flow Through
Rev: 1.05 7/2001
12/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
AC Electrical Characteristics
-166
-150
-133
-100
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
tKC
tKQ
6.0
—
—
3.5
—
6.7
—
—
3.8
—
7.5
—
—
4
10
—
—
4.5
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
1.5
1.5
—
1.5
1.5
—
1.5
1.5
—
—
—
4
1.5
1.5
—
tLZ1
tKM
—
—
—
Clock to Match Valid
Pipeline
3.5
—
3.8
—
4.5
—
Clock to Match Invalid
Clock to Match in Low-Z
Clock Cycle Time
tKMX
1.5
1.5
10.0
—
1.5
1.5
10.0
—
1.5
1.5
15.0
—
—
—
—
11.0
—
—
11.0
—
—
—
—
4
1.5
1.5
15.0
—
tMLZ1
tKC
—
—
—
—
—
—
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
tKQ
8.5
—
10.0
—
12.0
—
tKQX
3.0
3.0
—
3.0
3.0
—
3.0
3.0
—
3.0
3.0
—
tLZ1
tKM
—
—
—
Clock to Match Valid
Flow-Thru
8.5
—
10.0
—
12.0
—
Clock to Match Invalid
Clock to Match in Low-Z
Clock HIGH Time
tKMX
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.5
1.7
1.5
—
3.0
3.0
1.7
1.9
1.5
—
3.0
3.0
2
tMLZ1
tKH
—
—
—
—
—
—
Clock LOW Time
tKL
—
—
2.2
1.5
—
—
tHZ1
tOE
Clock to Output in High-Z
OE to Output Valid
3.5
3.5
—
3.8
3.8
—
5
4
5
tOLZ1
OE to output in Low-Z
0
0
0
—
0
—
tOHZ1
tMOE
OE to output in High-Z
MOE to Match Valid
—
—
0
3.5
3.5
—
—
—
0
3.8
3.8
—
—
—
0
4
4
—
—
0
5
5
ns
ns
ns
ns
tMOLZ1
tMOHZ1
MOE to Match in Low-Z
MOE to Match in High-Z
—
4
—
5
—
3.5
—
3.8
—
—
Rev: 1.05 7/2001
13/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
AC Electrical Characteristics
-166
-150
-133
-100
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max
Setup time
Hold time
tS
tH
1.5
0.5
5
—
—
—
1.5
0.5
5
—
—
—
2.0
0.5
5
—
—
—
2.0
0.5
5
—
—
—
ns
ns
ns
tZZS2
ZZ setup time
tZZH2
tZZR
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.05 7/2001
14/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Write Cycle Timing
Burst Write
Deselected
Single Write
Write
CLK
tS tH
ADSP is blocked by CE1 inactive
t
t
tKC
KH
KL
ADSP
ADSC
tH
tS
ADSC initiated write
tS
tH
ADV
tS tH
ADV must be inactive for ADSP Write
WR2
WR3
WR1
A0–A17
tS tH
GW
tH
tS
BWE
tS
tH
BW1–
BW2
WR2
WR3
WR1
t
S tH
CE1 masks ADSP
CE1
CE2
CE3
OE
tS tH
Deselected with CE2
tS
tH
CE2 and CE3 only sampled with ADSP or ADSC
tS
tH
Write specified byte for 2a and all bytes for 2b, 2c& 2d
Hi-Z
DQ1–16
DQP1–2
D2c
D2d
D3a
D1a
D2a
D2b
tS
tH
DE
Rev: 1.05 7/2001
15/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Flow Through—Read Cycle Timing
Single Read
Single Read
CLK
tS tH
tKH
tKL
ADSP is blocked by CE1 inactive
tKC
ADSP
ADSC
tS tH
ADSC initiated read
tS
tH
Suspend Burst
Suspend Burst
ADV
tS
tH
RD1
RD2
RD3
A0–A17
tS
tH
GW
tS
tH
BWE
BW1–
BW2
tH
tS
CE1 masks ADSP
CE1
CE2
CE3
tH
tS
CE2 and CE3 only sampled with ADSP or ADSC
Deselected with CE2
tS tH
tOE
OE
tOHZ
Q1a
tKQX
tKQX
tOLZ
Hi-Z
DQ1–16
DQP1–2
Q2b
Q2c
Q3a
Q2a
Q2d
tLZ
tKQ
tHZ
Rev: 1.05 7/2001
16/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Flow Through—Read/Write Cycle Timing
Burst Read
Single Write
Single Read
CLK
tKC
tS tH
tKH
ADSP is blocked by CE1 inactive
tKL
ADSP
ADSC
ADSC initiated read
tS tH
tS
tH
ADV
tS tH
RD2
WR1
RD1
A0–A17
tS
tH
GW
tS
tH
BWE
tS tH
BW1–
BW2
WR1
tH
tS
CE1 masks ADSP
CE1
CE2
tS
tH
CE2 and CE3 only sampled with ADSP and ADSC
t
S tH
Deselected with CE3
CE3
OE
tOHZ
tOE
tKQ
tS
tH
Hi-Z
DQ1–16
DQP1–2
Q1a
D1a
Q2a
Q2a
Q2b
Q2c
Q2d
tS
tH
Burst wrap around to its initial state
DE
Rev: 1.05 7/2001
17/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Pipeline—Read Cycle Timing
Single Read
Burst Read
CLK
tS tH
tKH
tKL
ADSP is blocked by CE1 inactive
tKC
ADSP
ADSC
tS tH
ADSC initiated read
tS
tH
Suspend Burst
ADV
tS tH
RD1
RD3
A0–A17
RD2
tS
tH
GW
tS
tH
BWE
BW1–
BW4
tH
tS
CE1 masks ADSP
CE1
CE2
CE3
tH
tS
CE2 and CE3 only sampled with ADSP or ADSC
Deselected with CE2
tS tH
tOE
OE
tOHZ
tKQX
Q3a
tHZ
tKQX
Q2a
tOLZ
tLZ
Hi-Z
DQ1–16
DQP1–2
Q1a
Q2b
Q2d
Q2c
tKQ
Rev: 1.05 7/2001
18/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Pipeline—Read/Write Cycle Timing
Single Write
Single Read
Burst Read
CLK
tKC
t
tS H
tKH
ADSP is blocked by CE1 inactive
tKL
ADSP
ADSC
ADSC initiated read
tS tH
tS
tH
ADV
tS
tH
RD2
WR1
RD1
A0–A17
tS
tH
GW
tS
tH
BWE
tS tH
WR1
BW1–
BW4
tH
tS
CE1 masks ADSP
CE1
CE2
CE3
tS
tH
CE2 and CE3 only sampled with ADSP and ADSC
t
S tH
Deselected with CE3
tOHZ
tOE
OE
tS
tKQ
tH
Hi-Z
DQ1–16
DQP1–2
D1a
Q2a
Q1a
Q2b
Q2c
Q2d
tS
tH
DE
Rev: 1.05 7/2001
19/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Flow Through—Compare/Fill Write Cycle Timing
CLK
t
t
S
H
CE(1)
W(2)
OE
B
B
B
A0-A17
A
A
DQ1-16
DQP1-2
DE
t
t
KM
t
KM
KM
MOE
MATCH
t
t
MOE
t
KMX
Match high when chip deselected
MLZ
Fill Write
Hit
Miss
Notes:
1. CE = L is defined as CE1=L, CE2=H and CE3=L
2. W = L is the Asertive function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
Rev: 1.05 7/2001
20/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Pipeline—Compare/Fill Write Cycle Timing
CLK
t
t
S
H
CE(1)
W(2)
OE
B
B
B
A0-A17
A
A
DQ1-16
DQP1-2
DE
t
t
KM
t
KM
KM
MOE
MATCH
t
t
MOE
KMX
Match high when chip deselected
t
MLZ
Hit
Miss
Fill Write
Notes:
1. CE = L is defined as CE1=L, CE2=H and CE3=L
2. W = L is the Asertive function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
Rev: 1.05 7/2001
21/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
ZZ Timing
CLK
tKC
tS tH
tKH
tKL
ADSP
ADSC
ZZ
tZZR
tZZS
tZZH
Snooze
Rev: 1.05 7/2001
22/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Test Mode Description
Functional Description
The GS84118 provides JTAG boundary scan interface using IEEE standard 1149.1 protocol. The Test mode is intended to provide
a mechanism for testing the interconnect between master (processor, controller, etc.), SRAM, other components and the Printed
Circuit Board.
Test Access Port (TAP)
Four pins (as defined in Pin Description Tables) are used to performed JTAG functions. TDI input is used to scan test data serially
into one of three registers (Instruction Register, Boundary Scan Register and Bypass Register). TDO is the output pin to serially
output scan test data. The TDI sends the data into the LSB of the selected register and the MSB of that register feeds the data to
TDO. TMS input pin controls the state transition of 16 state TAP controllers, as specified in IEEE standard 1149.1. Inputs on TDI
and TMS are registered on the rising edge of TCK clock, and the output data on TDO is presented on the falling edge of TCK. The
TDO driver is in active state only when TAP controller is in Shift-IR state or in Shift -DR state.
TAP Controller
Sixteen state controllers are implemented as specified in IEEE standard 1149.1.
The controller enters the Reset state either through
• Power up or
• Apply logic 1 on TMS input pin on 5 consecutive rising edges.
Tap Controller State Diagram
1
Test Logic Reset
0
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
1
1
1
1
Capture DR
0
Capture IR
0
0
0
Shift DR
1
Shift IR
1
Exit1 DR
0
Exit1 IR
0
0
0
0
0
Pause DR
1
Pause IR
1
Exit2 DR
1
Exit2 IR
1
Update DR
Update IR
1
0
1
0
Rev: 1.05 7/2001
23/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Instruction Register (3 Bits)
The JTAG Instruction register is consisted of shift register stage and parallel output latch. The register is 3 bits wide and is encoded
as follow:
Octal
MSB
—
0
LSB
Instruction
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
Bypass
IDCODE—Read device ID
Sample-Z—Sample Inputs and tri-state DQs, Match
Bypass
0
1
1
0
Sample—Sample Inputs
Private—Manufacturer use only
Bypass
0
1
1
Bypass
Bypass Register (1 Bit)
The Bypass Register is one bit wide and is connected electrically between TDI and TDO and provides the minimum length serially
path between TDI and TDO.
ID Register (32 Bits)
The ID Register are 32 bits wide and are listed as follow:
Header
ID[0]
1
101 1001
ID[7:1]
GSI ID
(89 decimal in bank 2)
ID[11:8]
ID[27:12]
ID[31:28]
0001
Part Number
0000 0000 0000 0000
xxxx
Revision Number
Rev: 1.05 7/2001
24/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Boundary Scan Register (54 Bits)
The Boundary Scan Register are 54 bits wide and are listed as follow:
DQx, Match
Address
19
18
5
GW, BWE, BW1-2, DE
CE1, CE2, CE3
OE, MOE
3
2
ADSP, ADSC, ADV
ZZ, FT, LBO
CLK
3
3
1
Total
54
Scan Order (Order by exit sequence)
Order
Signal
TQFP
BGA
Order
Signal
TQFP
BGA
1
2
3
4
5
6
7
8
A15
A14
A13
A12
A11
A16
A17
MOE
DE
MATCH
DQ1
DQ2
DQ3
DQ4
ZZ
DQ5
DQ6
DQ7
DQ8
DQP1
A10
A9
A8
ADV
ADSP
ADSC
OE
44
45
46
47
48
49
50
51
52
53
58
59
62
63
64
68
69
72
73
74
80
81
82
83
84
85
86
3T
2T
5T
6R
5C
5B
6C
6P
7N
6M
7P
6N
6L
7K
7T
6H
7G
6F
7E
6D
6T
6A
5A
4G
4A
4B
4F
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
BWE
GW
87
88
89
92
93
94
97
98
99
100
8
4M
4H
4K
6B
5L
3G
2B
4E
3A
2A
1D
2E
2G
1H
5R
2K
1L
2M
1N
2P
3R
2C
3B
3C
2R
4N
4P
CLK
CE3
BW1
BW2
CE2
CE1
A7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
A6
DQ9
DQ10
DQ11
DQ12
FT
DQ13
DQ14
DQ15
DQ16
DQP2
LBO
A5
9
12
13
14
18
19
22
23
24
31
32
33
34
35
36
37
A4
A3
A2
A1
A0
Rev: 1.05 7/2001
25/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Test Mode AC Electrical Characteristics
Parameter
TCK Cycle Time
Symbol
tTKC
tTKQ
tTKH
tTKL
Min
20
—
10
10
5
Max
—
Unit
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
10
—
ns
ns
—
ns
tTS
—
ns
tTH
5
—
ns
Test Mode Timing Diagram
t
t
TKH
TKL
t
TKC
TCK
TMS
TDI
t
t
TH
TS
TDO
t
TKQ
Rev: 1.05 7/2001
26/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Package Dimensions—100-Pin TQFP
q
L
c
L1
e
b
A1
A2
E1
E
Symbol
Description
Standoff
Min.
0.05
1.35
0.20
0.09
21.9
19.9
15.9
13.9
Nom.
0.10
Max
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
A1
A2
B
Body Thickness
Lead Width
1.40
0.30
C
Lead Thickness
Terminal Dimension
Package Body
Terminal Dimension
Package Body
Lead Pitch
D
22.0
20.0
16.0
14.0
0.65
0.60
1.00
D1
E
E1
E
L
Foot Length
0.45
0.75
L1
Y
Lead Length
Coplanarity
0.10
Q
Lead Angle
0°
7°
Notes:
1. All dimesnions are in millimeters (mm).
2. Package wideth and length do not include mold protrusion.
Rev: 1.05 7/2001
27/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Package Dimesions - 119 Pin PBGA
Pin 1
Corner
A
7 6 5 4 3 2
1
A
B
C
D
E
F
G
H
J
G
D
B
P
S
K
L
M
N
P
R
T
U
R
N
Bottom View
Top View
Package Dimesions - 119 Pin PBGA
Symbo
l
Min Nom Ma
Description
.
.
x
A
Width
13.8 14.0 14.2
21.8 22.0 22.2
B
Length
C
Package Height (including ball)
Ball Size
-
2.40
D
0.60 0.75 0.90
E
Ball Height
0.50 0.60 0.70
F
Package Height (excluding balls)
Width between Balls
Package Height above board
Cut-out Package Width
Foot Length
1.46 1.70
G
1.27
K
0.80 0.90 1.00
N
12.00
19.50
7.62
P
R
Width of package between balls
Length of package between balls
Variance of Ball Height
S
T
20.32
0.15
Unit: mm
Side View
BPR 1999.05.18
Rev: 1.05 7/2001
28/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
Ordering Information
2
T
3
Speed
A
1
Org
Type
Package
Status
Part Number
(MHz/ns)
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
Notes:
GS84118T-166
GS84118T-150
GS84118T-133
GS84118T-100
GS84118T-166I
GS84118T-150I
GS84118T-133I
GS84118T-100I
GS84118B-166
GS84118B-150
GS84118B-133
GS84118B-100
GS84118B-166I
GS84118B-150I
GS84118I-133I
GS84118B-100I
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
BGA
166/8.5
150/10
133/11
100/12
166/8.5
150/10
133/11
100/12
166/8.5
150/10
133/11
100/12
166/8.5
150/10
133/11
100/12
C
C
C
C
I
I
C
I
C
C
C
C
I
BGA
BGA
BGA
BGA
BGA
I
BGA
C
I
BGA
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032T-7.5T.
2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline / Flow through mode selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
Rev: 1.05 7/2001
29/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS84118T/B-166/150/130/100
4Mb Synchronous Tag RAM Datasheet Revision History
Types of Changes
Rev. Code: Old;New
Page /Revisions;Reason
Format or Content
• Updated BGA Pin Description to meet JEDEC standard
GS84118-2000207; 84118_r1_01
Content
• Updated format to comply with Technical Publications
standards
84118_r1_02; 84118_r1_03
84118_r1_03; 84118_r1_04
Content/Format
Content
• Corrected typo in TQFP Package Description table on page
27
• Updated Pinout on page 3
• Updated Pin Description tables for TQFP and PBGA
• Added overbar to all references of BWE, BW1, BW2, GW,
CE1, CE3, OE, ADV, ADSP, ADSC, MOE, DE, FT, and LBO
• Removed VDD note from AC Electrical Characteristics table
• Imported up-to-date Package Drawing for 119 PBGA
• Reordered pin location listings in pin description tables on
pages 4 and 5
• Removed Global Write reference from BWE description in pin
description tables
• Removed BWE reference from GW description in pin
description tables
84118_r1_04; 84118_r1_05
Content
• Placed overbars on Write references in Synchronous Truth
Table
Rev: 1.05 7/2001
30/30
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
相关型号：
©2020 ICPDF网 联系我们和版权申明