GS841E18AGB-150T [GSI]
Cache Tag SRAM, 256KX18, 10ns, CMOS, PBGA119, ROHS COMPLIANT, FBGA-119;
| 型号： | GS841E18AGB-150T |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Cache Tag SRAM, 256KX18, 10ns, CMOS, PBGA119, ROHS COMPLIANT, FBGA-119 静态存储器 |
| 文件： | 总21页 (文件大小：488K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS841E18AT/B-180/166/150/130/100
180 MHz–100 MHz
TQFP, BGA
Commercial Temp
Industrial Temp
256K x 18 Sync
Cache Tag
3.3 V V
DD
3.3 V and 2.5 V I/O
Output registers and the Match output register are provided and
controlled by the FT mode pin (Pin 14). Through use of the FT mode
pin, I/O registers can be programmed to perform pipeline or flow
through operation. Flow Through moreduces latency.
Features
• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O
supply
• Dual Cycle Deselect (DCD)
• Intergrated data comparator for Tag RAM application
• FT mode pin for flow through or pipeline operation
Byte write operation is performed by using Byte Write Enable (BWE)
input combined with two individual byte write signals BW1-2. In
addition, Global Write (GWs available for writing all bytes at one
time.
TM
• LBO pin for Linear or Interleave (Pentium and X86) Burst
mode
• Synchronous address, data I/O, and control inputs
• Synchronous Data Enable (DE)
• Asynchronous Output Enable (OE)
Compare cycles begin as a read cycle with output disabled so that
compare data can be loaded into the data input register. The
comparator compares the read data with the registered input data and a
match signal is gnerated. The match output can be either in Pipeline
or Flow Through modes controlled by the FT signal.
• Asynchronous Match Output Enable (MOE)
• Byte Write (BWE) and Global Write (GW) operation
• Three chip enable signals for easy depth expansion
• Internal self-timed write cycle
• JTAG Test mode conforms to IEEE standard 1149.1
• JEDEC-standard 100-lead TQFP package and 119-BGA
• RoHS-compliant 100-lead TQFP and 119-bump BGA
packages available
Low pow(Standby mode) is attained through the assertion of the ZZ
signal, or by stopping the clock (CLK). Memory data is retained
during Standby mode.
JTAG boundary scan interface is provided using IEEE standard
1149.1 protocol. Four pins—Test Data In (TDI), Test Data Out
(TDO), Test Clock (TCK) and Test Mode Select (TMS)—are used to
perform JTAG function.
Functional Description
The GS841E18A is a 256K x 18 high performance synchronous DCD
SRAM with integrated Tag RAM comparator. A 2-bit burst counter is
The GS841E18A operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate output
(VDDQ) pins are used to allow both 3.3 V or 2.5 V IO interface.
included to provide burst interface with PentiumTM and other high
performance CPUs. It is designed to be used as a Cache Tag SRAM,
as well as data SRAM. Addresses, data IOs, match output, chip
enables (CE1, CE2, CE3), address control inputs (ADSP, ADSC,
ADV), and write control inputs (BW1, BW2, BWE, GW, DE) are
synchronous and are controlled by a positive-edge-triggered clock
(CLK).
Dual Cycle Deselect (DCD)
The GS841E18A is a DCD pipelines synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. DCD SRAMs hold the deselect command for one full
cycle and then begin turning off their outputs just after the second
rising edge of the clock.
Output Enable (OE), Match Output Enable, and power down control
(ZZ) are asynchronous. Burst can be initiated with either ADSP or
ADSC inputs. Subsequent burst addresses are generated internally and
are controlled by ADV. The burst sequence is either interleave order
(PentiumTM or x86) or linear order, and is controlled by LBO.
Parameter Synopsis
–180
-166
-150
-133
-100
t
t
cycle
5.5 ns
3.2 ns
6.0 ns
3.5 ns
6.6 ns
3.8 ns
7.5 ns
4.0 ns
10 ns
4.5 ns
Pipeline
3-1-1-1
t
KQ
335 mA 310 mA 275 mA 250 mA 190 mA
I
DD
t
KQ
Flow
Through
2-1-1-1
8 ns
9.1 ns
8.5 ns
10 ns
10 ns
10 ns
11 ns
15 ns
12 ns
15 ns
cycle
210 mA 190 mA 190 mA 140 mA 140 mA
I
DD
Rev: 1.03b 2/2008
1/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. * Pentium is a trademark of Intel
GS841E18AT/B-180/166/150/130/100
Pin Configuration (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
NC
NC
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
V
V
DDQ
DDQ
V
V
SS
SS
NC
DQP
DQ
DQ
NC
NC
D
DQ
256K x 18
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
VDDQ
DQ
DQ
V
NC
V
ZZ
DQ
DQ
V
Top View
V
DDQ
DQ
DQ
FT
SS
V
DD
NC
DD
V
SS
DQ
DQ
V
DDQ
DDQ
V
V
SS
SS
DQ
DQ
NC
NC
V
V
DQ
DQ
DQP
NC
V
SS
SS
V
DDQ
DDQ
NC
NC
NC
MATCH
DE
MOE
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either V or V . These pins can also be left floating.
DD
SS
Rev: 1.03b 2/2008
2/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
GS841E18A PadOut—119-Bump BGA—Top View (Package B)
1
2
A
3
A
A
A
4
5
A
A
A
6
A
7
A
B
C
D
E
F
V
ADSP
ADSC
V
DDQ
DDQ
NC
E2
E3
NC
NC
A
V
A
NC
NC
DD
DQB
NC
NC
DQB
NC
DQB
NC
V
V
V
NC
E1
V
V
V
DQP
NC
DQA
NC
DQA
SS
SS
SS
SS
SS
SS
DQA
V
G
V
DDQ
DDQ
G
H
J
NC
BB
ADV
GW
NC
DQA
DQB
V
V
NC
SS
SS
V
V
N
V
NC
V
V
DDQ
DDQ
DD
DD
DD
K
L
NC
DQB
NC
DQB
NC
DQP
A
V
CK
NC
BW
A1
V
NC
DQA
MATCH
DQA
MOE
A
DQA
SS
SS
DQB
NC
BA
NC
V
V
V
V
DDQ
M
N
P
R
T
DDQ
SS
SS
SS
SS
SS
SS
DB
V
V
V
V
DE
NC
NC
NC
A0
DQA
NC
ZZ
LBO
A
V
FT
A
DD
A
NC
A
V
TMS
TDI
TCK
TDO
NC
V
DDQ
U
DDQ
Rev: 1.03b 2/2008
3/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
TQFP Pin Description
Symbol
Description
Address Input Signals—Inputs are registered and must meet setup and hold times, as specified on
An
page 11.
CLK
BWE
Clock Input Signal
Byte Write Enable Signal—The byte write enable signal needs to be combined with one of the four
byte write signals for a write operation to occur.
BW1
BW2
Byte Write signal for data outputs 1 thru 8
Byte Write signal for data outpus 9 thru 16
GW
Global Write Enable
CE1,CE2, CE3
OE
Chip Enables
Output Enable
ADV
Burst address advance
ADSP, ADSC
DQ
Address status signals
Data Input and Output pins
DQP
Parity Input and Output pins
MATCH
MOE
DE
Match Output
Match Output Enable
Data Enable—Data input registers are updated only when DE is active.
ZZ
Power down control—Application of ZZ will result in a low standby power consumption.
FT
Flow Through or Pipeline mode
Linear Order Burst mode
Test Mode Select
Test Data In
LBO
TMS
TDI
TDO
Test Data Out
TCK
Test Clock
V
3.3 V power supply
DD
V
Ground
2.5 V/3.3 V output power supply
No Connect
SS
V
DDQ
NC
Rev: 1.03b 2/2008
4/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
PBGA Pin Description
Symbol
Description
Address Input Signals—Inputs are registered and must meet setup and hold times, as specified on
An
page 11.
CLK
BWE
Clock Input Signal
Byte Write Enable Signal—The byte write enable signal needs to e combined with one of the four
byte write signals for a write operation o occur.
BW1
BW2
Byte Write signal for data outputs 1 thru 8
Byte Write signal for data ouuts 9 thru 16
GW
Global Write Enable
CE1,CE2, CE3
OE
Chip Enables
Output Enable
ADV
Burst address advance
ADSP, ADSC
DQ
Address status signals
Data Input and Output pins
DQP
Parity Input and Output pins
MATCH
MOE
DE
Match Output
Match Output Enable
Data Enable—Data input registers are updated only when DE is active.
ZZ
Power down control—Application of ZZ will result in a low standby power consumption.
FT
Flow Through or Pipeline mode
Linear Order Burst mode
Test Mode Select
Test Data In
LBO
TMS
TDI
TDO
Test Data Out
TCK
Test Clock
V
3.3 V power supply
DD
V
Ground
2.5 V/3.3 V output power supply
No Connect
SS
V
DDQ
NC
Rev: 1.03b 2/2008
5/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Functional Block Diagram
18
REGISTER
A0-17
D
Q
A0
A0
A1
D0
D1
Q0
A1
BINARY
COUNTER Q1
18
A
Load
LBO
ADV
256K X 18
Memory
CLK
Array
ADSC
ADSP
Q
D
GW
Register
18
BWE
BW1
18
D
Q
2
Register
D
Q
BW2
DE
Register
D
Q
Regis
CE1
CE2
D
Q
CE3
Powerdown
Control
Register
ZZ
D
Q
FT
OE
MOE
A, DQ,
Control
18
54
Bodary Scan
Registers
DQ1-16
DQP1-2
Match
always (Ø)
Bypass Reg
ID Reg.
TDI
TDO
Instruction Reg.
TMS
TCK
TAP
Controller
Rev: 1.03b 2/2008
6/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Mode Pin Function
LBO
Function
Linear Burst
FT
L
Function
Flow Through
Pipeline
L
H or NC
Interleaved Burst
H or NC
Power Down Control
ZZ
L or NC
H
Function
Active
Standby, IDD = ISB
Note:
There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above tables.
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Byte Write Function
GW BWE BW1 BW2
Function
Read
H
H
L
H
L
X
L
L
L
X
H
X
L
X
H
X
L
Read
Write all bytes
Write all bytes
Write byte 1
Write byte 2
H
H
H
L
H
L
H
Note: H = logic high, L = logic low, NC = no connect
Rev: 1.03b 2/2008
7/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Synchronous Truth Table
Operation
Address Used
none
CE1 CE2 CE3 ADSP ADSC ADV Write OE CLK
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
H
L
X
L
X
X
H
X
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
none
none
L
X
L
L
none
L
H
H
L
none
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
external
external
external
external
external
next
L
X
X
L
L-H
L-H High-Z
L-H
L-H High-Z
Q
L
L
L
H
L
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
Q
L
L
L
H
X
L
L
L
L
L-H
L-H
D
Q
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
next
L
H
L
L-H High-Z
L-H
L-H High-Z
next
L
Q
next
L
H
X
X
L
next
L
L-H
L-H
L-H
D
D
Q
next
L
L
current
current
current
current
currt
rrent
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H High-Z
L-H
L-H High-Z
Q
H
X
X
L-H
L-H
D
D
L
Notes:
1. X means “don’t care,” H means “logic high,” L means “logic low.”
2. Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
3. All inputs, except OE, must meet setup and hold on rising edge of CLK.
4. Suspending busrt generates a wait cycle.
5. ADSP LOW along with SRAM being selected always initiates a Read cycle at the L-H edge of the clock (CLK).
6. A Write cycle can only be performed by setting Write low for the clock L-H edge of the subsequent wait cycle.
Refer to page 12 for te Write timing diagram.
Rev: 1.03b 2/2008
8/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Truth Table For Read/Write/Compare/Fill Write Operation
CE
L
Write
DE
X
MOE
OE
L
Match
—
DQ
Q
Read
Write
H
L
X
X
L
L
L
H
—
D
Compare
Fill Write
L
H
L
L
H
Data Out
—
D
L
H
X
X
L
X
X
Match Deselect
Deselect
H
H
X
X
X
High
High Z
High Z
High Z
X
H
X
Notes:
1. X means “don’t care,” H means “logic high,” L means “logic low.”
2. Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.
3. CE is defined as CE1=L, CE2=H and CE3=L
4. All signals are synchronous and are sampled by CLK except OE and MOE. OE and ME are asynchronous and drive the bus immediately.
)
Absolute Maximum Ratings (Voltage reference to V = 0 V)
SS
Symbol
Description
Supply Voltage
Commerical
Unit
V
–0.5 to 4.6
V
V
V
DD
V
–0.5 to V
Output Supply Voltage
CLK Input Voltage
DDQ
DD
V
–0.5 to 6
CLK
–0.5 to V + 0.5
DD
V
Input Voltage
V
V
in
(≤ 4.6 V max. )
–0.5 to V + 0.5
DD
V
Output Voltage
out
(≤ 4.6 V max. )
I
Output Current per I/O
Power Dissipation
+/–20
mA
W
out
P
1.5
D
o
T
Operating Temperature
Storage Temperature
0 to 70
C
OPR
o
T
–55 to 125
C
STG
Note:
Permanent damage to the device may occur if the Absolute Maximun Ratings are exceeded. Functional operation should be restricted to the
recommended operation conditions. Exposure to higher than recommended voltages, for an extended period of time, could effect the
performance and reliability of this component.
Rev: 1.03b 2/2008
9/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Package Thermal Characteristics
Rating
Layer Board
Symbol
TQFP max PBGA max Unit
Notes
1,2
R
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
single
four
—
32
20
7
28
18
4
°C/W
°C/W
°C/W
ΘJA
R
1,2
ΘJA
R
3
ΘJC
1. Junction temperature is a function of SRAM power dissapation, package thermal resistance, mounng board temperature, ambient.
Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
Output load 1
AC Test Conditions
(VDD = 3.135 V–3.6 V, Ta = 0–70°C)
DQ
Parameter
Conditions
1
30pF
50W
V
= 23 V
Input high level
IH
VT = 1.25 V
V = 0.2 V
Input low level
Input slew rate
IL
FIG. 1
R = 1 V/ns
1.25 V
Output load 2
2.5 V
Input reference level
Output reference level
Output load
1.25 V
Fig. 1& 2
225W
225W
DQ
1
Notes:
1. Include scope and jig capacitance.
5pF
FIG. 2
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noed.
3. Output load 2 for t , t , t
and t
.
OHZ
LZ HZ OLZ
4. Device is deselected as defined by the Truth Table.
Rev: 1.03b 2/2008
10/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
DC Characteristics and Supply Currents (Voltage reference to V = 0 V)
SS
(VDD = 3.135 V–3.6 V, Ta = 0–70°C for Commercial Temperature Offering)
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except ZZ, FT, LBO pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
V
≥ V ≥ V
IN
–1 uA
–1 uA
1 uA
300 uA
DD
IH
Iin
ZZ Input Current
ZZ
0 V ≤ V ≤ V
IN
IH
V
≥ V ≥ V
IN
Mode Input Current
(FT & LBO pins)
–30 0uA
–1 uA
1 uA
1 uA
DD
IL
Iin
I
M
0 V ≤ V ≤ V
IN
IL
Output Disable,
V
Output Leakage Current
–1 uA
1 uA
ol
= 0 to V
OUT
DD
V
V
I
I
= –4 mA, V
= –4 mA, V
= 2.375 V
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
OH
OH
OH
OH
DDQ
DDQ
= 3.135 V
V
I
= +4 mA
OL
0.4 V
OL
Rev: 1.03b 2/2008
11/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Operating Currents
-180
-166
-150
-133
-100
0
to
–40
to
0
to
–40
to
0
to
–40
to
0
to
–40
to
0
to
–40
to
Parameter
Test Conditions
Symbol
Unit
70°C 85°C 70°C +85°C 70°C +85°C 70°C +85°C 70°C +85°C
I
DD
335
210
20
345
220
30
310
190
30
320
200
40
275
190
30
285
200
40
250
140
30
260
150
40
190
140
30
200 mA
150 mA
40 mA
40 mA
90 mA
75 mA
Device Selected;
All other inputs
≥ V Or ≤ V
Pipeline
Operating
Current
I
DD
IH
IL
Flow
Through
Output open
I
SB
Pipeline
Standby
Current
ZZ ≥ V – 0.2 V
DD
I
SB
20
30
30
40
30
40
30
40
30
Flow
Through
I
DD
55
65
110
80
120
90
105
80
115
90
100
65
110
75
80
Pipeline
Device Deselected;
All other inputs
≥ V OR ≤ V
Deselect
Supply Current
I
DD
IH
IL
40
50
65
Flow
Through
Rev: 1.03b 2/2008
12/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
AC Electrical Characteristics
-180
-166
-150
-133
-100
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
tKC
tKQ
5.5
—
—
3.2
—
6.0
—
—
3.5
—
6.7
—
—
3.8
—
7.5
—
—
4
10
—
—
4.5
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
1.5
1.5
—
1.5
1.5
—
1.5
1.5
—
1.5
1.5
—
—
—
4
1.5
1.5
—
Clock to Output in Low-Z
—
—
—
—
Pipeline
tLZ1
tKM
Clock to Match Valid
Clock to Match Invalid
Clock to Match in Low-Z
Clock Cycle Time
3.2
—
3.5
—
3.8
—
4.5
—
tKMX
1.5
1.5
9.1
—
1.5
1.5
10.0
—
1.5
1.5
10.0
—
1.5
1.5
15.0
—
—
—
—
11.0
—
—
11.0
—
—
—
—
4
1.5
1.5
15.0
—
tMLZ1
tKC
—
—
—
—
—
—
—
—
Clock to Output Valid
Clock to Output Invalid
tKQ
8.0
—
8.5
—
10.0
—
12.0
—
tKQX
3.0
3.0
—
3.0
3.0
—
3.0
3.0
—
3.0
3.0
—
3.0
3.0
—
Flow
Through
tLZ1
tKM
Clock to Output in Low-Z
—
—
—
Clock to Match Valid
8.5
—
8.5
—
10.0
—
12.0
—
Clock to Match Invalid
Clock to Match in Low-Z
Clock HIGH Time
tKMX
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.5
1.7
1.5
—
3.0
3.0
1.7
1.9
1.5
—
3.0
3.0
2
tMLZ1
tKH
—
—
—
—
—
—
—
—
Clock LOW Time
tKL
—
—
—
2.2
1.5
—
—
tHZ1
tOE
Clock to Output in High-Z
OE to Output Valid
3.2
3.2
—
3.5
3.5
—
3.8
3.8
—
5
4
5
tOLZ1
OE to output in Low-Z
0
0
0
0
—
0
—
tOHZ1
tMOE
OE to output in High-Z
MOE to Match Valid
—
—
0
3.2
3.2
—
—
—
0
3.5
3.5
—
—
—
0
3.8
3.8
—
—
—
0
4
4
—
—
0
5
5
ns
ns
ns
tMOLZ1
MOE to Match in Low-Z
—
—
tMOHZ1
MOE to Match in High-Z
Setup time
—
1.5
0.5
5
3.2
—
—
—
—
1.5
0.5
5
3.5
—
—
—
—
1.5
0.5
5
3.8
—
—
—
—
2.0
0.5
5
4
—
2.0
0.5
5
5
ns
ns
ns
ns
tS
tH
—
—
—
—
—
—
Hold time
tZZS2
ZZ setup time
tZZH2
tZZR
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.03b 2/2008
13/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Pipeline Mode Timing
Begin
Read A Cont
Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont
tKL
Deselect Deselect
tKH
tKC
CK
ADSP
tS
tS
ADSC initiated read
tH
ADSC
ADV
tS
tH
tH
A
B
C
Ao–An
GW
tS
tS
tH
tH
BW
tS
Ba–Bd
E1
tS
tS
tS
Deselected with E1
tH
E2 and E3 only sampled with ADSC
tH
tH
E2
E3
G
tS
D(B)
tKQ
tHZ
tOE
tOHZ
Q(A)
tH
tLZ
tKQX
Hi-Z
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
DQa–DQd
Rev: 1.03b 2/2008
14/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Flow Through Mode Timing
Begin
Read A Cont
tKH
Deselect Write B
Read C Read C+1 Read C+2 Read C+3 Read C Deselect
tKL
tKC
CK
Fixed High
ADSP
tS
tH
tS
tH
ADSC initiated read
ADSC
ADV
Ao–An
GW
tH
tS
tS
tH
tS
tH
A
B
C
tS
tH
tS
tH
BW
tH
tS
Ba–Bd
E1
tS
Deselected with E1
tH
E1 masks ADSP
tS
tH
E2 and E3 only sampled with ADSP and ADSC
E1 masks ADSP
E2
tS
tH
E3
G
tH
tS
tOE
tKQ
tKQX
tHZ
tOHZ
D(B)
tLZ
Q(A)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
DQa–DQd
Rev: 1.03b 2/2008
15/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Pipeline Compare Fill Write Cycle
Hit
Miss
Fill Write
K
Address
DQ
tH
tH
tH
tH
tS
tS
tS
tS
A
A
B
A
B
CE
W
G
tH
tS
DE
MOE
tKM
tMOE
tMLZ
tKM
tKMX
tKM
Match
Rev: 1.03b 2/2008
16/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Flow Through Compare Fill Write Cycle
Hit
Miss
Fill Write
K
Address
DQ
tH
tS
A
B
A
B
tH
tH
tH
tS
A
tS
CE
tS
tS
W
G
tH
DE
MOE
tKM
tMOE
tMLZ
tKM
tKMX
tKM
Match
Rev: 1.03b 2/2008
17/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
TQFP Package Drawing (Package T)
θ
L
c
Symbol
Description
Standoff
Min. Nom. Max
L1
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
0.10
7°
A1
A2
E1
E
θ
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.03b 2/2008
18/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Package Dimensions—119-Bump FPBGA (Package GB (MCM), Variation 2)
TOP VIEW
BOTTOM VIEW
A1
S
A1
Ø0.10
C
S
S
S
Ø0.30 C A
B
Ø0.60~0.90 (119x)
1
2
3
4
5
6
7
7
6
5
4 3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
M
N
P
K
L
M
N
P
R
T
U
R
T
U
B
1.27
7.62
14±0.10
A
0.20(4x)
SEATING PLANE
C
Rev: 1.03b 2/2008
19/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Ordering Information
Org
2
Speed
3
1
Type
Package
T
Part Number
A
(MHz/ns)
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
GS841E18AT-180
GS841E18AT-166
GS841E18AT-150
GS841E18AT-133
GS841E18AT-100
GS841E18AT-180I
GS841E18AT-166I
GS841E18AT-150I
GS841E18AT-133I
GS841E18AT-100I
GS841E18AGT-180
GS841E18AGT-166
GS841E18AGT-150
GS841E18AGT-133
GS841E18AGT-100
GS841E18AGT-180I
GS841E18AGT-166I
GS841E18AGT-150I
GS841E18AGT-133I
GS841E18AGT-100I
GS841E18AB-180
GS841E18AB-166
GS841E18AB-150
GS841E18AB-133
GS841E18AB-100
GS841E18AB-180I
GS841E18AB-166I
GS841E18AB-150I
GS841E18AI-133I
GS841E18AB-100I
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Throgh
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipele/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
TQFP
TQFP
180/8
166/8.5
150/10
133/11
100/12
180/8
C
C
C
C
C
I
TQFP
TQFP
TQFP
TQFP
TQFP
166/8.5
150/10
133/11
100/12
180/8
I
TQFP
I
TQFP
I
TQFP
I
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
119 BGA (var. 2)
C
C
C
C
C
I
166/8.5
150/10
133/11
100/12
180/8
166/8.5
150/10
133/11
100/12
180/8
I
I
I
I
C
C
C
C
C
I
166/8.5
150/10
133/11
100/12
180/8
166/8.5
150/10
133/11
100/12
I
I
I
256K x 18
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS841E18AT-166T.
2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline / Flow through mode selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
Rev: 1.03b 2/2008
20/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS841E18AT/B-180/166/150/130/100
Ordering Information
Org
2
Speed
3
1
Type
Package
T
Part Number
A
(MHz/ns)
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
GS841E18AGB-180
GS841E18AGB-166
GS841E18AGB-150
GS841E18AGB-133
GS841E18AGB-100
GS841E18AGB-180I
GS841E18AGB-166I
GS841E18AGB-150I
GS841E18AGB-133I
GS841E18AGB-100I
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (va. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
RoHS-compliant 119 BGA (var. 2)
180/8
166/8.5
150/10
133/11
100/12
180/8
C
C
C
C
C
I
166/8.5
150/10
133/11
100/12
I
I
I
256K x 18
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS841E18AT-166T.
2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline / Flow through mode selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
4Mb Synchronous Tag RAM Datasheet Revision History
Types of Changes
Rev. Code: Old;New
Page /Revisions;Reason
Format or Content
• Creation of new datasheet
GS841E18A_r1
• Moved TCK from U6 (incorrect placement) to U4 (correct
placement) on BGA
• Changed U6 to NC
GS841E18A_r1;
GS841E18A_r1_01
Content
• Updated format
• Added 180 MHz speed bin
• Updated timing diagrams
• Updated mechanical drawings
• Added Pb-Free info for TQFP
GS841E18A_r1_01;
GS841E18A_r1_02
Format/Content
Content
• Added Pipeline Compare Fill Write Cycle and Flow Through
Compare Fill Write Cycle timing diagrams
• (Rev1.03a: Added RoHS-compliant information for BGA)
• Rev1.03b: updated coplanarity for 119 BGA mechanical,
removed status column from Ordering Information table.
GS841E18A_r1_02;
GS841E18A_r1_03
Rev: 1.03b 2/2008
21/21
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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