GS841Z36AT-200IT [GSI]
ZBT SRAM, 128KX36, 7.5ns, CMOS, PQFP100, TQFP-100;
| 型号： | GS841Z36AT-200IT |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | ZBT SRAM, 128KX36, 7.5ns, CMOS, PQFP100, TQFP-100 静态存储器 |
| 文件： | 总30页 (文件大小：955K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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GS841Z18/36AT-200/180/166/150/100
100-Pin TQFP
Commercial Temp
Industrial Temp
4Mb Pipelined and Flow Through 200 MHz–100 MHz
3.3 V V
DD
Synchronous NBT SRAMs
2.5 V and 3.3 V V
DDQ
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Features
• 256K x 18 and 128K x 36 configurations
• User-configurable Pipelined and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered, address, data, and control
• ZZ Pin for automatic power-down
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS841Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
• JEDEC-standard 100-lead TQFP package
–200
–180
–166
–150
–100
tCycle 5.0 ns 5.5 ns 6.0 ns 6.6 ns
10 ns
4.5 ns
Pipeline
3-1-1-1
tKQ
IDD
3.0 ns 3.2 ns 3.5 ns 3.8 ns
205 mA 185 mA 170 mA 155 mA 105 mA
Flow
tKQ
7.5 ns
8 ns
8.5 ns
10 ns
12 ns
12 ns
15 ns
Through tCycle 8.8 ns 9.1 ns 10 ns
2-1-1-1
IDD
115 mA 115 mA 105 mA 100 mA 80 mA
The GS841Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
Functional Description
The GS841Z18/36AT is an 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
A
R
B
C
R
D
E
R
F
Read/Write
W
W
W
Flow Through
Data I/O
QA
DB
QC
DD
QE
DD
Pipelined
Data I/O
QA
DB
QC
QE
Rev: 1.00 10/2001
1/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Product Preview
GS841Z18/36AT-200/180/166/150/100
GS841Z18AT Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A17
NC
NC
VDDQ
VSS
NC
DQA9
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
VDDQ
4
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
FT
VDD
NC
VSS
DQB5
DQB6
VDDQ
5
6
7
8
9
256K x 18
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.00 10/2001
2/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Product Preview
GS841Z18/36AT-200/180/166/150/100
GS841Z36AT Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQB9
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
DQC9
DQC8
DQC7
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
VDDQ
4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
NC
VSS
DQD1
DQD2
VDDQ
5
6
7
8
9
128K x 36
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
DQA9
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
DQD9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.00 10/2001
3/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Product Preview
GS841Z18/36AT-200/180/166/150/100
100-Pin TQFP Pin Descriptions
Typ
e
Pin Location
Symbol
Description
37, 36
A0, A1
In
Burst Address Inputs—Preload the burst counter
35, 34, 33, 32, 100, 99, 82, 81,
50, 49, 48, 47, 46, 45, 44
A2–A16
In
Address Inputs
80
89
93
94
95
96
88
98
97
92
86
85
87
A17
CK
BA
In
In
In
In
In
In
In
In
In
In
In
In
In
I/O
I/O
Address Input (x18 Version Only)
Clock Input Signal
Byte Write signal for data inputs DQA1–DQA9; active low
Byte Write signal for data inputs DQB1–DQB9; active low
Byte Write signal for data inputs DQC1–DQC9; active low (x36 Version Only)
Byte Write signal for data inputs DQD1–DQD9; active low (x36 Version Only)
Write Enable; active low
BB
BC
BD
W
E1
Chip Enable; active low
E2
Chip Enable; active low; for self decoded depth expansion
Chip Enable; active low; for self decoded depth expansion
Output Enable; active low
E3
G
ADV
CKE
Advance / Load—Burst address counter control pin
Clock Input Buffer Enable; active low
58, 59, 62,63, 68, 69, 72, 73, 74 DQA1–DQA9
Byte A Data Input and Output pins (x18 Version Only)
Byte B Data Input and Output pins (x18 Version Only)
8, 9, 12, 13, 18, 19, 22, 23, 24
DQB1–DQB9
51, 52, 53, 56, 57, 75, 78, 79,
1, 2, 3, 6, 7, 25, 28, 29, 30
NC
—
No Connect (x18 Version Only)
51, 52, 53, 56, 57, 58, 59, 62,63 DQA1–DQA9
I/O
Byte A Data Input and Output pins (x36 Versions Only)
Byte B Data Input and Output pins (x36 Versions Only)
Byte C Data Input and Output pins (x36 Versions Only)
Byte D Data Input and Output pins (x36 Versions Only)
Power down control; active high
68, 69, 72, 73, 74, 75, 78, 79, 80 DQB1–DQB9 I/O
1, 2, 3, 6, 7, 8, 9, 12, 13
DQC1–DQC9
I/O
I/O
In
18, 19, 22, 23, 24, 25, 28, 29, 30 DQD1–DQD9
64
ZZ
FT
14
In
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
31
LBO
TMS
TDI
In
38
—
—
—
—
In
Scan Test Mode Select
39
Scan Test Data In
42
43
TDO
TCK
VDD
Scan Test Data Out
Scan Test Clock
15, 41, 65, 91
3.3 V power supply
5,10, 17, 21, 26, 40, 55, 60, 67,
71, 76, 90
VSS
In
Ground
VDDQ
NC
4, 11, 20, 27, 54, 61, 70, 77
42, 43,, 84, 16, 66
In
3.3 V output power supply for noise reduction
No Connect
—
Rev: 1.00 10/2001
4/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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GS841Z18/36AT-200/180/166/150/100
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
W
H
L
BA
X
BB
X
BC
X
BD
X
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A Write
Cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 1.00 10/2001
5/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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GS841Z18/36AT-200/180/166/150/100
Synchronous Truth Table
Operation
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Continue
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
Write Abort, Continue Burst
Clock Edge Ignore, Stall
Sleep Mode
Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes
D
D
D
D
R
B
None
None
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
None
X
H
X
H
X
H
X
H
X
X
X
H
L
1
External
Next
L-H
L-H
Q
Q
X
L
X
L
H
L
L
1,10
2
R
B
External
Next
H
H
X
X
X
X
X
X
L-H High-Z
X
L
X
L
H
L
L-H High-Z 1,2,10
W
B
External
Next
L-H
L-H
D
D
3
X
L
X
L
H
L
X
L
L
1,3,10
2,3
W
B
None
H
H
X
X
L-H High-Z
Next
X
X
X
X
X
X
H
X
X
X
X
X
L-H High-Z 1,2,3,10
Current
None
L-H
X
-
4
High-Z
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect
cycle is executed first
2. Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is
sampled low but no Byte Write pins are active, so no Write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write
cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.00 10/2001
6/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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GS841Z18/36AT-200/180/166/150/100
Pipeline and Flow Through Read-Write Control State Diagram
D
B
Deselect
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
W
R
Burst Read
Burst Write
B
B
D
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B and D represent input command
codes, as indicated in the Synchronous Truth Table.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram
Rev: 1.00 10/2001
7/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
R
B
W
B
Intermediate
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
Intermediate
D
Intermediate
W
R
High Z
B
D
Intermediate
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+2)
Intermediate State (N+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Intermediate
State
Current State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.00 10/2001
8/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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Flow Through Mode Data I/O State Diagram
R
B
W
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
D
W
R
High Z
B
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 1.00 10/2001
9/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin Name
State
L
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Burst Order Control
LBO
H or NC
L
Output Register Control
Power Down Control
FT
ZZ
H or NC
L or NC
H
Active
Standby, IDD = ISB
Note:
There are pull-up devices on the LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Rev: 1.00 10/2001
10/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
CK
tZZR
ZZ
Sleep
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Pin 66, a No Connect (NC) on GSI’s GS880Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36 NBT
SRAM, is often marked as a power pin on other vendor’s NBT-compatible SRAMs. Specifically, it is marked VDD or VDDQ on
pipelined parts and VSS on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity feature
may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode applications or
tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By using the pull-up
resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT SRAMs
(GS881Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active low, open
drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs.
Rev: 1.00 10/2001
11/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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Absolute Maximum Ratings
(All voltages reference to VSS
)
Symbol
VDD
VDDQ
VCK
Description
Value
Unit
Voltage on VDD Pins
–0.5 to 4.6
–0.5 to VDD
V
V
V
Voltage in VDDQ Pins
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 6
VI/O
–0.5 to VDDQ +0.5 (£ 4.6 V max.)
V
V
VIN
–0.5 to VDD +0.5 (£ 4.6 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
IIN
+/–20
+/–20
mA
mA
W
IOUT
PD
TSTG
TBIAS
1.5
oC
oC
–55 to 125
–55 to 125
Temperature Under Bias
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended
period of time, may affect reliability of this component.
Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
VDD
VDDQ
VIH
Min.
3.135
2.375
1.7
Typ.
3.3
2.5
—
Max.
3.6
Unit
V
Notes
VDD
I/O Supply Voltage
V
1
2
2
3
3
VDD +0.3
Input High Voltage
V
VIL
Input Low Voltage
–0.3
0
—
0.8
70
85
V
TA
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
25
°C
°C
TA
–40
25
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V £ VDDQ £ 2.375 V
(i.e., 2.5 V I/O) and 3.6 V £ VDDQ £ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC.
Rev: 1.00 10/2001
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Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 2.0 V
VSS
50%
VDD
50%
VSS – 2.0 V
20% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Input Capacitance
Symbol
Test conditions
VIN = 0 V
Typ.
Max.
Unit
pF
CIN
4
6
5
7
CI/O
VOUT = 0 V
Input/Output Capacitance
pF
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
RQJA
Max
40
Unit
Notes
1,2
single
four
—
°C/W
°C/W
°C/W
RQJA
24
1,2
RQJC
9
3
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient.
Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.00 10/2001
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AC Test Conditions
Parameter
Input high level
Input low level
Conditions
2.3 V
0.2 V
Input slew rate
1 V/ns
Input reference level
Output reference level
Output load
1.25 V
1.25 V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225W
225W
DQ
30pF*
50W
5pF*
VT = 1.25 V
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
VDD ³ VIN ³ VIH
0 V £ VIN £ VIH
–1 uA
–1 uA
1 uA
300 uA
IINZZ
IINM
IOL
ZZ Input Current
VDD ³ VIN ³ VIL
0 V £ VIN £ VIL
–300 uA
–1 uA
1 uA
1 uA
Mode Pin Input Current
Output Leakage Current
Output Disable,
VOUT = 0 to VDD
–1 uA
1 uA
VOH
VOH
VOL
IOH = –8 mA, VDDQ = 2.375 V
IOH = –8 mA, VDDQ = 3.135 V
IOL = 8 mA
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
—
—
—
0.4 V
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Operating Currents
-200
-180
-166
-150
-100
Parameter
Test Conditions Symbol
Unit
0 to –40to 0 to –40to 0 to –40to 0 to –40to 0 to –40to
70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C
IDD
Pipeline
Device Selected;
Operating All other inputs
225
135
20
235
145
30
205
135
20
215
145
30
190
125
20
200
135
30
175
120
20
185
130
30
125
100
20
135
110
30
mA
mA
mA
mA
mA
mA
Current
³ VIH or £ VIL
IDD
Flow-Thru
Output open
ISB
Pipeline
ZZ ³ VDD –
Standby
Current
0.2 V
ISB
Flow-Thru
20
30
20
30
20
30
20
30
20
30
IDD
Pipeline
Device
60
70
55
65
50
60
50
60
40
50
Deselect
Current
Deselected;
All other inputs
³ VIH or £ VIL
IDD
Flow-Thru
45
55
40
50
40
50
35
45
35
45
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AC Electrical Characteristics
-200
-180
-166
-150
-100
Parameter
Symbol
Unit
Min
5.0
—
Max
—
Min
5.5
—
Max
—
Min
6.0
—
Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock Cycle Time
tKC
tKQ
—
3.5
—
6.7
—
—
3.8
—
10
—
—
4.5
—
—
—
12.0
—
—
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.0
—
3.2
—
Pipeline
tKQX
1.5
1.5
8.8
—
1.5
1.5
9.1
—
1.5
1.5
10.0
—
1.5
1.5
12.0
—
1.5
1.5
15.0
—
tLZ1
tKC
—
—
—
—
—
—
—
—
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKQ
7.5
—
8.0
—
8.5
—
10.0
—
Flow
Through
tKQX
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
tLZ1
tKH
tKL
—
—
—
—
—
—
—
—
Clock LOW Time
—
—
—
—
tHZ1
tOE
Clock to Output in High-Z
G to Output Valid
3.0
3.0
—
3.2
3.2
—
3.5
3.5
—
3.8
3.8
—
5
tOLZ1
G to output in Low-Z
0
0
0
0
0
—
tOHZ1
tS
G to output in High-Z
Setup time
—
1.5
0.5
5
3.0
—
—
—
—
1.5
0.5
5
3.2
—
—
—
—
1.5
0.5
5
3.5
—
—
—
—
1.5
0.5
5
3.8
—
—
—
—
2.0
0.5
5
5
ns
ns
ns
ns
—
—
—
Hold time
tH
tZZS2
ZZ setup time
tZZH2
tZZR
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
20
20
20
20
20
Rev: 1.00 10/2001
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Pipeline Mode Read/Write Cycle Timing
1
2
3
4
5
6
7
8
9
10
CK
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
tKH tKL tKC
CKE
E*
ADV
W
Bn
tH
A1
A2
A3
A4
A5
A6
A7
A0–An
tKQ
tKHQZ
tGLQV
tKQHZ
tKQLZ
D
Q
(A4+1)
DQA–DQD
D(A2)
Q(A3)
Q(A4)
Q(A6)
D(A1)
D(A5)
(A2+1)
tKQX
tH
tS
tOEHZ
tOELZ
G
Write
D(A5)
Write
D(A2) Write
D(A2+1)
BURST Read
Q(A3)
Read
Q(A4) Read
Q(A4+1)
BURST
Read
Q(A6)
DESELECT
Write
D(A1)
Write
D(A7)
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
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Pipeline Mode No-Op, Stall and Deselect Timing
2
8
4
3
5
6
10
7
9
1
CK
tH
tH
tH
tS
tS
tS
CKE
E*
ADV
tS
tH
W
Bn
A0–An
DQ
A1
A2
A3
A4
A5
tKHQZ
Q(A2)
D(A1)
Q(A3)
D(A4)
Q(A5)
tKQHZ
NOP
Read
Q(A2)
STALL Read
Q(A3)
Write
D(A4)
STALL
Read
Q(A5)
CONTINUE
DESELECT
Write
D(A1)
DESELECT
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
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Flow Through Mode Read/Write Cycle Timing
4
3
5
6
8
10
7
9
1
2
CK
CKE
E*
tH
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
tKH tKL
tKC
ADV
W
Bn
A7
A0–An
A1
A2
A3
A4
A5
A6
tKQ
tKHQZ
tGLQV
tKQHZ
tKQLZ
D
Q
DQ
D(A2)
Q(A3)
Q(A4)
Q(A6)
D(A1)
D(A5)
(A2+1)
(A4+1)
tOELZ
tKQX
tH
tS
tOEHZ
G
Write
D(A5)
Write
D(A2)
BURST Read
Read
Q(A4) Read
Q(A4+1)
BURST
Read
Q(A6)
DESELECT
Write
D(A1)
Write
D(A7)
COMMAND
Write
Q(A3)
D(A2+1)
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
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Flow Through Mode No-Op, Stall and Deselect Timing
4
3
5
6
8
10
7
9
1
2
CK
tH
tS
tS
tS
CKE
E*
tH
tH
ADV
W
Bn
A1
A2
A3
A4
A5
A0–An
tKHQZ
Q(A2)
D(A1)
Q(A5)
Q(A3)
D(A4)
NOP
DQ
tKQHZ
Read
Q(A2)
STALL Read
Q(A3)
Write
D(A4)
STALL
Read
Q(A5)
DESELECT
CONTINUE
DESELECT
Write
D(A1)
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
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JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface
standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Some
functions have been modified or eliminated because they can slow the RAM. Nevertheless, the RAM supports 1149.1-1990 TAP
(Test Access Port) Controller architecture, and can be expected to function in a manner that does not conflict with the operation of
Standard 1149.1 compliant devices. The JTAG Port interfaces with conventional TTL / CMOS logic level signaling.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits. To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions
Pin
Pin Name I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the
falling edge of TCK.
TCK
Test Clock
In
Test Mode
Select
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state
machine. An undriven TMS input will produce the same result as a logic one input level.
TMS
TDI
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed
between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP
In Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to
Test Data In
the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input
level.
Output that is active depending on the state of the TAP state machine. Output changes in response to the
falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
TDO Test Data Out Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS
as TCK is strobed. Each of the TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and
push serial data out on the next falling edge of TCK. When a register is selected it is placed between the TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAMs JTAG Port to another device in the scan chain with as little delay as possible.
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Boundary Scan Register
Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The
flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. Two TAP
instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1 0
·
· · ·
Boundary Scan Register
n
2 1 0
· · · · · · · · ·
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
ID Code
I/O
Not Used
Configuration
1
1
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
10 9 8 7 6 5 4 3 2 1
0
x36
x18
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0 0 1 1 0 1 1 0 0 1
0 0 1 1 0 1 1 0 0 1
1
1
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Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1-
compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor
all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This
device will not perform EXTEST, INTEST or the SAMPLE/PRELOAD command.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
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SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring con-
tents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm
the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data cap-
ture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O
ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the
TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-
DR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This
functionality is not Standard 1149.1-compliant.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in
the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, this device is not 1149.1-compliant. Neverthe-
less, this RAM’s TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the instruction regis-
ter the RAM responds just as it does in response to the BYPASS instruction described above.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the
Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 1.00 10/2001
24/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
This RAM does not implement 1149.1 EXTEST function. *Not 1149.1 Compliant *
1
1, 2
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.
SAMPLE-Z
010
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
011
1
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1 Compliant *
100
101
110
111
1
1
1
1
GSI
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol Min. Max. Unit Notes
VIHT
VDD +0.3
Test Port Input High Voltage
1.7
–0.3
–300
–1
V
V
1, 2
1, 2
3
VILT
Test Port Input Low Voltage
0.8
1
IINTH
IINTL
IOLT
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
uA
uA
uA
V
1
4
–1
1
5
VOHT
VOLT
2.4
—
—
0.4
6, 7
6, 8
V
Notes:
1. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
2. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20%
tTKC.
3. VDD ³ VIN ³ VIL
4. 0 V £ VIN £ VIL
5. Output Disable, VOUT = 0 to VDD
6. The TDO output driver is served by the VDD supply.
7. IOH = –4 mA
8. IOL = +4 mA
Rev: 1.00 10/2001
25/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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JTAG Port AC Test Conditions
Parameter
Input high level
Conditions
2.3 V
JTAG Port AC Test Load
DQ
Input low level
0.2 V
30pF*
Input slew rate
1 V/ns
50W
Input reference level
Output reference level
1.25 V
VT = 1.25 V
1.25 V
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
JTAG Port Timing Diagram
tTKL
tTKH
tTKC
TCK
tTS tTH
TMS
TDI
TDO
tTKQ
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
20
—
10
10
5
Max
Unit
ns
TCK Cycle Time
—
10
—
—
—
—
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
ns
ns
ns
ns
tTH
5
ns
Rev: 1.00 10/2001
26/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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Output Driver Characteristics
120.0
100.0
Pull Down Drivers
80.0
60.0
40.0
VDDQ
20.0
IOut
0.0
VOut
VS S
-20.0
-40.0
-60.0
-80.0
-100.0
-120.0
-140.0
Pull Up Drivers
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD HD
3.3V PD HD
3.1V PD HD
3.1V PU HD
3.3V PU HD
3.6V PU HD
BPR 1999.05.18
Rev: 1.00 10/2001
27/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Product Preview
GS841Z18/36AT-200/180/166/150/100
TQFP Package Drawing
q
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
—
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
—
0.10
7°
q
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
BPR 1999.05.18
Rev: 1.00 10/2001
28/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Product Preview
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Ordering Information—GSI NBT Synchronous SRAM
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
GS841Z18AT-200
GS841Z18AT-180
GS841Z18AT-166
GS841Z18AT-150
GS841Z18AT-100
GS841Z36AT-200
GS841Z36AT-180
GS841Z36AT-166
GS841Z36AT-150
GS841Z36AT-100
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
200/7.5
180/8
C
C
C
C
C
C
C
C
C
C
I
166/8.5
150/10
100/12
200/7.5
180/8
166/8.5
150/10
100/12
200/7.5
180/8
256K x 18 GS841Z18AT-2001I
256K x 18
256K x 18
256K x 18
256K x 18
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
Notes:
GS841Z18AT-180I
GS841Z18AT-166I
GS841Z18AT-150I
GS841Z18AT-100I
GS841Z36AT-200I
GS841Z36AT-180I
GS841Z36AT-166I
GS841Z36AT-150I
GS841Z36AT-100I
I
166/8.5
150/10
100/12
200/7.5
180/8
I
I
I
I
I
166/8.5
150/10
100/12
I
I
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8Z36A-100IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some
of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.00 10/2001
29/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Product Preview
GS841Z18/36AT-200/180/166/150/100
4Mb Synchronous NBT Datasheet Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Page /Revisions/Reason
New
• Creation of new datasheet
841Z18A_r1
Rev: 1.00 10/2001
30/30
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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