GS842Z36AGB-200T [GSI]
ZBT SRAM, 128KX36, 7.5ns, CMOS, PBGA119, BGA-119;
| 型号： | GS842Z36AGB-200T |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | ZBT SRAM, 128KX36, 7.5ns, CMOS, PBGA119, BGA-119 静态存储器 |
| 文件： | 总33页 (文件大小：745K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS842Z18/36AB-200/180/166/150/100
119-Bump BGA
Commercial Temp
Industrial Temp
200 MHz–100 MHz
4Mb Pipelined and Flow Through
3.3 V V
DD
Synchronous NBT SRAMs
2.5 V and 3.3 V V
DDQ
Features
Functional Description
The GS842Z18/36AB is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
• 256K x 18 and 128K x 36 configurations
• User configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• Pin-compatible with 2M, 8M, and 16M devices
• 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered address, data, and control
• ZZ Pin for automatic power-down
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
• JEDEC-standard 119-bump BGA package
–200
–180
–166
–150
–100
tCycle 5.0 ns 5.5 ns 6.0 ns 6.6 ns
10 ns
4.5 ns
Pipeline
3-1-1-1
The GS842Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
tKQ
IDD
3.0 ns 3.2 ns 3.5 ns 3.8 ns
370 mA 335 mA 310 mA 280 mA 190 mA
Flow
tKQ
7.5 ns
8 ns
8.5 ns
10 ns
12 ns
12 ns
15 ns
Through tCycle 8.8 ns 9.1 ns 10 ns
2-1-1-1
IDD
220 mA 210 mA 190 mA 165 mA 135 mA
The GS842Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump BGA package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
A
R
B
C
R
D
E
R
F
Read/Write
W
W
W
Flow Through
Data I/O
Q
D
Q
D
Q
E
A
B
C
D
Pipelined
Data I/O
Q
D
Q
D
Q
E
A
B
C
D
Rev: 1.01 3/2002
1/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS842Z18/36AB-200/180/166/150/100
GS842Z18A Pad Out
119 Bump BGA—Top View
1
2
3
4
5
6
7
A
B
C
D
E
F
VDDQ
NC
A6
A7
NC
ADV
VDD
ZQ
E1
A8
A9
VDDQ
NC
E2
A4
A15
A14
VSS
VSS
VSS
NC
VSS
NC
VSS
BA
E3
NC
A5
A3
A16
NC
DQB1
NC
NC
VSS
VSS
VSS
BB
DQA9
NC
NC
DQB2
NC
DQA8
VDDQ
DQA6
NC
VDDQ
NC
G
DQA7
NC
G
H
J
DQB3
NC
VDD
DQB5
NC
NC
W
DQB4
VDDQ
NC
VSS
NC
VSS
NC
VSS
VSS
VSS
LBO
A11
TDI
DQA5
VDD
NC
VDD
CK
NC
CKE
A1
VDDQ
DQA4
NC
K
L
DQB6
VDDQ
DQB8
NC
DQA3
NC
M
N
P
R
T
DQB7
NC
VSS
VSS
VSS
FT
VDDQ
NC
DQA2
NC
DQB9
A2
A0
DQA1
NC
NC
VDD
NC
TCK
A13
NC
A10
A12
TDO
A17
ZZ
U
VDDQ
TMS
NC
VDDQ
Rev: 1.01 3/2002
2/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
GS842Z36A Pad Out
119 Bump BGA—Top View
1
2
3
4
5
6
7
A
B
C
D
E
F
VDDQ
NC
A6
A7
NC
ADV
VDD
ZQ
E1
A8
A9
VDDQ
NC
E2
A4
A15
A14
VSS
VSS
VSS
BB
E3
NC
A5
A3
A16
NC
DQC4
DQC3
VDDQ
DQC2
DQC1
VDDQ
DQD1
DQD2
VDDQ
DQD3
DQD4
NC
DQC9
DQC8
DQC7
DQC6
DQC5
VDD
VSS
VSS
VSS
BC
DQB9
DQB8
DQB7
DQB6
DQB5
VDD
DQB4
DQB3
VDDQ
DQB2
DQB1
VDDQ
DQA1
DQA2
VDDQ
DQA3
DQA4
NC
G
G
H
J
NC
W
VSS
NC
VSS
BD
VSS
NC
VSS
BA
VDD
CK
NC
CKE
A1
K
L
DQD5
DQD6
DQD7
DQD8
DQD9
A2
DQA5
DQA6
DQA7
DQA8
DQA9
A13
M
N
P
R
T
VSS
VSS
VSS
LBO
A10
TDI
VSS
VSS
VSS
FT
A0
VDD
A11
TCK
NC
NC
A12
TDO
NC
ZZ
U
VDDQ
TMS
NC
VDDQ
Rev: 1.01 3/2002
3/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
GS842Z18/36A Pin Description
Pin Location
Symbol
Type
Description
P4, N4
A0, A1
I
Address field LSBs and Address Counter Preset Inputs
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, R2, R6, T3, T5
An
I
Address Inputs
T4
An
NC
An
I
—
I
Address Inputs (x36 Version)
No Connect (x36 Version)
Address Inputs (x18 Version)
A4, T2, T6
T2, T6
K7, L7, N7, P7, K6, L6, M6, N6, P6 DQA1–DQA9
H7, G7, E7, D7, H6, G6, F6, E6, D6 DQB1–DQB9
H1, G1, E1, D1, H2, G2, F2, E2, D2 DQC1–DQC9
K1, L1, N1, P1, K2, L2, M2, N2, P2 DQD1–DQD9
I/O
Data Input and Output pins (x36 Version)
L5, G5, G3, L3
BA, BB, BC, BD
I
I/O
I
Byte Write Enable for DQA, DQB, DQC, DQA I/Os; active low ( x36 Version)
Data Input and Output pin (x18 Version)
P7, N6, L6, K7, H6, G7, F6, E7, D6 DQA1–DQA9
D1, E2, G2, H1, K2, L1, M2, N1, P2 DQB1–DQB9
L5, G3
BA, BB
Byte Write Enable for DQA, DQB Data I/Os; active low ( x18 Version)
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,
G5, L3, T4, A4
NC
—
No Connect (x18 Version)
K4
M4
H4
CK
CKE
W
I
I
I
I
I
I
I
I
I
I
Clock Input Signal; active high
Clock Input Buffer Enable; active low
Write Enable. Writes all enabled bytes; active low
Chip Enable; active low
E4, B6
B2
E1, E3
E2
Chip Enable; active high
F4
G
Output Enable; active low
B4
ADV
ZZ
Burst address counter advance enable; active high
Sleep Mode control; active high
T7
R5
FT
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
R3
LBO
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
D4
ZQ
I
B1, C1, R1, T1, L4, B7, C7, U6, J3,
J5, G4, R7
NC
—
No Connect
U2
TMS
I
Scan Test Mode Select
Rev: 1.01 3/2002
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© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
GS842Z18/36A Pin Description
Pin Location
Symbol
Type
Description
Scan Test Data In
Scan Test Data Out
Scan Test Clock
U3
TDI
TDO
TCK
VDD
I
O
I
U5
U4
J2, C4, J4, R4, J6
I
Core power supply
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
VSS
I
I/O and Core Ground
A1, F1, J1, M1, U1, A7, F7,
J7, M7, U7
VDDQ
CK
I
I
Output driver power supply
K4
Clock Input Signal; active high
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipelined Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
W
H
L
BA
X
BB
X
BC
X
BD
X
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle
Rev: 1.01 3/2002
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© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.
Flow through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving
the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a
double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode,
address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising
edge of clock.
Rev: 1.01 3/2002
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© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
Synchronous Truth Table
Operation
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Continue
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
Write Abort, Continue Burst
Clock Edge Ignore, Stall
Sleep Mode
Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes
D
D
D
D
R
B
None
None
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
None
X
H
X
H
X
H
X
H
X
X
X
H
L
1
External
Next
L-H
L-H
Q
Q
X
L
X
L
H
L
L
1,10
2
R
B
External
Next
H
H
X
X
X
X
X
X
L-H High-Z
X
L
X
L
H
L
L-H High-Z 1,2,10
W
B
External
Next
L-H
L-H
D
D
3
X
L
X
L
H
L
X
L
L
1,3,10
2,3
W
B
None
H
H
X
X
L-H High-Z
Next
X
X
X
X
X
X
H
X
X
X
X
X
L-H High-Z 1,2,3,10
Current
None
L-H
X
-
4
High-Z
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect
cycle is executed first
2. Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A write abort occurs when the W pin is
sampled low, but no byte write pins are active, so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write
cycles.
4. If CKE high occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE high occurs during a write cycle, the bus will
remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are low
6. All inputs, except G and ZZ, must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.01 3/2002
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© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
Pipelined and Flow Through Read-Write Control State Diagram
D
B
Deselect
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
W
R
Burst Read
Burst Write
B
B
D
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram
Rev: 1.01 3/2002
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© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
R
B
W
B
Intermediate
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
Intermediate
D
Intermediate
W
R
High Z
B
D
Intermediate
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+2)
Intermediate State (N+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Intermediate
State
Current State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.01 3/2002
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© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
Flow Through Mode Data I/O State Diagram
R
B
W
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
D
W
R
High Z
B
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
Current State
Next State
Current State and Next State Definition for: Pipelined and Flow Through Read Write Control State Diagram
Rev: 1.01 3/2002
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© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
Read to Write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, interleaved burst sequence is selected. See the tables
below for details.
FLXDrive™
The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
L
H or NC
L
Burst Order Control
LBO
Output Register Control
Power Down Control
FT
ZZ
ZQ
H or NC
L or NC
H
Active
Standby, IDD = ISB
L
High Drive (Low Impedance)
Low Drive (High Impedance)
FLXDrive Output Impedance Control
H or NC
Note:
There is a are pull-up devices on the LBO, ZQ, and FT pins and a pull down device on the PE and ZZ pins, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.01 3/2002
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© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep Mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
CK
tZZR
ZZ
Sleep
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Bump R5. Not all vendors offer this option, however, most mark Bump R5 as VDD or VDDQ on pipelined parts and VSS
on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.
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Preliminary
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Absolute Maximum Ratings
(All voltages reference to VSS
)
Symbol
VDD
Description
Value
Unit
Voltage on VDD Pins
–0.5 to 4.6
–0.5 to VDD
V
V
V
VDDQ
VCK
Voltage in VDDQ Pins
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 6
VI/O
–0.5 to VDDQ +0.5 (£ 4.6 V max.)
V
V
VIN
–0.5 to VDD +0.5 (£ 4.6 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
IIN
+/–20
+/–20
mA
mA
W
IOUT
PD
1.5
oC
oC
TSTG
–55 to 125
–55 to 125
TBIAS
Temperature Under Bias
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended
period of time, may affect reliability of this component.
Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
VDD
VDDQ
VIH
Min.
3.135
2.375
1.7
Typ.
3.3
2.5
—
Max.
3.6
Unit
V
Notes
VDD
I/O Supply Voltage
V
1
2
2
3
3
VDD +0.3
Input High Voltage
V
VIL
Input Low Voltage
–0.3
0
—
0.8
70
85
V
TA
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
25
°C
°C
TA
–40
25
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V £ VDDQ £ 2.375 V
(i.e., 2.5 V I/O) and 3.6 V £ VDDQ £ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
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Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 2.0 V
VSS
50%
VDD
50%
VSS – 2.0 V
20% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Input Capacitance
Symbol
Test conditions
VIN = 0 V
Typ.
Max.
Unit
pF
CIN
4
6
5
7
CI/O
VOUT = 0 V
Input/Output Capacitance
pF
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
RQJA
Max
40
Unit
Notes
1,2
single
four
—
°C/W
°C/W
°C/W
RQJA
24
1,2
RQJC
9
3
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient.
Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
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AC Test Conditions
Parameter
Input high level
Input low level
Conditions
2.3 V
0.2 V
Input slew rate
1 V/ns
Input reference level
Output reference level
Output load
1.25 V
1.25 V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225W
225W
DQ
30pF*
50W
5pF*
VT = 1.25 V
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
VDD ³ VIN ³ VIH
0 V £ VIN £ VIH
–1 uA
–1 uA
1 uA
300 uA
IINZZ
IINM
IOL
ZZ Input Current
VDD ³ VIN ³ VIL
0 V £ VIN £ VIL
–300 uA
–1 uA
1 uA
1 uA
Mode Pin Input Current
Output Leakage Current
Output Disable,
VOUT = 0 to VDD
–1 uA
1 uA
VOH
VOH
VOL
IOH = –8 mA, VDDQ = 2.375 V
IOH = –8 mA, VDDQ = 3.135 V
IOL = 8 mA
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
—
—
—
0.4 V
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
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Operating Currents
-200
-180
-166
-150
-100
Test
Conditions
Parameter
Symbol
Unit
0 to –40to 0 to –40to 0 to –40to 0 to –40to 0 to –40to
70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C
IDD
Pipeline
Device Selected;
All other inputs
³ VIH or £ VIL
370
220
20
380
230
30
335
210
20
345
220
30
310
190
20
320
200
30
280
165
20
290
175
30
190
135
20
200
145
30
mA
mA
mA
mA
mA
mA
Operating
Current
IDD
Flow-Thru
Output open
ISB
Pipeline
ZZ ³ VDD –
Standby
Current
0.2 V
ISB
Flow-Thru
20
30
20
30
20
30
20
30
20
30
IDD
Pipeline
Device
Deselected;
All other inputs
³ VIH or £ VIL
60
70
55
65
50
60
50
60
40
50
Deselect
Current
IDD
Flow-Thru
45
55
40
50
40
50
35
45
35
45
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Preliminary
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AC Electrical Characteristics
-200
-180
-166
-150
-100
Parameter
Symbol
Unit
Min
5.0
—
Max
—
Min
5.5
—
Max
—
Min
6.0
—
Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock Cycle Time
tKC
tKQ
—
3.5
—
6.7
—
—
3.8
—
10
—
—
4.5
—
—
—
12.0
—
—
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.0
—
3.2
—
Pipeline
tKQX
1.5
1.5
8.8
—
1.5
1.5
9.1
—
1.5
1.5
10.0
—
1.5
1.5
12.0
—
1.5
1.5
15.0
—
tLZ1
tKC
—
—
—
—
—
—
—
—
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKQ
7.5
—
8.0
—
8.5
—
10.0
—
Flow
Through
tKQX
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
1.5
—
tLZ1
tKH
tKL
—
—
—
—
—
—
—
—
Clock LOW Time
—
—
—
—
tHZ1
tOE
Clock to Output in High-Z
G to Output Valid
3.0
3.0
—
3.2
3.2
—
3.5
3.5
—
3.8
3.8
—
5
tOLZ1
G to output in Low-Z
0
0
0
0
0
—
tOHZ1
tS
G to output in High-Z
Setup time
—
1.5
0.5
5
3.0
—
—
—
—
1.5
0.5
5
3.2
—
—
—
—
1.5
0.5
5
3.5
—
—
—
—
1.5
0.5
5
3.8
—
—
—
—
2.0
0.5
5
5
ns
ns
ns
ns
—
—
—
Hold time
tH
tZZS2
ZZ setup time
tZZH2
tZZR
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
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Pipeline Mode Read/Write Cycle Timing
1
2
3
4
5
6
7
8
9
10
CK
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
tKH tKL tKC
CKE
E*
ADV
W
Bn
tH
A1
A2
A3
A4
A5
A6
A7
A0–An
tKQ
tHZ
tOE
tKQX
tLZ
D
Q
(A4+1)
DQA–DQD
D(A2)
Q(A3)
Q(A4)
Q(A6)
D(A1)
D(A5)
(A2+1)
tKQX
tH
tS
tOHZ
tOLZ
G
Write
D(A5)
Write
D(A2) Write
D(A2+1)
BURST Read
Q(A3)
Read
Q(A4) Read
Q(A4+1)
BURST
Read
Q(A6)
DESELECT
Write
D(A1)
Write
D(A7)
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
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© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
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Pipeline Mode No-Op, Stall and Deselect Timing
2
8
4
3
5
6
10
7
9
1
CK
tH
tH
tH
tS
tS
tS
CKE
E*
ADV
tS
tH
W
Bn
A0–An
DQ
A1
A2
A3
A4
A5
tHZ
Q(A2)
D(A1)
Q(A3)
D(A4)
Q(A5)
tKQX
NOP
Read
Q(A2)
STALL Read
Q(A3)
Write
D(A4)
STALL
Read
Q(A5)
CONTINUE
DESELECT
Write
D(A1)
DESELECT
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
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Flow Through Mode Read/Write Cycle Timing
4
3
5
6
8
10
7
9
1
2
CK
CKE
E*
tH
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
tKH tKL
tKC
ADV
W
Bn
A7
A0–An
A1
A2
A3
A4
A5
A6
tKQ
tHZ
tOE
tKQX
tLZ
D
Q
(A4+1)
DQ
D(A2)
Q(A3)
Q(A4)
Q(A6)
D(A1)
D(A5)
(A2+1)
tKQX
tOHZ
tH
tS
tOLZ
G
Write
D(A5)
Write
D(A2)
BURST Read
Read
Q(A4) Read
Q(A4+1)
BURST
Read
Q(A6)
DESELECT
Write
D(A1)
Write
D(A7)
COMMAND
Write
Q(A3)
D(A2+1)
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
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Preliminary
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Flow Through Mode No-Op, Stall and Deselect Timing
4
3
5
6
8
10
7
9
1
2
CK
tH
tS
tS
tS
CKE
E*
tH
tH
ADV
W
Bn
A1
A2
A3
A4
A5
A0–An
tHZ
Q(A2)
D(A1)
Q(A5)
Q(A3)
D(A4)
NOP
DQ
tKQX
Read
Q(A2)
STALL Read
Q(A3)
Write
D(A4)
STALL
Read
Q(A5)
DESELECT
CONTINUE
DESELECT
Write
D(A1)
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
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Preliminary
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JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard
(commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ
.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI,
and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may
be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied
to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and
pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various
data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The
Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset
state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s
JTAG Port to another device in the scan chain with as little delay as possible.
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Preliminary
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Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are
then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also
includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan
Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the
contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is
moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1 0
·
· · ·
Boundary Scan Register
n
2 1 0
· · · · · · · · ·
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with
the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the
RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the
register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
ID Code
I/O
Not Used
Configuration
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
1
1
x36
x18
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
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Preliminary
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Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private)
instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed
ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the
RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the
controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially
loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded
instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
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Preliminary
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SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s.
The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input
pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-
ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the
value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the
Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 1.01 3/2002
25/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
1
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.
SAMPLE-Z
RFU
010
011
1
1
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
SAMPLE/PRELOAD
GSI
100
101
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
GSI private instruction.
1
1
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
110
111
1
1
BYPASS
Notes:
Places Bypass Register between TDI and TDO.
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.01 3/2002
26/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
VIHJ3
VILJ3
Min.
Max.
VDD3 +0.3
0.8
Unit Notes
2.0
3.3 V Test Port Input High Voltage
3.3 V Test Port Input Low Voltage
2.5 V Test Port Input High Voltage
2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
V
V
1
1
–0.3
VIHJ2
VILJ2
0.6 * VDD2
VDD2 +0.3
0.3 * VDD2
V
1
–0.3
V
1
IINHJ
–300
1
100
1
uA
uA
uA
V
2
IINLJ
–1
3
IOLJ
–1
4
VOHJ
VOLJ
Test Port Output High Voltage
Test Port Output Low Voltage
1.7
—
—
5, 6
5, 7
5, 8
5, 9
0.4
V
VOHJC
VOLJC
VDDQ – 100 mV
Test Port Output CMOS High
—
V
Test Port Output CMOS Low
—
100 mV
V
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. ILJ £ VIN £ VDDn
V
3. 0 V £ VIN £ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOHJC = +100 uA
Rev: 1.01 3/2002
27/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
JTAG Port AC Test Conditions
Parameter
Input high level
Conditions
2.3 V
JTAG Port AC Test Load
DQ
Input low level
0.2 V
30pF*
50W
Input slew rate
1 V/ns
VT = 1.25 V
Input reference level
Output reference level
1.25 V
* Distributed Test Jig Capacitance
1.25 V
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
JTAG Port Timing Diagram
tTKL
tTS
tTKH
tTKC
TCK
tTH
TMS
TDI
TDO
tTKQ
Rev: 1.01 3/2002
28/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
50
—
Max
—
Unit
ns
TCK Cycle Time
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
ns
20
20
10
10
ns
—
ns
—
ns
tTH
—
ns
GS842Z18/36A Boundary Scan Chain Order
Bump
Order
x36
x18
x36
x18
1(TBD)
Rev: 1.01 3/2002
29/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
Output Driver Characteristics
TBD
Rev: 1.01 3/2002
30/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
Package Dimensions—119-Bump BGA
Pin 1
Corner
A
7 6 5 4 3 2
1
A
B
C
D
E
F
G
H
J
G
D
B
P
S
K
L
M
N
P
R
T
U
R
N
Bottom View
Top View
Package Dimensions—119-Pin BGA
Symbol
Description
Width
Min. Nom. Max
A
13.8
21.8
-
14.0
22.0
14.2
22.2
2.40
0.90
0.70
1.70
B
Length
C
Package Height (including ball)
Ball Size
D
0.60
0.50
0.75
0.60
E
Ball Height
F
Package Height (excluding balls)
Width between Balls
Package Height above board
Cut-out Package Width
Foot Length
1.46
G
1.27
K
0.80
0.90
1.00
N
12.00
19.50
7.62
P
R
Width of package between balls
Length of package between balls
Variance of Ball Height
S
T
20.32
0.15
Side View
Unit: mm
BPR 1999.05.18
Rev: 1.01 3/2002
31/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
Ordering Information—GSI NBT Synchronous SRAM
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
GS842Z18AB-200
GS842Z18AB-180
GS842Z18AB-166
GS842Z18AB-150
GS842Z18AB-100
GS842Z36AB-200
GS842Z36AB-180
GS842Z36AB-166
GS842Z36AB-150
GS842Z36AB-100
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
200/7.5
180/8
C
C
C
C
C
C
C
C
C
C
I
166/8.5
150/10
100/12
200/7.5
180/8
166/8.5
150/10
100/12
200/7.5
180/8
256K x 18 GS842Z18AB-2001I
256K x 18
256K x 18
256K x 18
256K x 18
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
Notes:
GS842Z18AB-180I
GS842Z18AB-166I
GS842Z18AB-150I
GS842Z18AB-100I
GS842Z36AB-200I
GS842Z36AB-180I
GS842Z36AB-166I
GS842Z36AB-150I
GS842Z36AB-100I
I
166/8.5
150/10
100/12
200/7.5
180/8
I
I
I
I
I
166/8.5
150/10
100/12
I
I
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS842Z36AB-100IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some
of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.01 3/2002
32/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
4Mb Synchronous NBT Datasheet Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Page /Revisions/Reason
New
• Creation of new datasheet
842Z18A_r1
• Updated power numbers in table on page 1 and Operating
Currents table
• Updated pinout for x18
• Updated Pin Description table
• Removed ByteSafe references
• Changed DP and QE to NC
842Z18A_r1;
842Z18A_r1_01
Content
• Delete PE from entire document (changed to NC)
Rev: 1.01 3/2002
33/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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