GS8641ZV18GE-200_技术文档

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GS8641ZV18/32/36E-300/250/200/167

300 MHz–167 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb Pipelined and Flow Through

Synchronous NBT SRAM

1.8 V V

DD

1.8 V I/O

Because it is a synchronous device, address, data inputs, and

Features

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable, ZZ and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

• User-configurable Pipeline and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization

• Fully pin-compatible with both pipelined and flow through

NtRAM™, NoBL™ and ZBT™ SRAMs

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V +10%/–10% core power supply

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with4Mb, 9Mb, 18Mb, and 36Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ pin for automatic power-down

• JEDEC-standard 165-bump FP-BGA package

The GS8641ZV18/32/36E may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising-edge-triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

Functional Description

The GS8641ZV18/32/36E is a 72Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

The GS8641ZV18/32/36E is implemented with GSI's high

performance CMOS technology and is available in JEDEC-

standard 165-bump FP-BGA package.

Parameter Synopsis

-300

-250

-200

-167

Unit

t

2.3

3.3

2.5

4.0

3.0

5.0

3.5

6.0

ns

KQ

Pipeline

3-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

400

480

340

410

290

350

260

305

mA

t

5.5

6.5

7.5

8.0

ns

KQ

Flow

Through

2-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

285

330

245

280

220

250

210

240

mA

Rev: 1.00 9/2004

1/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS8641ZV18/32/36E-300/250/200/167

165 Bump BGA—x18 Commom I/O—Top View (Package E)

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

NC

A

E1

BB

NC

E3

CKE

ADV

A

B

C

D

E

F

NC

A

NC

E2

NC

BA

CK

W

G

A

NC

DQA

NC

A

NC

DQA

ZZ

V

DDQ

SS

DD

SS

DD

DDQ

NC

DQB

MCH

NC

V

NC

G

H

J

NC

G

H

J

FT

NC

DQB

NC

V

NC

DDQ

K

L

NC

V

NC

K

L

NC

M

N

P

R

NC

M

N

P

R

NC

V

NC

TDI

NC

A1

A0

NC

V

NC

DDQ

SS

DDQ

A

TDO

TCK

A

NC

LBO

A

TMS

A

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

Rev: 1.00 9/2004

2/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS8641ZV18/32/36E-300/250/200/167

165 Bump BGA—x32 Common I/O—Top View (Package E)

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

NC

A

E1

BC

BB

E3

CKE

ADV

A

NC

A

B

C

D

E

F

NC

A

E2

BD

BA

CK

W

G

A

NC

V

NC

DDQ

SS

DD

SS

DD

DDQ

DQC

FT

DQC

MCH

DQD

NC

V

DQB

NC

DQB

ZZ

G

H

J

G

H

J

NC

DQD

NC

V

DQA

NC

DQA

NC

DDQ

K

L

V

K

L

M

N

P

R

M

N

P

R

V

NC

TDI

NC

A1

A0

NC

V

SS

DDQ

SS

DDQ

NC

A

TDO

TCK

A

NC

LBO

A

TMS

A

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

Rev: 1.00 9/2004

3/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS8641ZV18/32/36E-300/250/200/167

165 Bump BGA—x36 Common I/O—Top View (Package E)

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

NC

A

E1

BC

BB

E3

CKE

ADV

A

NC

A

B

C

D

E

F

NC

A

E2

BD

BA

CK

W

G

A

NC

DQB

ZZ

DQC

FT

NC

V

NC

DDQ

SS

DD

SS

DD

DDQ

DQC

MCH

DQD

NC

V

DQB

NC

G

H

J

G

H

J

NC

DQD

NC

V

DQA

NC

DQA

NC

DDQ

K

L

V

K

L

M

N

P

R

M

N

P

R

V

NC

TDI

NC

A1

A0

NC

V

SS

DDQ

SS

DDQ

A

TDO

TCK

A

LBO

A

TMS

A

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

Rev: 1.00 9/2004

4/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS8641ZV18/32/36E-300/250/200/167

GS8641ZV18/32/36E 165-Bump BGA Pin Description

Symbol

A0, A1

An

Type

Description

I

Address field LSBs and Address Counter Preset Inputs

Address Inputs

DQ^A

DQB

DQC

DQD

I/O

Data Input and Output pins

B^A, BB, BC, BD

I

—

I

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

No Connect

NC

CK

Clock Input Signal; active high

Clock Enable; active low

CKE

W

I

Write Enable; active low

E¹

I

Chip Enable; active low

E³

I

Chip Enable; active low

E²

I

Chip Enable; active high

FT

I

Flow Through / Pipeline Mode Control

Output Enable; active low

Burst address counter advance enable; active high

Sleep mode control; active high

Linear Burst Order mode; active low

Scan Test Mode Select

G

I

ADV

ZZ

I

LBO

TMS

TDI

TDO

TCK

MCH

I

Scan Test Data In

O

I

Scan Test Data Out

Scan Test Clock

—

I

Must Connect High

V

Core power supply

DD

V

I

I/O and Core Ground

SS

V

Output driver power supply

DDQ

Rev: 1.00 9/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS8641ZV18/32/36E-300/250/200/167

GS8641ZV18/32/36 NBT SRAM Functional Block Diagram

s

n s e e S A m p

i t r e W D r i v e r

s

Rev: 1.00 9/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to

suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle

read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device

activation is accomplished by asserting all three of the Chip Enable inputs (E¹, E2 and E3). Deassertion of any one of the Enable

inputs will deactivate the device.

Function

Read

W

H

L

BA

X

BB

X

BC

X

BD

X

Write Byte “a”

Write Byte “b”

Write Byte “c”

Write Byte “d”

Write all Bytes

Write Abort/NOP

L

H

L

H

L

H

L

H

L

H

L

H

L

H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three

chip enables (E¹, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address

presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control

logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At

the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The

Byte Write Enable inputs (B^A, BB, BC & BD) determine which bytes will be written. All or none may be activated. A write cycle

with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the

write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising

edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the

third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use

of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new

address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow

Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability

to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late

write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address

and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of

clock.

Rev: 1.00 9/2004

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Synchronous Truth Table

Operation

Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes

Read Cycle, Begin Burst

Read Cycle, Continue Burst

NOP/Read, Begin Burst

R

B

R

B

W

B

D

External

L-H

L

H

L

H

X

H

X

L

X

L

X

L

H

X

H

X

H

X

L

X

L

Q

1,10

2

External

H

X

High-Z

Dummy Read, Continue Burst

Write Cycle, Begin Burst

H

L

X

L

X

L

High-Z 1,2,10

External

D

3

Write Cycle, Continue Burst

Write Abort, Continue Burst

Deselect Cycle, Power Down

H

L

X

L

X

H

X

H

X

1,3,10

X

High-Z 1,2,3,10

High-Z

None

L

High-Z

None

L

High-Z

1

Deselect Cycle

D

None

L-H

L

H

L

H

L

X

L

High-Z

Deselect Cycle, Continue

Sleep Mode

None

L-H

X

L

X

H

X

L

H

L

High-Z

-

1

4

Clock Edge Ignore, Stall

Current

L-H

Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-

lect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W

pin is sampled low but no Byte Write pins are active so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during

write cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus

will remain in High Z.

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write

signals are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

Rev: 1.00 9/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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Pipelined and Flow Through Read Write Control State Diagram

D

B

Deselect

R

D

W

New Read

New Write

R

W

B

R

W

R

Burst Read

Burst Write

B

D

Key

Notes:

Input Command Code

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

ƒ

Transition

2. W, R, B, and D represent input command

codes as indicated in the Synchronous Truth Table.

Current State (n)

Next State (n+1)

n

n+1

n+2

n+3

Clock (CK)

Command

ƒ

Current State

Next State

Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram

Rev: 1.00 9/2004

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Pipeline Mode Data I/O State Diagram

Intermediate

R

W

B

Intermediate

B

R

Data Out

(Q Valid)

High Z

(Data In)

W

D

Intermediate

D

Intermediate

W

R

High Z

B

D

Intermediate

Key

Notes:

Input Command Code

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

ƒ

Transition

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Current State (n)

Next State (n+2)

Intermediate State (N+1)

n

n+1

n+2

n+3

Clock (CK)

Command

ƒ

Intermediate

State

Current State

Next State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Rev: 1.00 9/2004

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Flow Through Mode Data I/O State Diagram

R

W

B

R

Data Out

(Q Valid)

High Z

(Data In)

W

D

W

R

High Z

B

D

Key

Notes:

Input Command Code

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

ƒ

Transition

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Current State (n)

Next State (n+1)

n

n+1

n+2

n+3

Clock (CK)

Command

ƒ

Current State

Next State

Current State and Next State Definition for: Pipeline and Flow through Read Write Control State Diagram

Rev: 1.00 9/2004

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Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from

read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address

generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when

driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write

the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into

Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been

accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst

sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables

below for details.

Mode Pin Functions

Mode Name

Pin Name

State

Function

Linear Burst

Interleaved Burst

Flow Through

Pipeline

L

Burst Order Control

LBO

H

L

Output Register Control

Power Down Control

FT

ZZ

H or NC

L or NC

H

Active

Standby, I = I

DD SB

Note:

There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate

in the default states as specified in the above tables.

Burst Counter Sequences

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

1st address

2nd address

3rd address

4th address

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Note:

The burst counter wraps to initial state on the 5th clock.

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Rev: 1.00 9/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of

SB

Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

SB

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKH

tKC

tKL

CK

ZZ

tZZR

tZZS

tZZH

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found

on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V or V

on pipelined parts and V on flow

SS

DD

DDQ

through parts. GSI NBT SRAMs are fully compatible with these sockets.

Rev: 1.00 9/2004

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Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

Description

Value

Unit

V

Voltage on V Pins

–0.5 to 3.6

DD

V

Voltage in V

Pins

DDQ

–0.5 to 3.6

V

DDQ

V

–0.5 to V

+0.5 (≤ 3.6 V max.)

DDQ

Voltage on I/O Pins

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

V

I/O

V

–0.5 to V +0.5 (≤ 3.6 V max.)

V

IN

DD

I

+/–20

mA

W

IN

I

OUT

P

1.5

D

o

T

–55 to 125

C

STG

o

T

Temperature Under Bias

C

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Power Supply Voltage Ranges

Parameter

Symbol

Min.

1.6

Typ.

1.8

Max.

2.0

Unit

V

Notes

V

1.8 V Supply Voltage

DD1

1.8 V V

I/O Supply Voltage

V

1.6

1.8

2.0

V

DDQ

DDQ1

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

Rev: 1.00 9/2004

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Logic Levels

Parameter

Symbol

Min.

Typ.

—

Max.

Unit

Notes

V

Input High Voltage

Input Low Voltage

V

0.6*V

V

+ 0.3

DD

V

1

DD

IH

DD

V

0.3*V

DD

–0.3

—

1

DD

IL

V

I/O Input High Voltage

I/O Input Low Voltage

V

0.6*V

V

+ 0.3

DDQ

—

1,3

DDQ

IHQ

DD

V

0.3*V

DD

–0.3

—

DDQ

ILQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

3.

V

(max) is voltage on V

pins plus 0.3 V.

IHQ

DDQ

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKC

V

+ 2.0 V

50%

DD

V

SS

50%

V

DD

V

– 2.0 V

SS

20% tKC

V

IL

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 2.5 V)

A

DD

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

pF

C

V

= 0 V

Input Capacitance

4

6

5

7

IN

C

V

OUT

= 0 V

Input/Output Capacitance

pF

I/O

Note:

These parameters are sample tested.

Rev: 1.00 9/2004

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AC Test Conditions

Parameter

Conditions

V

– 0.2 V

Input high level

Input low level

DD

0.2 V

1 V/ns

/2

Input slew rate

V

Input reference level

DD

V

/2

Output reference level

Output load

DDQ

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

Output Load 1

DQ

*

50Ω

30pF

V

DDQ/2

* Distributed Test Jig Capacitance

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I

V = 0 to V

IN DD

–1 uA

1 uA

IL

V

≥ V ≥ V

IN

–1 uA

1 uA

100 uA

DD

IH

I

ZZ Input Current

IN1

IN2

0 V ≤ V ≤ V

IN

V

≥ V ≥ V

IN

–100 uA

–1 uA

1 uA

DD

IL

FT, SCD,ZQ Input Current

0 V ≤ V ≤ V

IN

I

Output Disable, V

= 0 to V

= 1.6 V

Output Leakage Current

Output High Voltage

Output Low Voltage

–1 uA

1 uA

—

OL

OUT

DD

V

I

= –4 mA, V

V

– 0.4 V

DDQ

OH1

OH

DDQ

V

I

= 4 mA, V = 1.6 V

OL DD

—

0.4 V

OL1

Rev: 1.00 9/2004

16/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8641ZV18/32/36E-300/250/200/167

Operating Currents

-300

-250

-200

-167

0

to

–40

0

to

–40

0

to

–40

0

to

–40

Parameter

Test Conditions

Mode

Symbol

Unit

to

70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C

I

420

60

440

60

360

50

380

50

310

40

330

40

270

35

290

35

DD

mA

Pipeline

I

DDQ

(x32/

x36)

I

Flow

Through

300

30

320

30

255

25

275

25

230

20

250

20

220

20

240

20

DD

Device Selected;

All other inputs

≥V or ≤ V

DDQ

Operating

Current

IH

IL

I

370

30

390

30

315

25

335

25

270

20

290

20

240

20

260

20

DD

Pipeline

Output open

DDQ

(x18)

I

Flow

Through

270

15

290

15

230

15

250

15

205

15

225

15

195

15

215

15

DD

DDQ

I

Pipeline

100

150

135

120

165

150

100

140

125

120

155

140

100

130

120

146

135

100

125

120

140

135

mA

SB

Standby

Current

ZZ ≥ V – 0.2 V

—

DD

Flow

Through

I

SB

I

Pipeline

Device Deselected;

All other inputs

≥ V or ≤ V

DD

Deselect

Current

Flow

Through

I

DD

IH

IL

Notes:

1.

I

and I

apply to any combination of V and V

operation.

DDQ

DD

DDQ

DD

2. All parameters listed are worst case scenario.

Rev: 1.00 9/2004

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GS8641ZV18/32/36E-300/250/200/167

AC Electrical Characteristics

-300

-250

-200

-167

Parameter

Symbol

Unit

Min

3.3

—

Max

—

2.3

—

5.5

—

Min

4.0

—

Max

—

2.5

—

6.5

—

Min

5.0

—

Max

—

3.0

—

7.5

—

Min

6.0

—

Max

—

3.5

—

8.0

—

Clock Cycle Time

tKC

tKQ

ns

Clock to Output Valid

Clock to Output Invalid

Pipeline

tKQX

1.5

1.1

0.1

5.5

—

3.0

1.5

0.5

1.0

1.2

1.5

1.2

0.2

6.5

—

3.0

1.5

0.5

1.3

1.5

1.4

0.4

7.5

—

3.0

1.5

0.5

1.3

1.5

0.5

8.0

—

3.0

1.5

0.5

1.3

1.5

1

Clock to Output in Low-Z

tLZ

Setup time

Hold time

tS

tH

Clock Cycle Time

Clock to Output Valid

tKC

tKQ

tKQX

Clock to Output Invalid

Clock to Output in Low-Z

Setup time

Flow

Through

1

tLZ

tS

tH

Hold time

Clock HIGH Time

Clock LOW Time

tKH

tKL

Clock to Output in

High-Z

1

1.5

2.3

1.5

2.5

1.5

3.0

1.5

3.0

ns

tHZ

G to Output Valid

G to output in Low-Z

G to output in High-Z

ZZ setup time

tOE

—

0

2.3

—

2.3

—

0

2.5

—

2.5

—

0

3.0

—

3.0

—

0

3.5

—

3.0

—

ns

1

tOLZ

1

—

5

—

5

—

5

—

5

tOHZ

2

tZZS

2

ZZ hold time

1

tZZH

ZZ recovery

tZZR

20

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Rev: 1.00 9/2004

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Pipeline Mode Timing (NBT)

Write A

Write B

Write B+1

tKL

tKH

Read C

tKC

Cont

Read D

Write E

Read F

DESELECT

CK

CKE

tH

tS

E*

ADV

W

Bn

A

B

C

D

E

F

G

A0–An

DQa–DQd

tH

tLZ

tHZ

tS

D(A)

tKQ

tKQX

D(E)

D(B)

D(B+1)

Q(C)

Q(D)

tOLZ

Q(F)

tOHZ

tOE

G

*Note: E=High(False) if E1 = 1 or E2 = 0 or E3 = 1

Rev: 1.00 9/2004

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Flow Through Mode Timing (NBT)

Write A

Write B

Write B+1 Read C

tKL

Cont

Read D

Write E

Read F

Write G

tKH

tKC

CK

CKE

E

tH

tS

ADV

W

Bn

A0–An

A

B

C

D

E

F

G

tKQ

tLZ

tH

tKQ

tLZ

D(B+1)

tKQX

tS

D(A)

tHZ

Q(D)

tKQX

D(G)

DQ

G

D(B)

Q(C)

D(E)

Q(F)

tOLZ

tOE

tOHZ

*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output

DD

drivers are powered by V

.

DDQ

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

DD

SS

Rev: 1.00 9/2004

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JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TCK

Test Clock

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

TMS

TDI

Test Mode Select

Test Data In

In controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in

Out response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

TDO

Test Data Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

Rev: 1.00 9/2004

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JTAG TAP Block Diagram

·

Boundary Scan Register

·

0

Bypass Register

2

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1

0

·

· · ·

Control Signals

Test Access Port (TAP) Controller

TMS

TCK

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

Die

Revision

Code

GSI Technology

JEDEC Vendor

ID Code

I/O

Not Used

Configuration

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

0

1

x36

x32

x18

X

0

1

0

1

0

1

0

0 1 1 0 1 1 0 0 1

Rev: 1.00 9/2004

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Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

1

Run Test Idle

Select DR

Select IR

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This

occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-

tate testing of other devices in the scan path.

Rev: 1.00 9/2004

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SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is

loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and

I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and

are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because

the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will

not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the

TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP

operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then

places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with

all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is

still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.

Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output

drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-

tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-

ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR

state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-

ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

Rev: 1.00 9/2004

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JTAG TAP Instruction Set Summary

Instruction

EXTEST

IDCODE

Code

000

001

Description

Notes

1

1, 2

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z

010

011

TDO.

1

Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

GSI private instruction.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

100

101

110

111

1

GSI

RFU

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Rev: 1.00 9/2004

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Product Preview

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JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

Max.

Unit Notes

V

0.6 * V

V

+0.3

DD

1.8 V Test Port Input High Voltage

1.8 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

V

1

IHJ

DD

V

0.3 * V

1

–0.3

–300

–1

ILJ

DD

I

uA

V

2

INHJ

I

100

1

3

INLJ

I

–1

4

OLJ

V

1.7

—

5, 6

5, 7

5, 8

5, 9

OHJ

V

—

0.4

—

V

OLJ

V

– 100 mV

DDQ

Test Port Output CMOS High

V

OHJC

V

Test Port Output CMOS Low

—

100 mV

V

OLJC

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < V

+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

2.

V

≤ V ≤ V

ILJ

IN

DDn

3. 0 V ≤ V ≤ V

IN

ILJn

4. Output Disable, V

= 0 to V

DDn

OUT

5. The TDO output driver is served by the V

supply.

DDQ

6.

7.

8.

9.

I

= –4 mA

OHJ

= + 4 mA

OLJ

= –100 uA

= +100 uA

OHJC

JTAG Port AC Test Conditions

Parameter

Conditions

JTAG Port AC Test Load

V

– 0.2 V

Input high level

Input low level

DQ

DD

0.2 V

1 V/ns

*

50Ω

Input slew rate

30pF

V

/2

Input reference level

DDQ

V

/2

DDQ

/2

Output reference level

DDQ

* Distributed Test Jig Capacitance

Notes:

1. Include scope and jig capacitance.

2. Test conditions as as shown unless otherwise noted.

Rev: 1.00 9/2004

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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JTAG Port Timing Diagram

tTKC

tTKH

tTKL

TCK

TDI

tTH

tTS

TMS

TDO

tTKQ

tTH

tTS

Parallel SRAM input

JTAG Port AC Electrical Characteristics

Parameter

TCK Cycle Time

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

50

—

Max

—

Unit

ns

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

20

—

20

10

—

tTH

—

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications

Engineering Department at: apps@gsitechnology.com.

Rev: 1.00 9/2004

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Package Dimensions—165-Bump FPBGA (Package E; Variation 2)

A1

1

TOP VIEW

3 4 5 6 7 8 9 10 11

BOTTOM VIEW

M

A1

Ø0.10

C

M

Ø0.25 C AB

Ø0.44~0.64(165x)

2

11 10 9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

I

A

B

C

D

E

F

G

H

J

K

L

M

N

P

K

L

M

N

P

R

A

1.0

10.0

1.0

15±0.05

B

0.20(4x)

SEATING PLANE

C

Rev: 1.00 9/2004

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Ordering Information for GSI Synchronous Burst RAMs

2

Speed

3

1

Org

Type

Package

Status

T

Part Number

A

(MHz/ns)

4M x 18

2M x 32

2M x 36

4M x 18

2M x 32

2M x 36

GS8641ZV18E-300

GS8641ZV18E-250

GS8641ZV18E-200

GS8641ZV18E-167

GS8641ZV32E-300

GS8641ZV32E-250

GS8641ZV32E-200

GS8641ZV32E-167

GS8641ZV36E-300

GS8641ZV36E-250

GS8641ZV36E-200

GS8641ZV36E-167

GS8641ZV18E-300I

GS8641ZV18E-250I

GS8641ZV18E-200I

GS8641ZV18E-167I

GS8641ZV32E-300I

GS8641ZV32E-250I

GS8641ZV32E-200I

GS8641ZV32E-167I

GS8641ZV36E-300I

GS8641ZV36E-250I

GS8641ZV36E-200I

GS8641ZV36E-167I

NBT Pipeline/Flow Through

165 BGA (E, var.2)

300/5.5

250/6.5

200/7.5

167/8

C

I

300/5.5

250/6.5

200/7.5

167/8

300/5.5

250/6.5

200/7.5

167/8

300/5.5

250/6.5

200/7.5

167/8

I

300/5.5

250/6.5

200/7.5

167/8

I

300/5.5

250/6.5

200/7.5

167/8

I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8641ZV18E-167IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.00 9/2004

29/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS8641ZV18/32/36E-300/250/200/167

72Mb Sync SRAM Data Sheet Revision History

DS/DateRev. Code: Old;

Types of Changes

Format or Content

Page;Revisions;Reason

• Creation of new datasheet

New

8641ZVxx_r1

Rev: 1.00 9/2004

30/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS8641ZV18GE-200
厂家：	GSI TECHNOLOGY
描述：	ZBT SRAM, 4MX18, 7.5ns, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, FBGA-165 静态存储器
文件：	总30页 (文件大小：825K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS8641ZV18GE-200 [GSI]

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