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GS864436E-150T [GSI]

Cache SRAM, 2MX36, 7.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165;
GS864436E-150T
型号： GS864436E-150T
厂家： GSI TECHNOLOGY    GSI TECHNOLOGY
描述：

Cache SRAM, 2MX36, 7.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165

静态存储器 内存集成电路
文件： 总33页 (文件大小：1168K)
中文：  中文翻译
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GS864418/36E-250/225/200/166/150/133  
250 MHz–133MHz  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
4M x 18, 2M x 36  
72Mb S/DCD Sync Burst SRAMs  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
Flow Through/Pipeline Reads  
Features  
The function of the Data Output register can be controlled by the user  
via the FT mode . Holding the FT mode pin low places the RAM in  
Flow Through mode, causing output data to bypass the Data Output  
Register. Holding FT high places the RAM in Pipeline mode,  
activating the rising-edge-triggered Data Output Register.  
• FT pin for user-configurable flow through or pipeline operation  
• Single/Dual Cycle Deselect selectable  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• ZQ mode pin for user-selectable high/low output drive  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to SCD x18/x36 Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
SCD and DCD Pipelined Reads  
The GS864418/36E is a SCD (Single Cycle Deselect) and DCD (Dual  
Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs  
pipeline disable commands to the same degree as read commands.  
SCD SRAMs pipeline deselect commands one stage less than read  
commands. SCD RAMs begin turning off their outputs immediately  
after the deselect command has been captured in the input registers.  
DCD RAMs hold the deselect command for one full cycle and then  
begin turning off their outputs just after the second rising edge of  
clock. The user may configure this SRAM for either mode of  
operation using the SCD mode input.  
• Automatic power-down for portable applications  
• JEDEC-standard 165-bump BGA package  
• RoHS-compliant 165-bump BGA package available  
Functional Description  
Applications  
Byte Write and Global Write  
The GS864418/36E is a 75,497,472-bit high performance  
synchronous SRAM with a 2-bit burst address counter. Although of a  
type originally developed for Level 2 Cache applications supporting  
high performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main store to  
networking chip set support.  
Byte write operation is performed by using Byte Write enable (BW)  
input combined with one or more individual byte write signals (Bx).  
In addition, Global Write (GW) is available for writing all bytes at one  
time, regardless of the Byte Write control inputs.  
FLXDrive™  
The ZQ pin allows selection between high drive strength (ZQ low) for  
Controls  
multi-drop bus applications and normal drive strength (ZQ floating or  
high) point-to-point applications. See the Output Driver  
Characteristics chart for details.  
Addresses, data I/Os, chip enable (E1), address burst control inputs  
(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are  
synchronous and are controlled by a positive-edge-triggered clock  
input (CK). Output enable (G) and power down control (ZZ) are  
asynchronous inputs. Burst cycles can be initiated with either ADSP  
or ADSC inputs. In Burst mode, subsequent burst addresses are  
generated internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or interleave order  
with the Linear Burst Order (LBO) input. The Burst function need not  
be used. New addresses can be loaded on every cycle with no  
degradation of chip performance.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion (High) of  
the ZZ signal, or by stopping the clock (CK). Memory data is retained  
during Sleep mode.  
Core and Interface Voltages  
The GS864418/36E operates on a 2.5 V or 3.3 V power supply. All  
input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ  
)
pins are used to decouple output noise from the internal circuits and  
are 3.3 V and 2.5 V compatible.  
Parameter Synopsis  
-250 -225 -200 -166 -150 -133 Unit  
tKQ(x18/x36)  
tCycle  
2.5  
4.0  
2.7  
4.4  
3.0  
5.0  
3.5  
6.0  
3.8  
6.7  
4.0  
7.5  
ns  
ns  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x36)  
385  
450  
360  
415  
335  
385  
305  
345  
295 265  
325 295  
mA  
mA  
tKQ  
6.5  
6.5  
6.5  
6.5  
6.5  
6.5  
7.0  
7.0  
7.5  
7.5  
8.5  
8.5  
ns  
ns  
Flow  
Through  
2-1-1-1  
tCycle  
Curr (x18)  
Curr (x36)  
265  
290  
265  
290  
265  
290  
255  
280  
240 225  
265 245  
mA  
mA  
Rev: 1.07 2/2011  
1/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
165-Bump BGA—x18 Commom I/O—Top View (Package E)  
1
2
3
4
5
6
7
8
9
10  
A
11  
A
A
B
C
D
E
F
NC  
A
E1  
BB  
NC  
E3  
BW  
ADSC  
ADV  
A
B
C
D
E
F
NC  
NC  
A
E2  
NC  
BA  
CK  
GW  
G
ADSP  
A
NC  
NC  
NC  
NC  
NC  
ZQ  
NC  
DQPA  
DQA  
DQA  
DQA  
DQA  
ZZ  
NC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
SS  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
NC  
DQB  
DQB  
DQB  
DQB  
MCL  
NC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC  
NC  
G
H
J
NC  
G
H
J
FT  
NC  
NC  
DQB  
DQB  
DQB  
DQB  
DQPB  
NC  
V
V
DQA  
DQA  
DQA  
DQA  
NC  
A
NC  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
K
L
NC  
V
V
V
V
V
V
V
V
NC  
K
L
NC  
NC  
M
N
P
R
NC  
NC  
M
N
P
R
SCD  
A
V
NC  
TDI  
A
NC  
V
NC  
DDQ  
SS  
SS  
DDQ  
A
A
A
A1  
A0  
TDO  
TCK  
A
A
A
A
LBO  
A
A
TMS  
A
A
A
11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch  
Rev: 1.07 2/2011  
2/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
165-Bump BGA—x36 Common I/O—Top View (Package E)  
1
2
3
4
5
6
7
8
9
10  
A
11  
A
B
C
D
E
F
NC  
A
E1  
BC  
BB  
E3  
BW  
ADSC  
ADV  
NC  
A
B
C
D
E
F
NC  
DQPC  
DQC  
DQC  
DQC  
DQC  
FT  
A
E2  
BD  
BA  
CK  
GW  
G
ADSP  
A
NC  
DQPB  
DQB  
DQB  
DQB  
DQB  
ZZ  
NC  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
SS  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DQC  
DQC  
DQC  
DQC  
MCL  
DQD  
DQD  
DQD  
DQD  
SCD  
A
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQB  
DQB  
DQB  
DQB  
ZQ  
G
H
J
G
H
J
NC  
NC  
DQD  
DQD  
DQD  
DQD  
DQPD  
NC  
V
V
DQA  
DQA  
DQA  
DQA  
NC  
DQA  
DQA  
DQA  
DQA  
DQPA  
A
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
K
L
V
V
V
V
V
V
V
V
K
L
M
N
P
R
M
N
P
R
V
NC  
TDI  
A
NC  
V
SS  
DDQ  
SS  
DDQ  
A
A
A
A1  
A0  
TDO  
TCK  
A
A
A
A
LBO  
A
A
TMS  
A
A
A
11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch  
Rev: 1.07 2/2011  
3/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
GS864418/36E 165-Bump BGA Pin Description  
Symbol  
A0, A1  
A
Type  
Description  
I
I
Address field LSBs and Address Counter Preset Inputs  
Address Inputs  
DQA  
DQB  
DQC  
DQD  
I/O  
Data Input and Output pins  
BA, BB, BC, BD  
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)  
Clock Input Signal; active high  
CK  
BW  
Byte Write—Writes all enabled bytes; active low  
Global Write Enable—Writes all bytes; active low  
Chip Enable; active low  
GW  
E1  
E3  
Chip Enable; active low  
E2  
Chip Enable; active high  
G
ADV  
Output Enable; active low  
Burst address counter advance enable; active l0w  
Address Strobe (Processor, Cache Controller); active low  
Sleep mode control; active high  
ADSC, ADSP  
ZZ  
FT  
Flow Through or Pipeline mode; active low  
Linear Burst Order mode; active low  
LBO  
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low  
Drive])  
ZQ  
I
I
I
Scan Test Mode Select  
Scan Test Data In  
TMS  
TDI  
O
I
Scan Test Data Out  
TDO  
TCK  
MCL  
SCD  
Scan Test Clock  
—
—
I
Must Connect Low  
Single Cycle Deselect/Dual Cyle Deselect Mode Control  
Core power supply  
V
DD  
V
I
I/O and Core Ground  
SS  
V
I
Output driver power supply  
No Connect  
DDQ  
NC  
—
Rev: 1.07 2/2011  
4/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
GS864418/36E Block Diagram  
Register  
A0–An  
D
Q
A0  
A1  
A0  
A1  
D0  
D1  
Q0  
Q1  
Counter  
Load  
A
LBO  
ADV  
Memory  
Array  
CK  
ADSC  
ADSP  
Q
D
Register  
GW  
BW  
BA  
D
Q
36  
36  
Register  
D
Q
BB  
BC  
BD  
4
Register  
D
Q
Register  
D
Q
Register  
36  
D
Q
36  
36  
Register  
D
E1  
Q
Register  
D
Q
FT  
G
36  
SCD  
Power Down  
Control  
DQx1–DQx9  
ZZ  
Note: Only x36 version shown for simplicity.  
Rev: 1.07 2/2011  
5/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Mode Pin Functions  
Mode Name  
Pin Name  
State  
Function  
Linear Burst  
Interleaved Burst  
Flow Through  
Pipeline  
L
Burst Order Control  
LBO  
H
L
H or NC  
L or NC  
H
Output Register Control  
FT  
ZZ  
Active  
Power Down Control  
Standby, I = I  
DD SB  
L
Dual Cycle Deselect  
Single Cycle Deselect  
Single/Dual Cycle Deselect Control  
FLXDrive Output Impedance Control  
SCD  
ZQ  
H or NC  
L
High Drive (Low Impedance)  
Low Drive (High Impedance)  
H or NC  
Note:  
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the  
chip will operate in the default states as specified in the above tables.  
Burst Counter Sequences  
Linear Burst Sequence  
A[1:0] A[1:0] A[1:0] A[1:0]  
Interleaved Burst Sequence  
A[1:0] A[1:0] A[1:0] A[1:0]  
1st address  
2nd address  
3rd address  
4th address  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
1st address  
2nd address  
3rd address  
4th address  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Note:  
The burst counter wraps to initial state on the 5th clock.  
Note:  
The burst counter wraps to initial state on the 5th clock.  
BPR 1999.05.18  
Rev: 1.07 2/2011  
6/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Byte Write Truth Table  
Function  
Read  
GW  
H
BW  
H
L
BA  
X
BB  
X
BC  
X
BD  
X
Notes  
1
Write No Bytes  
Write byte a  
Write byte b  
Write byte c  
Write byte d  
Write all bytes  
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
H
L
2, 3  
H
L
H
H
H
L
2, 3  
H
L
H
H
L
2, 3, 4  
2, 3, 4  
2, 3, 4  
H
L
H
L
H
L
L
Write all bytes  
L
X
X
X
X
X
Notes:  
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.  
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.  
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.  
4. Bytes “C” and “D” are only available on the x32 and x36 versions.  
Rev: 1.07 2/2011  
7/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Synchronous Truth Table  
State  
Diagram  
Key  
Address  
Used  
3
Operation  
E1  
E2  
E3  
ADSP  
ADSC  
ADV  
W
DQ  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Read Cycle, Begin Burst  
Read Cycle, Begin Burst  
Write Cycle, Begin Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
Notes:  
None  
None  
X
X
L
L
L
L
H
L
L
L
X
H
X
H
X
H
X
H
X
L
H
X
H
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
L
L
L
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
X
X
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z  
High-Z  
None  
X
X
L
X
X
L
High-Z  
None  
X
L
High-Z  
None  
X
X
H
H
H
X
X
X
X
X
X
X
X
X
L
High-Z  
External  
External  
External  
Next  
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
R
H
H
H
X
H
X
H
X
H
X
W
CR  
CR  
CW  
CW  
L
H
H
H
H
H
H
H
H
Next  
Next  
Next  
Current  
Current  
Current  
Current  
1. X = Don’t Care, H = High, L = Low  
2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1  
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.  
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown  
as “Q” in the Truth Table above).  
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish  
basic synchronous or synchronous burst operations and may be avoided for simplicity.  
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.  
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.  
Rev: 1.07 2/2011  
8/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Simplified State Diagram  
X
Deselect  
W
R
W
R
X
R
X
First Write  
First Read  
CW  
CR  
CR  
W
R
R
X
Burst Write  
X
Burst Read  
CR  
CW  
CR  
Notes:  
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.  
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and  
that ADSP is tied high and ADSC is tied low.  
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and  
assumes ADSP is tied high and ADV is tied low.  
Rev: 1.07 2/2011  
9/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Simplified State Diagram with G  
X
Deselect  
W
R
W
R
X
W
R
X
First Write  
First Read  
CR  
CW  
CW  
CR  
W
R
R
W
X
Burst Write  
X
Burst Read  
CR  
CW  
CW  
CR  
Notes:  
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.  
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing  
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.  
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet  
Data Input Set Up Time.  
Rev: 1.07 2/2011  
10/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Absolute Maximum Ratings  
(All voltages reference to V  
)
SS  
Symbol  
VDD  
VDDQ  
VI/O  
Description  
Value  
–0.5 to 4.6  
Unit  
V
Voltage on VDD Pins  
Voltage in VDDQ Pins  
–0.5 to 4.6  
V
–0.5 to VDDQ +0.5 (≤ 4.6 V max.)  
–0.5 to VDD +0.5 (≤ 4.6 V max.)  
Voltage on I/O Pins  
Voltage on Other Input Pins  
Input Current on Any Pin  
Output Current on Any I/O Pin  
Package Power Dissipation  
Storage Temperature  
V
VIN  
V
IIN  
+/–20  
+/–20  
mA  
mA  
W
IOUT  
PD  
1.5  
oC  
oC  
TSTG  
–55 to 125  
–55 to 125  
TBIAS  
Temperature Under Bias  
Note:  
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended  
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of  
this component.  
Power Supply Voltage Ranges  
Parameter  
Symbol  
VDD3  
Min.  
3.0  
Typ.  
3.3  
Max.  
3.6  
Unit  
V
3.3 V Supply Voltage  
VDD2  
2.5 V Supply Voltage  
2.3  
2.5  
2.7  
V
3.3 V VDDQ I/O Supply Voltage  
2.5 V VDDQ I/O Supply Voltage  
VDDQ3  
VDDQ2  
3.0  
3.3  
3.6  
V
2.3  
2.5  
2.7  
V
V
Range Logic Levels  
DD3  
Parameter  
Symbol  
VIH  
Min.  
2.0  
Typ.  
—
Max.  
Unit  
V
VDD + 0.3  
Input High Voltage  
Input Low Voltage  
VIL  
–0.3  
—
0.8  
V
Note:  
(max) is voltage on V  
V
pins plus 0.3 V.  
DDQ  
IHQ  
Rev: 1.07 2/2011  
11/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
V
Range Logic Levels  
DD2  
Parameter  
Symbol  
VIH  
Min.  
Typ.  
—
Max.  
Unit  
V
0.6*VDD  
VDD + 0.3  
0.3*VDD  
Input High Voltage  
Input Low Voltage  
VIL  
–0.3  
—
V
Note:  
(max) is voltage on V  
V
pins plus 0.3 V.  
DDQ  
IHQ  
Recommended Operating Temperatures  
Parameter  
Symbol  
Min.  
0
Typ.  
25  
Max.  
70  
Unit  
°C  
TA  
TA  
Ambient Temperature (Commercial Range Versions)  
Ambient Temperature (Industrial Range Versions)*  
–40  
25  
85  
°C  
Note:  
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications  
quoted are evaluated for worst case in the temperature range marked on the device.  
Thermal Impedance  
Test PCB  
Substrate  
θ JA (C°/W)  
Airflow = 0 m/s  
θ JA (C°/W)  
Airflow = 1 m/s  
θ JA (C°/W)  
Airflow = 2 m/s  
θ JB (C°/W)  
θ JC (C°/W)  
Package  
165 BGA  
4-layer  
18.1  
14.5  
13.8  
7.3  
2.3  
Notes:  
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.  
2. Please refer to JEDEC standard JESD51-6.  
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to  
the PCB can result in cooling or heating of the RAM depending on PCB temperature.  
Undershoot Measurement and Timing  
Overshoot Measurement and Timing  
V
IH  
20% tKC  
V
+ 2.0 V  
DD  
V
SS  
50%  
50%  
V
DD  
V
– 2.0 V  
SS  
20% tKC  
V
IL  
Note:  
Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.  
DDn  
Rev: 1.07 2/2011  
12/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Capacitance  
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)  
A
DD  
Parameter  
Symbol  
CIN  
Test conditions  
VIN = 0 V  
Typ.  
Max.  
Unit  
pF  
Input Capacitance  
4
6
5
7
CI/O  
VOUT = 0 V  
Input/Output Capacitance  
pF  
Note:  
These parameters are sample tested.  
AC Test Conditions  
Parameter  
Conditions  
VDD – 0.2 V  
Input high level  
Input low level  
0.2 V  
1 V/ns  
VDD/2  
Input slew rate  
Input reference level  
VDDQ/2  
Output reference level  
Output load  
Fig. 1  
Notes:  
1. Include scope and jig capacitance.  
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.  
3. Device is deselected as defined by the Truth Table.  
Output Load 1  
DQ  
*
50Ω  
30pF  
V
DDQ/2  
* Distributed Test Jig Capacitance  
Rev: 1.07 2/2011  
13/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
DC Electrical Characteristics  
Parameter  
Symbol  
Test Conditions  
Min  
Max  
Input Leakage Current  
(except mode pins)  
IIL  
VIN = 0 to VDD  
–1 uA  
1 uA  
VDD ≥ VIN ≥ VIH  
0 V ≤ VIN ≤ VIH  
–1 uA  
–1 uA  
1 uA  
100 uA  
IIN1  
ZZ Input Current  
VDD ≥ VIN ≥ VIL  
0 V ≤ VIN ≤ VIL  
–100 uA  
–1 uA  
1 uA  
1 uA  
IIN2  
FT, SCD, ZQ Input Current  
IOL  
Output Disable, VOUT = 0 to VDD  
IOH = –8 mA, VDDQ = 2.375 V  
IOH = –8 mA, VDDQ = 3.135 V  
IOL = 8 mA  
Output Leakage Current  
Output High Voltage  
Output High Voltage  
Output Low Voltage  
–1 uA  
1.7 V  
2.4 V  
—
1 uA  
—
VOH2  
VOH3  
VOL  
—
0.4 V  
Rev: 1.07 2/2011  
14/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Rev: 1.07 2/2011  
15/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
AC Electrical Characteristics  
-250  
-225  
-200  
-166  
-150  
-133  
Parameter  
Symbol  
Unit  
Min Max Min Max Min Max Min Max Min Max Min Max  
Clock Cycle Time  
Clock to Output Valid  
Clock to Output Invalid  
tKC  
tKQ  
4.0  
—
—
2.5  
—
—
—
—
—
6.5  
—
—
—
—
—
—
4.4  
—
—
2.7  
—
—
—
—
—
6.5  
—
—
—
—
—
—
5.0  
—
—
3.0  
—
—
—
—
—
6.5  
—
—
—
—
—
—
6.0  
—
—
3.5  
—
—
—
—
—
7.0  
—
—
—
—
—
—
6.7  
—
—
3.8  
—
—
—
—
—
7.5  
—
—
—
—
—
—
7.5  
—
1.5  
1.5  
1.5  
0.5  
8.5  
—
3.0  
3.0  
1.5  
0.5  
1.7  
2
—
4.0  
—
—
—
—
—
8.5  
—
—
—
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tKQX  
1.5  
1.5  
1.3  
0.2  
6.5  
—
1.5  
1.5  
1.3  
0.3  
6.5  
—
1.5  
1.5  
1.4  
0.4  
6.5  
—
1.5  
1.5  
1.5  
0.5  
7.0  
—
1.5  
1.5  
1.5  
0.5  
7.5  
—
Pipeline  
tLZ1  
tS  
Clock to Output in Low-Z  
Setup time  
Hold Time  
tH  
Clock Cycle Time  
Clock to Output Valid  
tKC  
tKQ  
tKQX  
Clock to Output Invalid  
3.0  
3.0  
1.5  
0.5  
1.3  
1.5  
3.0  
3.0  
1.5  
0.5  
1.3  
1.5  
3.0  
3.0  
1.5  
0.5  
1.3  
1.5  
3.0  
3.0  
1.5  
0.5  
1.3  
1.5  
3.0  
3.0  
1.5  
0.5  
1.5  
1.7  
Flow  
Through  
tLZ1  
tS  
Clock to Output in Low-Z  
Setup time  
Hold time  
tH  
Clock HIGH Time  
Clock LOW Time  
tKH  
tKL  
Clock to Output in  
High-Z  
tHZ1  
1.5  
2.5  
1.5  
2.7  
1.5  
3.0  
1.5  
3.0  
1.5  
3.0  
1.5  
3.0  
ns  
G to Output Valid  
G to output in Low-Z  
G to output in High-Z  
ZZ setup time  
tOE  
—
0
2.5  
—
2.5  
—
—
—
—
0
2.7  
—
2.7  
—
—
—
—
0
3.2  
—
3.0  
—
—
—
—
0
3.5  
—
3.0  
—
—
—
—
0
3.8  
—
3.0  
—
—
—
—
0
4.0  
—
3.0  
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
tOLZ1  
tOHZ1  
tZZS2  
—
5
—
5
—
5
—
5
—
5
—
5
tZZH2  
tZZR  
ZZ hold time  
1
1
1
1
1
1
ZZ recovery  
20  
20  
20  
20  
20  
20  
Notes:  
1. These parameters are sampled and are not 100% tested.  
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold  
times as specified above.  
Rev: 1.07 2/2011  
16/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Pipeline Mode Timing (SCD)  
Begin  
Read A Cont  
Single Read  
Cont  
Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont  
Deselect  
Single Write  
tKL  
Burst Read  
tKH  
tKC  
CK  
ADSP  
tS  
tS  
tH  
ADSC initiated read  
ADSC  
ADV  
tS  
tH  
tH  
A
B
C
A0–An  
GW  
tS  
tS  
tH  
tH  
BW  
tS  
Ba–Bd  
E1  
tS  
tS  
tS  
Deselected with E1  
tH  
E1 masks ADSP  
tH  
tH  
E2 and E3 only sampled with ADSP and ADSC  
E2  
E3  
G
tS  
D(B)  
tKQ  
tKQX  
tHZ  
tOE  
tOHZ  
Q(A)  
tH  
tLZ  
Q(C)  
Q(C+1)  
Q(C+2) Q(C+3)  
DQa–DQd  
Rev: 1.07 2/2011  
17/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Flow Through Mode Timing (SCD)  
Begin  
Read A Cont  
tKH  
Cont  
Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont  
Deselect  
tKL  
tKC  
CK  
Fixed High  
ADSP  
tS  
tH  
tS  
tH  
ADSC initiated read  
ADSC  
ADV  
A0–An  
GW  
tS  
tH  
tS  
tH  
A
B
C
tS  
tH  
tS  
tH  
BW  
tS  
tH  
Ba–Bd  
E1  
tS  
tS  
Deselected with E1  
tH  
tH  
E2 and E3 only sampled with ADSC  
E2  
tS  
tH  
E3  
G
tH  
tS  
tKQ  
tLZ  
tHZ  
tOE  
tOHZ  
D(B)  
tKQX  
Q(A)  
Q(C)  
Q(C+1)  
Q(C+2)  
Q(C+3)  
Q(C)  
DQa–DQd  
Rev: 1.07 2/2011  
18/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Pipeline Mode Timing (DCD)  
Begin  
Read A Cont  
Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont  
tKL  
Deselect Deselect  
tKH  
tKC  
CK  
ADSP  
tS  
tS  
ADSC initiated read  
tH  
ADSC  
ADV  
tS  
tH  
tH  
A
B
C
Ao–An  
GW  
tS  
tS  
tH  
tH  
BW  
tS  
Ba–Bd  
E1  
tS  
tS  
tS  
Deselected with E1  
tH  
E2 and E3 only sampled with ADSC  
tH  
tH  
E2  
E3  
G
tS  
D(B)  
tKQ  
tHZ  
tOE  
tOHZ  
Q(A)  
tH  
tLZ  
tKQX  
Hi-Z  
Q(C)  
Q(C+1)  
Q(C+2)  
Q(C+3)  
DQa–DQd  
Rev: 1.07 2/2011  
19/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Flow Through Mode Timing (DCD)  
Begin  
Read A Cont  
tKH  
Deselect Write B  
tKC  
Read C Read C+1 Read C+2 Read C+3 Read C Deselect  
tKL  
CK  
Fixed High  
ADSP  
tS  
tH  
tS  
tH  
ADSC initiated read  
ADSC  
ADV  
Ao–An  
GW  
tH  
tS  
tS  
tH  
tS  
tH  
A
B
C
tS  
tH  
tS  
tH  
BW  
tH  
tS  
Ba–Bd  
E1  
tS  
Deselected with E1  
tH  
E1 masks ADSP  
tS  
tH  
E2 and E3 only sampled with ADSP and ADSC  
E1 masks ADSP  
E2  
tS  
tH  
E3  
G
tH  
tS  
tOE  
tKQ  
tKQX  
tHZ  
tOHZ  
D(B)  
tLZ  
Q(A)  
Q(C)  
Q(C+1)  
Q(C+2)  
Q(C+3)  
Q(C)  
DQa–DQd  
Rev: 1.07 2/2011  
20/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Sleep Mode  
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,  
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to  
low, the SRAM operates normally after ZZ recovery time.  
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of  
SB  
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become  
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.  
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending  
SB  
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated  
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands  
may be applied while the SRAM is recovering from Sleep mode.  
Sleep Mode Timing Diagram  
tKH  
tKC  
tKL  
CK  
Setup  
Hold  
ADSP  
ADSC  
tZZR  
tZZS  
tZZH  
ZZ  
Application Tips  
Single and Dual Cycle Deselect  
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with  
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually  
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste  
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at  
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.  
JTAG Port Operation  
Overview  
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan  
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output  
DD  
drivers are powered by V  
.
DDQ  
Disabling the JTAG Port  
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless  
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG  
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.  
DD  
SS  
Rev: 1.07 2/2011  
21/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
JTAG Pin Descriptions  
Pin  
Pin Name  
I/O  
Description  
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate  
from the falling edge of TCK.  
TCK  
Test Clock  
In  
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP  
TMS  
TDI  
Test Mode Select  
Test Data In  
In controller state machine. An undriven TMS input will produce the same result as a logic one input  
level.  
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers  
placed between TDI and TDO. The register placed between TDI and TDO is determined by the  
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP  
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce  
the same result as a logic one input level.  
Output that is active depending on the state of the TAP state machine. Output changes in  
Out response to the falling edge of TCK. This is the output side of the serial registers placed between  
TDI and TDO.  
TDO  
Test Data Out  
Note:  
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is  
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.  
JTAG Port Registers  
Overview  
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s  
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the  
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the  
TDI and TDO pins.  
Instruction Register  
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or  
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the  
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the  
controller is placed in Test-Logic-Reset state.  
Bypass Register  
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through  
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.  
Boundary Scan Register  
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.  
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The  
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the  
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan  
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in  
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,  
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.  
Rev: 1.07 2/2011  
22/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
JTAG TAP Block Diagram  
·
·
·
·
·
·
·
·
Boundary Scan Register  
·
·
·
0
Bypass Register  
2
1 0  
Instruction Register  
TDI  
TDO  
ID Code Register  
31 30 29  
2 1  
0
·
· · ·  
Control Signals  
Test Access Port (TAP) Controller  
TMS  
TCK  
* For the value of M, see the BSDL file, which is available at by contacting us at apps@gsitechnology.com.  
Identification (ID) Register  
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in  
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.  
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the  
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.  
ID Register Contents  
GSI Technology  
Not Used  
JEDEC Vendor  
ID Code  
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1  
0 1 1 0 1 1 0 0 1  
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
Rev: 1.07 2/2011  
23/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Tap Controller Instruction Set  
Overview  
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific  
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be  
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load  
address, data or control signals into the RAM or to preload the I/O buffers.  
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.  
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired  
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the  
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this  
device is listed in the following table.  
JTAG Tap Controller State Diagram  
Test Logic Reset  
1
0
1
1
1
Run Test Idle  
Select DR  
Select IR  
0
0
0
1
1
1
1
Capture DR  
Capture IR  
0
0
Shift DR  
Shift IR  
0
0
1
1
Exit1 DR  
Exit1 IR  
0
0
Pause DR  
Pause IR  
0
0
0
0
1
1
Exit2 DR  
Exit2 IR  
1
1
Update DR  
Update IR  
1
0
1
0
Instruction Descriptions  
BYPASS  
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This  
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-  
tate testing of other devices in the scan path.  
Rev: 1.07 2/2011  
24/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is  
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and  
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and  
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because  
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents  
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will  
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the  
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP  
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then  
places the boundary scan register between the TDI and TDO pins.  
EXTEST  
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with  
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is  
still determined by its input pins.  
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.  
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output  
drivers on the falling edge of TCK when the controller is in the Update-IR state.  
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-  
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-  
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR  
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-  
ated.  
IDCODE  
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and  
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction  
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.  
SAMPLE-Z  
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-  
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR  
state.  
RFU  
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.  
Rev: 1.07 2/2011  
25/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
JTAG TAP Instruction Set Summary  
Instruction  
EXTEST  
Code  
000  
Description  
Notes  
1
Places the Boundary Scan Register between TDI and TDO.  
Preloads ID Register and places it between TDI and TDO.  
IDCODE  
001  
1, 2  
Captures I/O ring contents. Places the Boundary Scan Register between TDI and  
SAMPLE-Z  
010  
011  
TDO.  
1
1
Forces all RAM output drivers to High-Z.  
Do not use this instruction; Reserved for Future Use.  
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.  
RFU  
SAMPLE/  
PRELOAD  
Captures I/O ring contents. Places the Boundary Scan Register between TDI and  
TDO.  
100  
101  
110  
111  
1
1
1
1
GSI  
GSI private instruction.  
Do not use this instruction; Reserved for Future Use.  
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.  
RFU  
BYPASS  
Places Bypass Register between TDI and TDO.  
Notes:  
1. Instruction codes expressed in binary, MSB on left, LSB on right.  
2. Default instruction automatically loaded at power-up and in test-logic-reset state.  
Rev: 1.07 2/2011  
26/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
JTAG Port Recommended Operating Conditions and DC Characteristics (2.5/3.3 V Version)  
Parameter  
Symbol  
Min.  
Max.  
Unit Notes  
V
0.6 * V  
V
V
V
+0.3  
2.5 V Test Port Input High Voltage  
2.5 V Test Port Input High Voltage  
3.3 V Test Port Input High Voltage  
3.3 V Test Port Input Low Voltage  
TMS, TCK and TDI Input Leakage Current  
TMS, TCK and TDI Input Leakage Current  
TDO Output Leakage Current  
V
V
1
1
IHJ2  
DD2  
DD2  
DD2  
DD3  
V
0.6 * V  
2.0  
+0.3  
+0.3  
IHJ2  
DD2  
V
V
1
IHJ3  
V
–0.3  
–300  
–1  
0.8  
V
1
ILJ3  
I
1
100  
1
uA  
uA  
uA  
V
2
INHJ  
I
3
INLJ  
I
–1  
4
OLJ  
V
Test Port Output High Voltage  
1.7  
—
0.4  
—
5, 6  
5, 7  
5, 8  
5, 9  
OHJ  
V
Test Port Output Low Voltage  
—
V
OLJ  
V
V
– 100 mV  
DDQ  
Test Port Output CMOS High  
V
OHJC  
V
Test Port Output CMOS Low  
—
100 mV  
V
OLJC  
Notes:  
1. Input Under/overshoot voltage must be –2 V < Vi < V  
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.  
DDn  
2.  
V
≤ V ≤ V  
ILJ  
IN  
DDn  
3. 0 V ≤ V ≤ V  
IN  
ILJn  
4. Output Disable, V  
= 0 to V  
DDn  
OUT  
5. The TDO output driver is served by the V  
supply.  
DDQ  
6.  
7.  
8.  
9.  
I
I
I
I
= –4 mA  
OHJ  
= + 4 mA  
OLJ  
= –100 uA  
= +100 uA  
OHJC  
OLJC  
JTAG Port AC Test Conditions  
Parameter  
Conditions  
JTAG Port AC Test Load  
V
– 0.2 V  
Input high level  
Input low level  
DQ  
DD  
0.2 V  
1 V/ns  
*
50Ω  
Input slew rate  
30pF  
V
V
/2  
Input reference level  
DDQ  
V
/2  
DDQ  
/2  
Output reference level  
DDQ  
* Distributed Test Jig Capacitance  
Notes:  
1. Include scope and jig capacitance.  
2. Test conditions as shown unless otherwise noted.  
Rev: 1.07 2/2011  
27/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
JTAG Port Timing Diagram  
tTKC  
tTKH  
tTKL  
TCK  
tTH  
tTH  
tTS  
tTS  
TDI  
TMS  
TDO  
tTKQ  
tTH  
tTS  
Parallel SRAM input  
JTAG Port AC Electrical Characteristics  
Parameter  
Symbol  
tTKC  
tTKQ  
tTKH  
tTKL  
tTS  
Min  
Max  
—
Unit  
TCK Cycle Time  
50  
—
ns  
ns  
ns  
ns  
ns  
ns  
TCK Low to TDO Valid  
TCK High Pulse Width  
TCK Low Pulse Width  
TDI & TMS Set Up Time  
TDI & TMS Hold Time  
20  
—
20  
20  
10  
10  
—
—
tTH  
—
Boundary Scan (BSDL Files)  
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications  
Engineering Department at: apps@gsitechnology.com.  
Rev: 1.07 2/2011  
28/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Package Dimensions—165-Bump FPBGA (Package E (MCM))  
A1  
1
TOP  
7
BOTTOM  
M
A1  
Ø0.10  
C
M
Ø0.25 C AB  
Ø0.40~0.60  
2
3
4
5
6
8 9 10  
11 10 9 8  
7
6 5 4 3 2  
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
M
N
P
K
L
M
N
P
R
R
A
1.0  
1.0  
10.  
15±0.0  
B
0.20(4  
SEATING  
C
Rev: 1.07 2/2011  
29/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Package Dimensions—165-Bump FPBGA (Package GE (MCM))  
A1  
1
TOP  
7
BOTTOM  
M
A1  
Ø0.10  
C
M
Ø0.25 C AB  
Ø0.40~0.60  
2
3
4
5
6
8 9 10  
11 10 9 8  
7
6 5 4 3 2  
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
M
N
P
K
L
M
N
P
R
R
A
1.0  
1.0  
10.  
15±0.0  
B
0.20(4  
SEATING  
C
Rev: 1.07 2/2011  
30/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Ordering Information for GSI Synchronous Burst RAMs  
2
Voltage  
Option  
Speed  
3
1
Org  
Type  
Package  
T
Part Number  
A
(MHz/ns)  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
4M x 18  
4M x 18  
GS864418E-250  
GS864418E-225  
GS864418E-200  
GS864418E-166  
GS864418E-150  
GS864418E-133  
GS864436E-250  
GS864436E-225  
GS864436E-200  
GS864436E-166  
GS864436E-150  
GS864436E-133  
GS864418E-250I  
GS864418E-225I  
GS864418E-200I  
GS864418E-166I  
GS864418E-150I  
GS864418E-133I  
GS864436E-250I  
GS864436E-225I  
GS864436E-200I  
GS864436E-166I  
GS864436E-150I  
GS864436E-133I  
GS864418GE-250  
GS864418GE-225  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
165 BGA  
165 BGA  
250/6.5  
225/6.5  
200/6.5  
166/8  
C
C
C
C
C
C
C
C
C
C
C
C
I
165 BGA  
165 BGA  
165 BGA  
150/8.5  
133/8.5  
250/6.5  
225/6.5  
200/6.5  
166/8  
165 BGA  
165 BGA  
165 BGA  
165 BGA  
165 BGA  
165 BGA  
150/8.5  
133/8.5  
250/6.5  
225/6.5  
200/6.5  
166/8  
165 BGA  
165 BGA  
165 BGA  
I
165 BGA  
I
165 BGA  
I
165 BGA  
150/8.5  
133/8.5  
250/6.5  
225/6.5  
200/6.5  
166/8  
I
165 BGA  
I
165 BGA  
I
165 BGA  
I
165 BGA  
I
165 BGA  
I
165 BGA  
150/8.5  
133/8.5  
250/6.5  
225/6.5  
I
165 BGA  
I
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
C
C
Notes:  
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS864418E-150IB.  
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each  
device is Pipeline/Flow Through mode-selectable by the user.  
3. C = Commercial Temperature Range. I = Industrial Temperature Range.  
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are  
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.  
Rev: 1.07 2/2011  
31/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
Ordering Information for GSI Synchronous Burst RAMs (Continued)  
2
Voltage  
Option  
Speed  
3
1
Org  
Type  
Package  
T
Part Number  
A
(MHz/ns)  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
4M x 18  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
2M x 36  
GS864418GE-200  
GS864418GE-166  
GS864418GE-150  
GS864418GE-133  
GS864436GE-250  
GS864436GE-225  
GS864436GE-200  
GS864436GE-166  
GS864436GE-150  
GS864436GE-133  
GS864418GE-250I  
GS864418GE-225I  
GS864418GE-200I  
GS864418GE-166I  
GS864418GE-150I  
GS864418GE-133I  
GS864436GE-250I  
GS864436GE-225I  
GS864436GE-200I  
GS864436GE-166I  
GS864436GE-150I  
GS864436GE-133I  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
Synchronous Burst MCM  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
3.3 V or 2.5 V  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
RoHS-compliant 165 BGA  
200/6.5  
166/8  
C
C
C
C
C
C
C
C
C
C
I
150/8.5  
133/8.5  
250/6.5  
225/6.5  
200/6.5  
166/8  
150/8.5  
133/8.5  
250/6.5  
225/6.5  
200/6.5  
166/8  
I
I
I
150/8.5  
133/8.5  
250/6.5  
225/6.5  
200/6.5  
166/8  
I
I
I
I
I
I
150/8.5  
133/8.5  
I
I
Notes:  
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS864418E-150IB.  
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each  
device is Pipeline/Flow Through mode-selectable by the user.  
3. C = Commercial Temperature Range. I = Industrial Temperature Range.  
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are  
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.  
Rev: 1.07 2/2011  
32/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
GS864418/36E-250/225/200/166/150/133  
72Mb Sync SRAM Data Sheet Revision History  
DS/DateRev. Code: Old;  
New  
Types of Changes  
Format or Content  
Page;Revisions;Reason  
• Creation of new datasheet  
8644xx_r1  
• Updated Operating Currents table  
• Updated FT AC Characteristics for tKQ  
8644xx_r1; 8644xx_r1_01  
Content  
Content  
• Updated FT tKQ and PL tS/tH and FT current numbers for 250  
and 225 MHz (match 200 MHz)  
• Updated basic format  
• Added thermal characteristics to mechanical drawings  
• Updated JTAG section for module  
8644xx_r1_01;  
8644xx_r1_02  
• Updated format  
• Added variation information to package mechanicals  
8644xx_r1_02;  
8644xx_r1_03  
Format/Content  
Content  
• Corrected 165 mechanical drawing  
• Added RoHS-compliance information for 165 BGA  
8644xx_r1_03;  
8644xx_r1_04  
• Updated Truth Tables (pg. 15, 16)  
• Rev1.05a: updated coplanarity for 119/165/209 BGA  
mechanical  
8644xx_r1_04;  
8644xx_r1_05  
Content  
• Removed Preliminary banner  
• Updated Synchronous Truth Table (pg. 16)  
8644xx_r1_05;  
8644xx_r1_06  
Content  
Content  
• Removed NRND 119 BGA and 209 BGA  
8644xx_r1_06;  
8644xx_r1_07  
Rev: 1.07 2/2011  
33/33  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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GS864436E-150V

 4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs
GSI

GS864436E-150VT

 Cache SRAM, 2MX36, 7.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GSI

GS864436E-166

 4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs
GSI

GS864436E-166I

 4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs
GSI

GS864436E-166IT

 Cache SRAM, 2MX36, 7ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GSI

GS864436E-166IV

 4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs
GSI

GS864436E-166IVT

 暂无描述
GSI

GS864436E-166V

 4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs
GSI

GS864436E-166VT

 Cache SRAM, 2MX36, 7ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GSI

GS864436E-200

 4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs
GSI

GS864436E-200I

 4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs
GSI

GS864436E-200IT

 Cache SRAM, 2MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FPBGA-165
GSI
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