GS8662D18E-167_技术文档

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

333 MHz–167 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaQuad-II

Burst of 4 SRAM

1.8 V V

DD

1.8 V and 1.5 V I/O

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, and 36Mb and

future 144Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaQuad™ Family Overview

The GS8662D08/09/18/36E are built in compliance with the

SigmaQuad-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662D08/18/36E SigmaQuad SRAMs are

just one element in a family of low power, low voltage HSTL

I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Because Separate I/O SigmaQuad-II B4 RAMs always transfer

data in four packets, A0 and A1 are internally set to 0 for the

first read or write transfer, and automatically incremented by 1

for the next transfers. Because the LSBs are tied off internally,

the address field of a SigmaQuad-II B4 RAM is always two

address pins less than the advertised index depth (e.g., the 4M

x 18 has a 1024K addressable index).

Clocking and Addressing Schemes

The GS8662D08/09/18/36E SigmaQuad-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

Parameter Synopsis

- 333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

6.0 ns

0.50 ns

tKHKH

tKHQV

Rev: 1.01a 2/2006

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

2M x 36 SigmaQuad-II SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

MCL/SA

(288Mb)

MCL/SA

(144Mb)

A

CQ

SA

W

BW2

K

BW1

R

SA

CQ

B

C

D

E

F

Q27

D27

D28

Q29

Q30

D30

Doff

D31

Q32

Q33

D33

D34

Q35

TDO

Q18

Q28

D20

D29

Q21

D22

D18

D19

Q19

Q20

D21

Q22

SA

BW3

SA

K

BW0

SA

D17

D16

Q16

Q15

D14

Q13

Q17

Q7

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

V

NC

V

SS

V

D15

D6

SS

DD

SS

DD

V

DDQ

V

Q14

D13

DDQ

G

H

J

V

REF

DDQ

Q31

D32

Q24

Q34

D26

D35

TCK

D23

Q23

D24

D25

Q25

Q26

SA

D12

Q12

D11

D10

Q10

Q9

Q4

D3

K

L

V

Q11

Q1

DDQ

SS

M

N

P

R

V

SS

V

SA

C

SA

V

D9

SA

D0

C

SA

TMS

2

11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35

2. MCL = Must Connect Low

Rev: 1.01a 2/2006

2/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

4M x 18 SigmaQuad-II SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

MCL/SA

(144Mb)

A

CQ

SA

W

BW1

K

NC

R

SA

CQ

B

C

D

E

F

NC

Doff

NC

TDO

Q9

NC

D9

SA

NC

SA

K

BW0

SA

NC

Q7

NC

D6

NC

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

D10

Q10

Q11

D12

Q13

V

NC

V

SS

D11

NC

V

SS

DD

SS

DD

V

DDQ

Q12

D13

V

DDQ

G

H

J

V

REF

DDQ

NC

D14

Q14

D15

D16

Q16

Q17

SA

NC

Q4

K

L

V

NC

SA

D3

NC

Q1

Q15

NC

V

DDQ

SS

M

N

P

R

V

SS

D17

NC

V

SA

C

SA

V

NC

D0

SA

TCK

C

TMS

2

11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.

2. MCL = Must Connect Low

Rev: 1.01a 2/2006

3/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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8M x 9 SigmaQuad-II SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

CQ

SA

W

NC

K

NC

R

SA

CQ

NC

D5

NC

D6

NC

Q5

NC

Q6

SA

NC

SA

K

BW0

SA

NC

D3

Q4

D4

NC

Q3

NC

ZQ

D2

NC

Q1

D1

NC

Q0

TDI

V

NC

V

SS

V

SS

DD

SS

DD

V

DDQ

V

NC

DDQ

G

H

J

V

D

V

REF

off

REF

DDQ

NC

Q2

K

L

NC

Q7

NC

D7

NC

Q8

SA

V

NC

SA

NC

D0

NC

V

DDQ

SS

M

N

P

R

NC

D8

V

SS

NC

V

SA

C

SA

V

NC

TCK

SA

TDO

C

TMS

2

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to D0:D8.

2. MCL = Must Connect Low

Rev: 1.01a 2/2006

4/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

8M x 8 SigmaQuad-II SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

CQ

SA

W

NW1

K

NC

R

SA

CQ

NC

Doff

NC

TDO

NC

D4

NC

D5

NC

Q4

NC

Q5

SA

NC

SA

K

NW0

SA

NC

D2

Q3

D3

NC

Q2

NC

ZQ

D1

NC

Q0

D0

NC

TDI

V

NC

V

SS

V

SS

DD

SS

DD

V

DDQ

V

NC

DDQ

G

H

J

V

REF

DDQ

NC

Q1

K

L

NC

Q6

NC

D6

NC

Q7

SA

V

NC

SA

NC

V

DDQ

SS

M

N

P

R

NC

D7

V

NC

SS

V

SA

C

SA

V

NC

TCK

SA

NC

C

TMS

2

11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch

Notes:

1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.

2. MCL = Must Connect Low

Rev: 1.01a 2/2006

5/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

Pin Description Table

Symbol

Description

Synchronous Address Inputs

No Connect

Type

Input

—

Comments

—

SA

NC

R

—

Synchronous Read

Synchronous Write

Input

Active Low

W

Active Low

x9/x18/x36 only

BW0–BW3

NW0–NW1

Synchronous Byte Writes

Nybble Write Control Pin

Input

Active Low

x8 only

K

Input Clock

Input

Active High

Active Low

C

Output Clock

Input

Active High

C

Output Clock

Input

Active Low

TMS

TDI

TCK

TDO

Test Mode Select

Input

—

Test Data Input

Input

Test Clock Input

Input

Test Data Output

Output

Input

V

HSTL Input Reference Voltage

Output Impedance Matching Input

Synchronous Data Outputs

Synchronous Data Inputs

Disable DLL when low

Output Echo Clock

Power Supply

REF

ZQ

Qn

Dn

Input

Output

Input

D

Input

Active Low

off

CQ

Output

Supply

—

V

1.8 V Nominal

DD

V

Isolated Output Buffer Supply

Power Supply: Ground

Supply

1.5 or 1.8 V Nominal

—

DDQ

V

SS

Note:

NC = Not Connected to die or any other pin

Rev: 1.01a 2/2006

6/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are

needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O

SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from

Separate I/O SRAMs can cut the RAM’s bandwidth in half.

Alternating Read-Write Operations

SigmaQuad-II SRAMs follow a few simple rules of operation.

- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.

- Read or Write data transfers in progress may not be interrupted and re-started.

- R and W high always deselects the RAM.

- All address, data, and control inputs are sampled on clock edges.

In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for

details.

SigmaQuad-II B4 SRAM DDR Read

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data

can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following

rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C,

and after the following rising edge of K with a rising edge of C. Clocking in a high on the Read Enable-bar pin, R, begins a read

port deselect cycle.

SigmaQuad-II B4 Double Data Rate SRAM Read First

Read A

NOP

Read B

Write C

Read D

Write E

NOP

K

Address

A

B

C

D

E

R

W

BWx

D

C

C+1

C+2

C+3

E

E+1

C

Q

A

A+1

A+2

A+3

B

B+1

B+2

B+3

D

D+1

D+2

CQ

Rev: 1.01a 2/2006

7/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

SigmaQuad-II B4 SRAM DDR Write

The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on

the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous

command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge

of K, and finally by the next rising edge of K. and by the rising edge of the K that follows.

SigmaQuad-II B4 Double Data Rate SRAM Write First

Write A

NOP

Read B

Write C

Read D

Write E

NOP

K

Address

A

B

C

D

E

R

W

BWx

D

A

A+1

A+2

A+3

C

C+1

C+2

C+3

E

E+1

E+

C

Q

B

B+1

B+2

B+3

D

D+1

D+2

CQ

Rev: 1.01a 2/2006

8/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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Power-Up Sequence for SigmaQuad-II SRAMs

SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.

Power-Up Sequence

1. Power-up and maintain Doff at low state.

1a. Apply V_DD

.

1b. Apply V_DDQ

.

1c. Apply V_REF(may also be applied at the same time as V_DDQ).

2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.

3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.

Note:

If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become

stablized.

DLL Constraints

• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t_KCVaron page 21).

• The DLL cannot operate at a frequency lower than 119 MHz.

• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during

the initial stage.

Power-Up Sequence (Doff controlled)

Power UP Interval

Unstable Clocking Interval

DLL Locking Interval (1024 Cycles)

Normal Operation

K

V

DD

V

DDQ

V

REF

Doff

Power-Up Sequence (Doff tied High)

Power UP Interval

Unstable Clocking Interval

Stop Clock Interval

30ns Min

DLL Locking Interval (1024 Cycles)

Normal Operation

K

V

DD

V

DDQ

V

REF

Doff

Note:

If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.

Rev: 1.01a 2/2006

9/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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Special Functions

Byte Write and Nybble Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18

version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble

Write Enable” and “NBx” may be substituted in all the discussion above.

Example x18 RAM Write Sequence using Byte Write Enables

Data In Sample

BW0

BW1

D0–D8

D9–D17

Time

Beat 1

Beat 2

Beat 3

Beat 4

0

1

0

1

0

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Resulting Write Operation

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Byte 1

D0–D8

Byte 2

D9–D17

Written

Unchanged

Written

Unchanged

Written

Beat 1

Beat 2

Beat 3

Beat 4

Output Register Control

SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output

Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the

output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K

and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to

function as a conventional pipelined read SRAM.

Rev: 1.01a 2/2006

10/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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Example Four Bank Depth Expansion Schematic

R

3

W

3

R

2

W

2

1

0

R

1

W

R

0

W

A –A

0

n

K

D –D

1

n

Bank 3

Bank 1

Bank 2

Bank 0

A

W

R

W

R

CQ

K

CQ

K

CQ

K

D

C

K

D

C

D

C

Q

D

C

Q

C

Q –Q

1

n

CQ

0

CQ

1

CQ

2

3

Note:

For simplicity BWn, NWn, K, and C are not shown.

Rev: 1.01a 2/2006

11/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

Rev: 1.01a 2/2006

12/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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FLXDrive-II Output Driver Impedance Control

HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to

via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be

V

SS

5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is

between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts

in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and

temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance

evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is

implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is

producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.

Separate I/O SigmaQuad-II B4 SRAM Truth Table

Current

Operation

A

R

W

D

Q

K

↑

(t_n)

K

↑

(t_n)

K

↑

(t_n)

K ↑

(t_n)

K ↑

(t_n+1½

K ↑

(t_n+2½

K ↑

(t_n+1½

K ↑

(t_n+2½)

(t_n-1

)

(t_n+1

)

(t_n+2

)

(t_n+1

)

(t_n+2

)

Deselect

Write

X

V

1

X

1

0

X

0

1

X

1

0

X

0

X

Deselect

Write

X

D2

X

D3

X

—

Hi-Z

Q2

Hi-Z

Q3

—

Read

—

Deselect

Read

D0

X

D1

X

D2

—

D3

—

Hi-Z

Q0

Hi-Z

Q1

—

Read

Q2

—

Q3

—

Write

D0

D2

D1

D3

D2

—

D3

—

Q2

Q3

Write

Read

Q0

Q1

Q2

Q3

Notes:

1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”

2. “—” indicates that the input requirement or output state is determined by the next operation.

3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.

4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.

5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-

ceded by a Read command.

6. Users should not clock in metastable addresses.

Rev: 1.01a 2/2006

13/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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Byte Write Clock Truth Table

BW

Current Operation

D

K ↑

(t_n+1½

K ↑

(t_n+2½

K ↑

(t_n)

K ↑

(t_n+1½

K ↑

(t_n+2½)

(t_n+1

)

(t_n+2

)

(t_n+1

)

(t_n+2

)

Write

T

F

T

F

T

F

T

F

D0

X

D2

X

D3

X

D4

X

Dx stored if BWn = 0 in all four data transfers

Write

T

F

T

F

Dx stored if BWn = 0 in 1st data transfer only

Write

D1

X

Dx stored if BWn = 0 in 2nd data transfer only

Write

X

D2

X

Dx stored if BWn = 0 in 3rd data transfer only

Write

X

D3

X

Dx stored if BWn = 0 in 4th data transfer only

Write Abort

X

No Dx stored in any of the four data transfers

Notes:

1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

2. If one or more BWn = 0, then BW = “T”, else BW = “F”.

Rev: 1.01a 2/2006

14/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

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x36 Byte Write Enable (BWn) Truth Table

BW0 BW1 BW2 BW3

D0–D8

Don’t Care

Data In

D9–D17

Don’t Care

Data In

D18–D26

Don’t Care

Data In

D27–D35

Don’t Care

Data In

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

x18 Byte Write Enable (BWn) Truth Table

BW0 BW1

D0–D8

Don’t Care

Data In

D9–D17

Don’t Care

Data In

1

0

1

0

1

0

Don’t Care

Data In

x09 Byte Write Enable (BWn) Truth Table

BW0

D0–D8

Don’t Care

Data In

1

0

1

0

Don’t Care

Data In

Rev: 1.01a 2/2006

15/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

Nybble Write Clock Truth Table

NW

Current Operation

D

K ↑

(t_n+1

)

(t_n+1½

)

(t_n+2

)

(t_n+2½

)

(t_n)

(t_n+1

)

(t_n+1½

)

(t_n+2

)

(t_n+2½)

Write

T

F

T

F

T

F

T

F

D0

X

D2

X

D3

X

D4

X

Dx stored if NWn = 0 in all four data transfers

Write

T

F

T

F

Dx stored if NWn = 0 in 1st data transfer only

Write

D1

X

Dx stored if NWn = 0 in 2nd data transfer only

Write

X

D2

X

Dx stored if NWn = 0 in 3rd data transfer only

Write

X

D3

X

Dx stored if NWn = 0 in 4th data transfer only

Write Abort

X

No Dx stored in any of the four data transfers

Notes:

1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

2. If one or more NWn = 0, then NW = “T”, else NW = “F”.

x8 Nybble Write Enable (NWn) Truth Table

NW0 NW1

D0–D3

Don’t Care

Data In

D4–D7

Don’t Care

Data In

1

0

1

0

1

0

Don’t Care

Data In

Rev: 1.01a 2/2006

16/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

State Diagram

Power-Up

Read NOP

Write NOP

READ

WRITE

READ

WRITE

Load New

Write Address

D Count = 0

Load New

Read Address

D Count = 0

READ

D Count = 2

WRITE

D Count = 2

WRITE

D Count = 2

READ

D Count = 2

Always

DDR Read

D Count = D Count + 1

DDR Write

D Count = D Count + 1

READ

Always

WRITE

D Count = 1

Always

D Count = 1

Increment

Read Address

Increment

Write Address

Notes:

1. Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+0, next internal burst address is A0+1.

2. “READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is

true for “WRITE” and “WRITE”.

3. Read and write state machine can be active simultaneously.

4. State machine control timing sequence is controlled by K.

Rev: 1.01a 2/2006

17/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

Description

Value

Unit

V

Voltage on V Pins

DD

–0.5 to 2.9

V

DD

V

Voltage in V

Pins

–0.5 to V

V

DDQ

REF

DD

V

–0.5 to V

REF

DDQ

V

–0.5 to V

+0.5 (≤ 2.9 V max.)

Voltage on I/O Pins

V

I/O

DDQ

V

+0.5 (≤ 2.9 V max.)

Voltage on Other Input Pins

Input Current on Any Pin

V

IN

I

+/–100

125

mA dc

IN

I

Output Current on Any I/O Pin

Maximum Junction Temperature

Storage Temperature

OUT

o

T

C

J

o

T

–55 to 125

C

STG

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect

reliability of this component.

Recommended Operating Conditions

Power Supplies

Parameter

Supply Voltage

Symbol

Min.

1.7

Typ.

1.8

Max.

Unit

V

1.9

V

DD

V

I/O Supply Voltage

Reference Voltage

1.4

1.5

DDQ

DD

V

0.68

—

0.95

REF

Notes:

1. The power supplies need to be powered up simultaneously or in the following sequence: V , V , V , followed by signal

DD DDQ REF

inputs. The power down sequence must be the reverse. V

must not exceed V .

DD

DDQ

2. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The

part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance

specifications quoted are evaluated for worst case in the temperature range marked on the device.

Operating Temperature

Parameter

Symbol

Min.

Typ.

Max.

Unit

Ambient Temperature

(Commercial Range Versions)

T

0

25

70

°C

A

Ambient Temperature

(Industrial Range Versions)

T

–40

25

85

°C

A

Rev: 1.01a 2/2006

18/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

HSTL I/O DC Input Characteristics

Parameter

DC Input Logic High

Symbol

Min

Max

Units

Notes

V

(dc)

V

+ 0.1

V

+ 0.3

DD

V

1

IH

REF

V (dc)

V

– 0.1

REF

DC Input Logic Low

–0.3

IL

Notes:

1. Compatible with both 1.8 V and 1.5 V I/O drivers

2. These are DC test criteria. DC design criteria is V

± 50 mV. The AC V /V levels are defined separately for measuring timing param-

REF

IH IL

eters.

3. V (Min)DC = –0.3 V, V (Min)AC = –1.5 V (pulse width ≤ 3 ns).

IL

4.

V

(Max)DC = V

+ 0.3 V, V (Max)AC = V

+ 0.85 V (pulse width ≤ 3 ns).

DDQ

IH

DDQ

IH

HSTL I/O AC Input Characteristics

Parameter

AC Input Logic High

Symbol

Min

Max

Units

mV

Notes

3,4

V

(ac)

V

+ 200

REF

—

IH

V (ac)

V

– 200

REF

AC Input Logic Low

—

mV

3,4

IL

V

Peak to Peak AC Voltage

V

(ac)

5% V

(DC)

REF

—

mV

1

REF

Notes:

1. The peak to peak AC component superimposed on V

may not exceed 5% of the DC component of V

.

REF

2. To guarantee AC characteristics, V ,V , Trise, and Tfall of inputs and clocks must be within 10% of each other.

IH IL

3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKHKH

V

+ 1.0 V

DD

V

SS

50%

V

DD

V

– 1.0 V

SS

20% tKHKH

V

IL

Rev: 1.01a 2/2006

19/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 1.8 V)

A

DD

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

pF

C

V

= 0 V

Input Capacitance

Output Capacitance

Clock Capacitance

4

6

5

7

6

IN

C

V

OUT

= 0 V

pF

OUT

C

V = 0 V

IN

pF

CLK

Note:

This parameter is sample tested.

AC Test Conditions

Parameter

Conditions

1.25 V

Input high level

Input low level

0.25 V

2 V/ns

0.75 V

Max. input slew rate

Input reference level

Output reference level

V

/2

DDQ

Note:

Test conditions as specified with output loading as shown unless otherwise noted.

AC Test Load Diagram

DQ

RQ = 250 Ω (HSTL I/O)

V

= 0.75 V

REF

50Ω

VT = V /2

DDQ

Input and Output Leakage Characteristics

Parameter

Symbol

Test Conditions

Min.

Max

Notes

Input Leakage Current

(except mode pins)

I

V = 0 to V

IN DD

–2 uA

2 uA

IL

V

≥ V ≥ V

IN

–2 uA

2 uA

DD

IL

I

Doff

INDOFF

0 V ≤ V ≤ V

IN

Output Disable,

= 0 to V

I

Output Leakage Current

–2 uA

2 uA

OL

V

OUT

DDQ

Rev: 1.01a 2/2006

20/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

Programmable Impedance HSTL Output Driver DC Electrical Characteristics

Parameter

Symbol

Min.

Max.

Units Notes

V

/2 – 0.12

V

/2 + 0.12

DDQ

Output High Voltage

Output Low Voltage

Output High Voltage

V

1, 3

2, 3

4, 5

4, 6

OH1

DDQ

V

/2 – 0.12

– 0.2

/2 + 0.12

DDQ

OL1

DDQ

V

DDQ

OH2

DDQ

V

Output Low Voltage

Vss

0.2

OL2

Notes:

1.

I

= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).

DDQ OH DDQ

OH

2.

I

= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).

OL

DDQ

OL

DDQ

3. Parameter tested with RQ = 250Ω and V

= 1.5 V or 1.8 V

DDQ

4. Minimum Impedance mode, ZQ = V

SS

5.

6.

I

= –1.0 mA

= 1.0 mA

OH

OL

Operating Currents

-333

-300

-250

-200

-167

Parameter

Symbol

Test Conditions

Notes

0

to

–40

to

0

to

–40

to

0

to

–40

to

0

to

–40

to

0

to

–40

to

70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C

V_DD= Max, I_OUT= 0 mA

I_DD

Operating Current (x36): DDR

Operating Current (x18): DDR

Operating Current (x9): DDR

Operating Current (x8): DDR

TBD TBD

TBD

2, 3

Cycle Time ≥ t_KHKHMin

V_DD= Max, I_OUT= 0 mA

Cycle Time ≥ t_KHKHMin

V_DD= Max, I_OUT= 0 mA

Cycle Time ≥ t_KHKHMin

V_DD= Max, I_OUT= 0 mA

Cycle Time ≥ t_KHKHMin

Device deselected,

^OUT= 0 mA, f = Max,

I_SB1

I

Standby Current (NOP): DDR

TBD TBD

TBD

2, 4

^{All Inputs}≤ 0.2 V or ≥ V_DD– 0.2 V

Notes:

1.

2.

Power measured with output pins floating.

Minimum cycle, I_OUT= 0 mA

Operating current is calculated with 50% read cycles and 50% write cycles.

Standby Current is only after all pending read and write burst operations are completed.

3.

4.

Rev: 1.01a 2/2006

21/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

AC Electrical Characteristics

-333

-300

-250

-200

-167

Parameter

Symbol

Units Notes

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Clock

t_KHKH

t_CHCH

K, K Clock Cycle Time

C, C Clock Cycle Time

3.0

—

3.5

0.2

—

3.3

—

4.2

0.2

—

4.0

—

6.3

0.2

—

5.0

—

7.88

0.2

—

6.0

—

8.4

0.2

—

ns

t_KCVar

tKC Variable

ns

5

t_KHKL

t_CHCL

K, K Clock High Pulse Width

C, C Clock High Pulse Width

1.2

1.32

1.6

2.0

2.4

t_KLKH

t_CLCH

K, K Clock Low Pulse Width

C, C Clock Low Pulse Width

1.2

—

1.32

1.49

—

1.6

—

2.0

—

2.4

2.7

—

ns

K to K High

C to C High

t_KHKH

1.35

0

1.8

0

2.2

0

t_KHCH

t_KCLock

t_KCReset

K, K Clock High to C, C Clock High

DLL Lock Time

1.30

—

0

1.45

—

1.8

—

2.3

—

0

2.8

—

ns

cycle

ns

1024

30

1024

30

1024

30

1024

30

1024

30

6

K Static to DLL reset

—

Output Times

t_KHQV

t_CHQV

K, K Clock High to Data Output Valid

C, C Clock High to Data Output Valid

—

0.45

—

0.45

—

0.45

—

0.45

—

–0.5

—

0.5

—

ns

3

t_KHQX

t_CHQX

K, K Clock High to Data Output Hold

C, C Clock High to Data Output Hold

–0.45

—

–0.45

—

–0.45

—

–0.45

—

t_KHCQV

t_CHCQV

K, K Clock High to Echo Clock Valid

C, C Clock High to Echo Clock Valid

0.45

—

0.45

—

0.45

—

0.45

—

0.5

—

t_KHCQX

t_CHCQX

K, K Clock High to Echo Clock Hold

C, C Clock High to Echo Clock Hold

–0.45

–0.5

t_CQHQV

t_CQHQX

t_KHQZ

t_CHQZ

t_KHQX1

t_CHQX1

CQ, CQ High Output Valid

CQ, CQ High Output Hold

—

0.25

—

0.27

—

0.30

—

0.35

—

0.40

—

ns

7

–0.25

–0.27

–0.30

–0.35

–0.40

K Clock High to Data Output High-Z

C Clock High to Data Output High-Z

—

0.45

—

0.45

—

0.45

—

0.45

—

0.5

—

ns

3

K Clock High to Data Output Low-Z

C Clock High to Data Output Low-Z

–0.45

–0.5

Setup Times

t_AVKH

t_IVKH

Address Input Setup Time

0.4

—

0.4

0.3

—

0.5

—

0.6

0.4

—

0.7

0.5

—

ns

Control Input Setup Time

Data Input Setup Time

2

t_DVKH

0.28

0.35

Rev: 1.01a 2/2006

22/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

AC Electrical Characteristics (Continued)

-333

-300

-250

-200

-167

Parameter

Symbol

Units Notes

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Hold Times

t_KHAX

t_KHIX

Address Input Hold Time

0.4

—

0.4

0.3

—

0.5

—

0.6

0.4

—

0.7

0.5

—

ns

Control Input Hold Time

t_KHDX

Data Input Hold Time

0.28

0.35

Notes:

1.

2.

3.

4.

All Address inputs must meet the specified setup and hold times for all latching clock edges.

Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).

If C, C are tied high, K, K become the references for C, C timing parameters

To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN param-

eter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the

same board to be at such different voltages and temperatures.

5.

6.

Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

V_DDslew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V_DDand input clock are stable.

7.

Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands

and test setup variations.

Rev: 1.01a 2/2006

23/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

Rev: 1.01a 2/2006

24/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

Rev: 1.01a 2/2006

25/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

Package Dimensions—165-Bump FPBGA (Package E)

A1 CORNER

TOP VIEW

BOTTOM VIEW

A1 CORNER

M

Ø0.10

C

Ø0.25 C A B

Ø0.40~0.60 (165x)

1

2 3 4 5 6 7 8 9 10 11

11 10 9 8

7 6 5 4 3 2 1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

M

N

P

R

A

1.0

10.0

1.0

15±0.05

B

0.20(4x)

SEATING PLANE

C

Rev: 1.01a 2/2006

26/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

Ordering Information—GSI SigmaQuad-II SRAM

Speed

(MHz)

3

1

Org

Type

Package

T

Part Number

A

8M x 8

8M x 9

4M x 18

GS8662D08E-333

GS8662D08E-300

GS8662D08E-250

GS8662D08E-200

GS8662D08E-167

GS8662D08E-333I

GS8662D08E-300I

GS8662D08E-250I

GS8662D08E-200I

GS8662D08E-167I

GS8662D09E-333

GS8662D09E-300

GS8662D09E-250

GS8662D09E-200

GS8662D09E-167

GS8662D09E-333I

GS8662D09E-300I

GS8662D09E-250I

GS8662D09E-200I

GS8662D09E-167I

GS8662D18E-333

GS8662D18E-300

GS8662D18E-250

GS8662D18E-200

GS8662D18E-167

GS8662D18E-333I

GS8662D18E-300I

GS8662D18E-250I

GS8662D18E-200I

GS8662D18E-167I

SigmaQuad-II SRAM

165-bump BGA

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

C

I

C

I

C

I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS866x36E-300T.

2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

Rev: 1.01a 2/2006

27/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

Ordering Information—GSI SigmaQuad-II SRAM

Speed

(MHz)

3

1

Org

Type

Package

T

Part Number

A

2M x 36

8M x 8

8M x 9

GS8662D36E-333

GS8662D36E-300

GS8662D36E-250

GS8662D36E-200

GS8662D36E-167

GS8662D36E-333I

GS8662D36E-300I

GS8662D36E-250I

GS8662D36E-200I

GS8662D36E-167I

GS8662D08E-333

GS8662D08GE-300

GS8662D08GE-250

GS8662D08GE-200

GS8662D08GE-167

GS8662D08GE-333I

GS8662D08GE-300I

GS8662D08GE-250I

GS8662D08GE-200I

GS8662D08GE-167I

GS8662D09GE-333

GS8662D09GE-300

GS8662D09GE-250

GS8662D09GE-200

GS8662D09GE-167

GS8662D09GE-333I

GS8662D09GE-300I

GS8662D09GE-250I

GS8662D09GE-200I

GS8662D09GE-167I

SigmaQuad-II SRAM

165-bump BGA

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

C

I

165-bump BGA

I

165-bump BGA

I

165-bump BGA

I

165-bump BGA

I

165-bump BGA

C

I

RoHS-compliant 165-bump BGA

I

C

I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS866x36E-300T.

2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

Rev: 1.01a 2/2006

28/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

Ordering Information—GSI SigmaQuad-II SRAM

Speed

(MHz)

3

1

Org

Type

Package

T

Part Number

A

4M x 18

2M x 36

GS8662D18GE-333

GS8662D18GE-300

GS8662D18GE-250

GS8662D18GE-200

GS8662D18GE-167

GS8662D18GE-333I

GS8662D18GE-300I

GS8662D18GE-250I

GS8662D18GE-200I

GS8662D18GE-167I

GS8662D36GE-333

GS8662D36GE-300

GS8662D36GE-250

GS8662D36GE-200

GS8662D36GE-167

GS8662D36GE-333I

GS8662D36GE-300I

GS8662D36GE-250I

GS8662D36GE-200I

GS8662D36GE-167I

SigmaQuad-II SRAM

RoHS-compliant 165-bump BGA

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

333

300

250

200

167

C

I

C

I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS866x36E-300T.

2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

Rev: 1.01a 2/2006

29/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS8662D18E-167
厂家：	GSI TECHNOLOGY
描述：	72Mb SigmaQuad-II Burst of 4 SRAM 4 SRAM 72MB SigmaQuad -II突发静态存储器
文件：	总29页 (文件大小：1472K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS8662D18E-167 [GSI]

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