GS8662Q08GE-278I [GSI]
Standard SRAM, 8MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165;型号: | GS8662Q08GE-278I |
厂家: | GSI TECHNOLOGY |
描述: | Standard SRAM, 8MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 静态存储器 |
文件: | 总34页 (文件大小:1516K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
GS8662Q08/09/18/36E-278/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
278 MHz–167 MHz
72Mb SigmaQuad-II
Burst of 2 SRAM
1.8 V V
DD
1.8 V and 1.5 V I/O
Features
Clocking and Addressing Schemes
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
The GSQ8662Q08/09/18/36E SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are indeendent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allos the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, and 36Mb and
future 144Mb devices
Each internal rad and write operation in a SigmaQuad-II B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simuaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore the address field of a
SigmaQuad-II B2 RAM is always one address pin less than the
advertised index depth (e.g., the 8M x 8 has an 4M addressable
index).
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuad™ Family Overview
The GSQ8662Q08/09/18/36E are built in compliance with
the SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GSQ8662Q08/09/18/36E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Parameter Synopsis
-278
3.6 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
tKHKH
tKHQV
6.0 ns
0.5 ns
.
Rev: 1.09a 11/2011
1/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
2M x 36 SigmaQuad-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
MCL/SA
(288Mb)
MCL/SA
(144Mb)
A
CQ
SA
W
BW2
K
BW1
R
SA
CQ
B
C
D
E
F
Q27
D27
D28
Q29
Q30
D30
Doff
D31
Q32
Q33
D33
D34
Q35
TDO
Q18
Q28
D20
D29
Q21
D22
D18
D19
Q19
Q20
D21
Q22
SA
BW3
SA
K
BW0
SA
SA
D17
D16
Q16
Q15
D14
Q13
Q17
Q7
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
V
SA
V
SS
SS
SS
S
V
V
V
V
V
V
V
D15
D6
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
Q14
D13
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
Q31
D32
Q24
Q34
D26
D35
TCK
D23
Q23
D24
D25
Q25
Q26
SA
D12
Q12
D11
D10
Q10
Q9
Q4
D3
K
L
V
V
V
V
V
V
Q11
Q1
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
SS
SS
SS
SS
V
SA
SA
SA
SA
C
SA
SA
SA
V
D9
SA
SA
SA
SA
D0
C
SA
TMS
2
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35.
2. MCL = Must Connect Low
Rev: 1.09a 11/2011
2/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
4M x 18 SigmaQuad-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
MCL/SA
(144Mb)
A
CQ
SA
W
BW1
K
NC
R
SA
SA
CQ
B
C
D
E
F
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
Q9
NC
D9
SA
NC
SA
K
BW0
SA
SA
NC
NC
NC
NC
NC
NC
NC
Q7
NC
D6
NC
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
D10
Q10
Q11
D12
Q13
V
SA
V
SS
SS
SS
S
D11
NC
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
Q12
D13
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
D14
Q14
D15
D16
Q16
Q17
SA
NC
Q4
K
L
V
NC
NC
NC
NC
NC
SA
D3
NC
Q1
Q15
NC
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
SS
SS
SS
SS
D17
NC
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
D0
SA
SA
SA
SA
TCK
C
TMS
2
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. MCL = Must Connect Low
Rev: 1.09a 11/2011
3/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
8M x 8 SigmaQuad-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ
SA
SA
W
NW1
K
NC
R
SA
SA
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
D4
NC
NC
D5
NC
NC
NC
Q4
NC
Q5
SA
NC
SA
K
NW0
SA
SA
NC
NC
NC
NC
NC
NC
NC
NC
NC
D2
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
V
SA
V
SS
SS
SS
SS
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
NC
NC
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
NC
Q1
K
L
NC
Q6
NC
D6
NC
NC
Q7
SA
V
NC
NC
NC
NC
NC
SA
NC
NC
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
NC
D7
V
V
NC
SS
SS
SS
SS
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
NC
TCK
SA
A
SA
SA
NC
C
TMS
2
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.
2. MCL = Must Connect Low
Rev: 1.09a 11/2011
4/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
8M x 9 SigmaQuad-II SRAM — Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ
SA
SA
W
NC
K
NC
R
SA
SA
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
D5
NC
NC
D6
NC
NC
NC
Q5
NC
Q6
SA
NC
SA
K
BW
SA
SA
NC
NC
NC
NC
NC
NC
NC
NC
NC
D3
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
V
SA
V
SS
SS
SS
SS
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
NC
NC
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
NC
Q2
K
L
NC
Q7
NC
D7
NC
NC
Q8
SA
V
NC
NC
NC
NC
NC
SA
NC
NC
NC
NC
D0
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
NC
D8
V
V
SS
SS
SS
SS
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
TCK
SA
A
SA
SA
C
TMS
2
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Note: MCL = Must Connect Low
Rev: 1.09a 11/2011
5/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Pin Description Table
Symbol
Description
Synchronous Address Inputs
No Connect
Type
Input
—
Comments
—
SA
NC
R
—
Synchronous Read
Synchronous Write
Input
Input
Active Low
Active Low
W
Active Low
x9 only
BW
Synchronous Byte Write
Synchronous Byte Writes
Nybble Write Control Pin
Input
Input
Input
Active Low
x18/x36 only
BW0–BW3
NW0–NW1
Active Low
x8 only
K
K
Input Clock
Input Clock
Input
Input
Active High
Active Low
C
Output Clock
Input
Active High
C
Output Clock
Input
Active Low
TMS
TDI
TCK
TDO
VREF
Test Mode Select
Input
—
—
—
—
—
—
Test Data Input
Input
Test Clock Input
Input
Test Data Output
Output
Input
HSTL Input Reference Voltage
Output Impedance Matching Input
Synchronous Data Outputs
Synchronous Data Inputs
Disable DLL when low
Outpt Echo Clock
Output Echo Clock
Power Supply
ZQ
Qn
Dn
Input
Output
Input
Input
Active Low
D
off
CQ
CQ
Output
Output
Supply
—
—
VDD
1.8 V Nominal
VDDQ
VSS
Isolated Output Buffer Supply
Power Supply: Ground
Supply
Supply
1.5 or 1.8 V Nominal
—
Notes:
1. NC = Not Connected to die or any other pin.
2. C, C, K, or K cannot be set to V voltage.
REF
Rev: 1.09a 11/2011
6/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
SigmaQuad-II B2 SRAM DDR Read
The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R,
begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied
high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high). Clocking in a high on the
Read Enable-bar pin, R, begins a read port deselect cycle.
SigmaQuad-II B2 Double Data Rate SRAM Read First
Read A
NOP
Write B
Read C Write D
Read E Write F
Read G Write H
K
K
Address
A
B
D
E
F
G
H
R
W
BWx
D
B
B
B+1
B+1
D
D+1
F
F+1
H
H
H+1
D
D+1
F
F+1
H+1
C
C
Q
A
A+1
C
C+1
E
CQ
CQ
Rev: 1.09a 11/2011
7/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
SigmaQuad-II B2 SRAM DDR Write
The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of
K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is
clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on
the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle.
SigmaQuad-II B2 Double Data Rate SRAM Write First
Write A
Read B
Read C Write D
NOP
Read E Write F
Read G Write H
NOP
K
K
Address
A
B
C
D
E
F
G
H
R
W
BWx
D
A
A
A+1
A+1
D
D
D+1
D+1
F
F
F+1
F+1
H
H
H+1
H+1
C
C
Q
B
B+1
C
C+1
E
E+1
CQ
CQ
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NBx” may be substituted in all the discussion above.
Rev: 1.09a 11/2011
8/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
D0–D8
D9–D17
Don’t Care
Data In
Beat 1
Beat 2
0
1
1
0
Data In
Don’t Care
Resulting Write Operation
Byte 1
D0–D8
Byte 2
D9–D17
Byte 3
D0–D8
Byte 4
D9–D17
Written
Unchanged
Unchanged
Written
Beat 1
Beat 2
Output Register Control
SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a w nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.
Rev: 1.09a 11/2011
9/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Example Four Bank Depth Expansion Schematic
R
3
W
3
R
2
W
2
1
0
R
1
W
R
0
W
A –A
0
n
K
D –D
1
n
Bank 3
Bank 1
Bank 2
Bank 0
A
A
A
A
W
R
W
W
W
R
R
R
CQ
K
CQ
K
CQ
CQ
K
D
C
K
D
C
D
C
Q
D
C
Q
Q
Q
C
Q –Q
1
n
CQ
0
CQ
1
CQ
CQ
2
3
Note:
For simplicity BWn, NWn, K, and C are not shown.
Rev: 1.09a 11/2011
10/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Rev: 1.09a 11/2011
11/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
SigmaQuad-II B2 Coherency and Pass Through Functions
Because the SigmaQuad-II B2 read and write commands are loaded at the same time, there may be some confusion over what
constitutes “coherent” operation. Normally, one would expect a RAM to produce the just-written data when it is read immediately
after a write. This is true of the SigmaQuad-II B2 except in one case, as is illustrated in the following diagram. If the user holds the
same address value in a given K clock cycle, loading the same address as a read address and then as a matching write address, the
SigmaQuad-II B2 will read or “Pass-thru” the latest data input, rather than the data from the previously completed write operation.
SigmaQuad-II B2 Coherency and Pass Through Functions
Rev: 1.09a 11/2011
12/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Read Truth Table
A
R
Output Next State
Q
Q
K ↑
n
K ↑
n
K ↑
n
K ↑
n+1
K ↑
n+1½
(t )
(t )
(t )
(t
)
(t
)
X
V
1
0
Deselect
Read
Hi-Z
Q0
Hi-Z
Q1
Notes:
1. X = Don’t Care, 1 = High, 0 = Low, V = Valid.
2. R is evaluated on the rising edge of K.
3. Q0 and Q1 are the first and second data output transfers in a read.
Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Write Truth Tale
A
W
BWn
BWn
Input Next State
D
D
K ↑
n + ½
K ↑
n
K ↑
n
K ↑
n + ½
K ↑
n
K ↑
n + ½
K ↑, K ↑
(t
)
(t )
(t )
(t
)
(tn), (tn + ½
)
(t )
(t
)
V
V
V
X
X
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Write Bye Dx0, Write Byte Dx1
Write Byte Dx0, Write Abort Byte Dx1
Write Abort Byte Dx0, Write Byte Dx1
Write Abort Byte Dx0, Write Abort Byte Dx1
Deselect
D0
D0
X
D1
X
D1
X
X
X
X
Notes:
1. X = Don’t Care, H = High, L = Low, V = Vali
2. W is evaluated on the rising edge of K.
3. D0 and D1 are the first and second data input transfers in a write.
4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.).
Rev: 1.09a 11/2011
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
x36 Byte Write Enable (BWn) Truth Table
BW0
BW1
BW2
BW3
D0–D8
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
D18–D26
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Daa In
D27–D35
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Don’t Care
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Data In
Data In
Data
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Data In
Data In
x18 Byte Write Enable (BWn) Truth Table
BW0
BW1
D0–D8
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
1
0
1
0
1
1
0
0
Don’t Care
Data In
Data In
x8 Nybble Write Enable (NWn) Truth Table
NW0
NW1
D0–D3
Don’t Care
Data In
D4–D7
Don’t Care
Don’t Care
Data In
1
0
1
0
1
0
0
Don’t Care
Data In
Data In
Rev: 1.09a 11/2011
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
VDD
Description
Value
–0.5 to 2.9
Unit
Voltage on VDD Pins
Voltage in VDDQ Pins
Voltage in VREF Pins
V
VDDQ
VREF
VI/O
–0.5 to VDD
V
V
–0.5 to VDDQ
–0.5 to VDDQ +0.5 (≤ 2.9 V max.)
–0.5 to VDDQ +0.5 (≤ 2.9 V max.)
Voltage on I/O Pins
V
VIN
Voltage on Other Input Pins
Input Current on Any Pin
V
IIN
+/–100
+/–100
125
mA dc
mA dc
IOUT
Output Current on Any I/O Pin
Maximum Junction Temperature
Storage Temperature
oC
oC
TJ
TSTG
–55 to 125
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are eceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Supply Voltage
Symbol
VDD
Min.
1.7
Typ.
1.8
—
Max.
1.9
Unit
V
VDDQ
VREF
I/O Supply Voltage
Reference Voltage
1.4
1.9
V
0.68
—
0.95
V
Note:
The power supplies need to be powered up simultaneously or in the following sequence: V , V , V , followed by signal inputs. The power
DD DDQ REF
down sequence must be the reverse. V
must not exceed V . For more information, read AN1021 SigmaQuad and SigmaDDR Power-
DD
DDQ
Up.
Operating Temperature
Parameter
Symbol
Min.
Typ.
Max.
Unit
Ambient Temperature
(Commercial RangVersions)
TA
0
25
70
°C
Ambient Temperature
(Industrial Range Versions)
TA
–40
25
85
°C
Rev: 1.09a 11/2011
15/34
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Thermal Impedance
Test PCB
Substrate
θ JA (C°/W)
Airflow = 0 m/s
θ JA (C°/W)
Airflow = 1 m/s
θ JA (C°/W)
Airflow = 2 m/s
θ JB (C°/W)
θ JC (C°/W)
Package
165 BGA
4-layer
16.3
13.4
12.4
6.2
1.5
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
HSTL I/O DC Input Characteristics
Parameter
Symbol
VIH (dc)
VIL (dc)
Min
Max
Units
Notes
VREF + 0.1
VDDQ + 0.3
VREF – 0.1
DC Input Logic High
V
V
1
1
–0.3
DC Input Logic Low
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers.
2. These are DC test criteria. DC design criteria is V
± 50 mV. The AC V /V levels are defined separately for measuring timing
REF
IH IL
parameters.
3. V (Min)DC = –0.3 V, V (Min)AC = –1.5 V (pulse width ≤ 3 ns).
IL
IL
4.
V
(Max)DC = V
+ 0.3 V, V (Max)AC = V
+ 0.85 V (pulse width ≤ 3 ns).
IH
DDQ
IH
DDQ
HSTL I/O AC Input Characteristics
Parameter
AC Input Logic High
Symbol
VIH (ac)
VIL (ac)
Min
Max
—
Units
mV
Notes
2,3
VREF + 200
VREF – 200
5% VREF (DC)
AC Input Logic Low
—
—
mV
2,3
V
Peak-to-Peak AC Voltage
VREF (ac)
mV
1
REF
Notes:
1. The peak-to-peak AC component superimposed on V
may not exceed 5% of the DC component of V
.
REF
REF
2. To guarantee AC characteristics, V ,V , Trise, and Tfall of inputs and clocks must be within 10% of each other.
IH IL
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Rev: 1.09a 11/2011
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKHKH
V
+ 1.0 V
DD
V
SS
50%
50%
V
DD
V
– 1.0 V
SS
20% tKHKH
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 1.8 V)
A
DD
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
Typ.
Max.
Unit
pF
Input Capacitance
Output Capacitance
Clock Capacitance
4
6
5
5
7
6
COUT
CCLK
VOUT = 0 V
VIN = 0 V
pF
pF
Note:
This parameter is sample tested.
AC Test Conditions
Parameter
Input high level
Input low level
Conditions
1.25 V
0.25 V
Max. input slew rate
Input reference level
Output reference level
2 V/ns
0.75 V
VDDQ/2
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
AC Test Load Diagram
DQ
RQ = 250 Ω (HSTL I/O)
= 0.75 V
V
REF
50Ω
VT = V /2
DDQ
Rev: 1.09a 11/2011
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GS8662Q08/09/18/36E-278/250/200/167
Input and Output Leakage Characteristics
Parameter
Symbol
Test Conditions
Min.
Max
Input Leakage Current
(except mode pins)
IIL
IINDOFF
IOL
VIN = 0 to VDD
–2 uA
2 uA
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–2 uA
–2 uA
2 uA
2 uA
Doff
Output Disable,
OUT = 0 to VDDQ
Output Leakage Current
–2 uA
2 uA
V
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter
Symbol
VOH1
Min.
Max.
Units
Notes
1, 3
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
V
V
V
V
Output High Voltage
Output Low Voltage
Output High Voltage
VOL1
2, 3
VOH2
4, 5
VOL2
Vss
0.2
4, 6
Output Low Voltage
Notes:
1.
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).
DDQ OH DDQ
OH
2.
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).
OL
DDQ
OL
DDQ
3. Parameter tested with RQ = 250Ω and V
4. 0Ω ≤ RQ ≤ ∞Ω
= 1.5 V or 1.8 V.
DDQ
5.
I
= –1.0 mA
OH
OL
6.
I
= 1.0 mA
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Operating Currents
-278
-250
-200
-167
Parameter
Symbol
Test Conditions
Notes
–40
to
0
to
–40
to
0
to
–40
to
0
to
–40
to
0
to 70°C
85°C
70°C
85°C
70°C
85°C
70°C
85°C
VDD = Max, IOUT = 0 mA
IDD
IDD
IDD
IDD
Operating Current (x36): DDR
Operating Current (x18): DDR
Operating Current (x9): DDR
Operating Current (x8): DDR
1050 mA 1075 mA 950 mA 975 mA 900 mA 925 mA 800 mA 825 mA
1000 mA 1025 mA 900 mA 925 mA 800 mA 825 mA 750 mA 775 mA
2, 3
2, 3
2, 3
2, 3
Cycle Time ≥ tKHKH Min
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
VDD = Max, IOUT = 0 mA
950 mA
950 mA
975 mA 850 mA 875 mA 750 mA 775 mA 700 mA 725 mA
975 mA 850 mA 875 mA 750 mA 775 mA 700 mA 725 mA
Cycle Time ≥ tKHKH Min
VDD = Max, IOUT = 0 mA
Cycle Time ≥ tKHKH Min
Device deselected,
IOUT = 0 mA, f = Max,
ISB1
Standby Current (NOP): DDR
315 mA
325 mA 305 mA 315 mA 285 mA 295 mA 270 mA 280 mA
2, 4
All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V
Notes:
1.
2.
Power measured with output pins floating.
Minimum cycle, IOUT = 0 mA
Operating current is calculated with 50% read cycles and 50% write cycles.
Standby Current is only after all pending read and write burst operations are completed.
3.
4.
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GS8662Q08/09/18/36E-278/250/200/167
AC Electrical Characteristics
-278
-250
-200
-167
Parameter
Symbol
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Clock
tKHKH
tCHCH
K, K Clock Cycle Time
C, C Clock Cycle Time
3.6
—
8.4
0.2
—
4.0
—
8.4
0.2
—
5.0
—
8.4
0.2
—
6.0
—
8.4
0.2
—
ns
ns
ns
tKCVar
tKC Variable
5
tKHKL
tCHCL
K, K Clock High Pulse Width
C, C Clock High Pulse Width
1.32
1.6
2.0
2.4
tKLKH
tCLCH
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
1.32
1.49
1.49
—
—
—
1.6
1.8
1.8
—
—
—
2.0
2.2
2
—
—
—
2.4
2.7
2.7
—
—
—
ns
ns
ns
tKHKH
tCHCH
K to K High
C to C High
tKHKH
tCHCH
K to K High
C to C High
tKHCH
tKCLock
tKCReset
K, K Clock High to C, C Clock High
DLL Lock Time
0
1.45
—
0
1.8
—
0
2.3
—
0
2.8
—
ns
cycle
ns
1024
30
1024
30
1024
30
1024
30
6
K Static to DLL reset
—
—
—
—
Output Times
tKHQV
tCHQV
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
—
0.45
—
—
0.45
—
—
0.45
—
—
–0.5
—
0.5
—
ns
ns
ns
ns
3
3
tKHQX
tCHQX
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
–0.45
—
–0.45
—
–0.45
—
tKHCQV
tCHCQV
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
0.45
—
0.45
—
0.45
—
0.5
—
tKHCQX
tCHCQX
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
–0.45
–0.45
–0.45
–0.5
tCQHQV
tCQHQX
tCQHCQH
tCQHCQH
tKHQZ
tCHQZ
tKHQX1
tCHQX1
CQ, CQ High Output Valid
CQ, CQ High Output Hold
—
0.27
—
—
0.30
—
—
0.35
—
—
0.40
—
ns
ns
7
7
–0.27
–0.30
–0.35
–0.40
CQ Phase Distortion
1.24
—
—
0.45
—
1.55
—
—
0.45
—
1.95
—
—
0.45
—
2.45
—
—
0.5
—
ns
ns
ns
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
3
3
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
–0.45
–0.45
–0.45
–0.5
Setup Times
tAVKH
tIVKH
Address Input Setup Time
0.3
0.3
0.3
—
—
—
0.35
0.35
0.35
—
—
—
0.4
0.4
0.4
—
—
—
0.5
0.5
0.5
—
—
—
ns
ns
ns
Control Input Setup Time
Data Input Setup Time
2
tDVKH
Rev: 1.09a 11/2011
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
AC Electrical Characteristics (Continued)
-278
-250
-200
-167
Parameter
Symbol
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Hold Times
tKHAX
tKHIX
Address Input Hold Time
0.3
0.3
0.3
—
—
—
0.35
0.35
0.35
—
—
—
0.4
0.4
0.4
—
—
—
0.5
0.5
0.5
—
—
—
ns
ns
ns
Control Input Hold Time
tKHDX
Data Input Hold Time
Notes:
1.
2.
3.
4.
All Address inputs must meet the specified setup and hold times for all latching clock edges.
Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).
If C, C are tied high, K, K become the references for C, C timing parameters
To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN
parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two
SRAMs on the same board to be at such different voltages and temperatures.
5.
6.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
7.
Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard
bands and test setup variations.
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GS8662Q08/09/18/36E-278/250/200/167
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22/34
© 2005, GSI Technology
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GS8662Q08/09/18/36E-278/250/200/167
Rev: 1.09a 11/2011
23/34
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GS8662Q08/09/18/36E-278/250/200/167
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DD
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation f the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be eft unconnected.
DD
SS
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active dependig on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controllis also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register stes. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Tst-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
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GS8662Q08/09/18/36E-278/250/200/167
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
·
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1
0
·
· · ·
Control Signals
Test Access Port (TAP) Controller
TMS
TCK
Identification (ID) Register
The ID Register is a 32-bit registr that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributs of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.09a 11/2011
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GS8662Q08/09/18/36E-278/250/200/167
ID Register Contents
GSI Technology
JEDEC Vendor
ID Code
Not Used
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0 1 1 0 1 1 0 0 1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.09a 11/2011
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© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers re in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data cature set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Rev: 1.09a 11/2011
27/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with whch each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
1
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z except CQ.
SAMPLE-Z
RFU
010
011
1
1
Do not use this instruction; Reserved for Future Use.
ReplicateBYPASS instruction. Places Bypass Register between TDI and TDO.
SAMPLE/PRELOAD
GSI
100
101
Captures /O ring contents. Places the Boundary Scan Register between TDI and TDO.
GSI private instruction.
1
1
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
110
111
1
1
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.09a 11/2011
28/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
–0.3
Max.
Unit Notes
V
0.3 * V
Test Port Input Low Voltage
V
V
1
1
ILJ
DD
V
0.6 * V
V
+0.3
DD
Test Port Input High Voltage
IHJ
DD
I
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
–300
–1
1
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
V
V
– 200 mV
—
0.4
—
5, 6
5, 7
5, 8
5, 9
OHJ
DD
V
—
V
OLJ
V
– 100 mV
V
OHJC
DD
V
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < V
+1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
3. 0 V ≤ V ≤ V
IN
ILJn
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V supply.
DD
6.
7.
8.
9.
I
I
I
I
= –2 mA
OHJ
= + 2 mA
OLJ
= –100 uA
= +100 uA
OHJC
OLJC
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
TDO
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
*
50Ω
30pF
Input slew rate
V
/2
DDQ
V
V
/2
Input reference level
DD
* Distributed Test Jig Capacitance
/2
Output reference level
DD
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.09a 11/2011
29/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
TDI
tTH
tTH
tTS
tTS
TMS
TDO
tTKQ
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
Max
—
Unit
TCK Cycle Time
50
—
ns
ns
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
20
20
10
10
—
—
tTH
—
Rev: 1.09a 11/2011
30/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Package Dimensions—165-Bump FPBGA (Package E)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.60 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
1.0
15±0.05
B
0.20(4x)
SEATING PLANE
C
Rev: 1.09a 11/2011
31/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Ordering Information—GSI SigmaQuad-II SRAM
Speed
(MHz)
3
1
Org
Type
Package
T
Part Number
A
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
GS8662Q36E-278
GS8662Q36E-250
GS8662Q36E-200
GS8662Q36E-167
GS8662Q36E-278I
GS8662Q36E-250I
GS8662Q36E-200I
GS8662Q36E-167I
GS8662Q18E-278
GS8662Q18E-250
GS8662Q18E-200
GS8662Q18E-167
GS8662Q18E-278I
GS8662Q18E-250I
GS8662Q18E-200I
GS8662Q18E-167I
GS8662Q09E-278
GS8662Q09E-250
GS8662Q09E-200
GS8662Q09E-167
GS8662Q09E-278I
GS8662Q09E-250I
GS8662Q09E-200I
GS8662Q09E-167I
GS8662Q08E-278
GS8662Q08E-250
GS8662Q08E-200
GS8662Q08E-167
G662Q08E-278I
GS8662Q08E-250I
GS8662Q08E-200I
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
278
250
200
167
278
250
200
167
278
250
200
167
278
250
200
167
278
250
200
167
278
250
200
167
278
250
200
167
278
250
200
C
C
C
C
I
I
I
I
C
C
C
C
I
I
I
I
C
C
C
C
I
I
I
I
C
C
C
C
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8662x36E-200T.
2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
Rev: 1.09a 11/2011
32/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Ordering Information—GSI SigmaQuad-II SRAM
Speed
(MHz)
3
1
Org
Type
Package
T
Part Number
A
8M x 8
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
GS8662Q08E-167I
GS8662Q36GE-278
GS8662Q36GE-250
GS8662Q36GE-200
GS8662Q36GE-167
GS8662Q36GE-278I
GS8662Q36GE-250I
GS8662Q36GE-200I
GS8662Q36GE-167I
GS8662Q18GE-278
GS8662Q18GE-250
GS8662Q18GE-200
GS8662Q18GE-167
GS8662Q18GE-278I
GS8662Q18GE-250I
GS8662Q18GE-200I
GS8662Q18GE-167I
GS8662Q09GE-278
GS8662Q09GE-250
GS8662Q09GE-200
GS8662Q09GE-167
GS8662Q09GE-278I
GS8662Q09GE-250I
GS8662Q09GE-200I
GS8662Q09GE-167I
GS8662Q08GE-278
GS8662Q08GE-250
GS8662Q08GE-200
GS8662Q08GE-167
GS662Q08GE-278I
GS8662Q08GE-250I
GS8662Q08GE-200I
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
SigmaQuad-II SRAM
165-bump BGA
167
278
250
200
167
278
250
200
167
278
250
200
167
278
250
200
167
278
250
200
167
278
250
200
167
278
250
200
167
278
250
200
I
C
C
C
C
I
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
oHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
I
I
I
C
C
C
C
I
I
I
I
C
C
C
C
I
I
I
I
C
C
C
C
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8662x36E-200T.
2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
Rev: 1.09a 11/2011
33/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662Q08/09/18/36E-278/250/200/167
Ordering Information—GSI SigmaQuad-II SRAM
Speed
(MHz)
3
1
Org
Type
SigmaQuad-II SRAM
Package
T
Part Number
A
8M x 8
GS8662Q08GE-167I
RoHS-compliant 165-bump BGA
167
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8662x36E-200T.
2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
SigmaQuad-II Revision History
File Name
8662Qxx_r1
Format/Content
Description of changes
Creation of datasheet
8662Qxx_r1; 8662Qxx_r1_01
8662Qxx_r1_01; 8662Qxx_r1_02
Content
Content
Added RoHS-compliant package information
Updated MAX tKHKH
• Updated tKHKH, tKHCH in AC Char table
• Added HKH and CQ Phase Distortion to AC Char table
8662Qxx_r1_02; 8662Qxx_r1_03
8662Qxx_r1_03; 8662Qxx_r1_04
8662Qxx_r1_05
Content
Content
Content
• Added CZ data
• Updated I/O supply voltage data
• Updated power-up sequence information
• Removed 300 MHz (Q)
• Updated to PQ
• Removed status from ordering information
• Added 278 MHz (Q)
8662Qxx_r1_06
8662Qxx_r1_07
Content
Content
• Added V
note to Pin Description table
REF
8662Qxx_r1_08
Content
• Updated FLXDrive-II Output Driver Impedance Control section
• Removed Preliminary banner due to production status
• Updated AC Electrical Characteristics table
• Updated 165-BGA Mechanical drawing
• Revised Power-up Sequence and Truth Tables
• Removed Status column from Ordering Information table
• (Rev1.09a: Editorial updates)
8662Qxx_r1_09
Content
Rev: 1.09a 11/2011
34/34
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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