GS8662T36BD-300IT [GSI]
DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165;型号: | GS8662T36BD-300IT |
厂家: | GSI TECHNOLOGY |
描述: | DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165 时钟 双倍数据速率 静态存储器 内存集成电路 |
文件: | 总35页 (文件大小:1299K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
GS8662T08/09/18/36BD-400/350/333/300/250
400 MHz–250 MHz
165-Bump BGA
Commercial Temp
Industrial Temp
72Mb SigmaDDR-IITM
Burst of 2 SRAM
1.8 V V
DD
1.8 V and 1.5 V I/O
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Features
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36, x18 and x9) and Nybble Write (x8) function
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
Each internal read and write operation in a SigmaDDR-II B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed.
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb
devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
When a new address is loaded into a x18 or x36 version of the
part, A0 is used to initialize the pointers that control the data
multiplexer / de-multiplexer so the RAM can perform "critical
word first" operations. From an external address point of view,
regardless of the starting point, the data transfers always follow
the same sequence {0, 1} or {1, 0} (where the digits shown
represent A0).
SigmaDDR™ Family Overview
The GS8662T08/09/18/36BD are built in compliance with the
SigmaDDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662T08/09/18/36BD SigmaDDR-II SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Unlike the x18 and x36 versions, the input and output data
multiplexers of the x8 and x9 versions are not preset by
address inputs and therefore do not allow "critical word first"
operations. The address fields of the x8 and x9 SigmaDDR-II
B2 RAMs are one address pin less than the advertised index
depth (e.g., the 8M x 8 has an 4M addressable index, and A0 is
not an accessible address pin).
Clocking and Addressing Schemes
The GS8662T08/09/18/36BD SigmaDDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
Parameter Synopsis
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
tKHKH
tKHQV
Rev: 1.02c 12/2011
1/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
2M x 36 SigmaDDR-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
NC/SA
(144Mb)
A
B
CQ
SA
R/W
BW2
K
BW1
LD
SA
SA
CQ
NC/SA
(288Mb)
NC
DQ27
DQ18
SA
BW3
SA
K
BW0
SA
SA
NC
DQ8
C
D
E
F
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
DQ28
DQ19
DQ20
DQ21
DQ22
V
V
SA0
V
NC
NC
NC
NC
NC
DQ17
NC
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
SS
SS
SS
SS
DQ29
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
DQ15
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DQ30
DQ31
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
V
V
V
NC
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
NC
NC
NC
NC
NC
NC
SA
DQ13
DQ12
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
K
L
V
DQ33
NC
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
DQ11
NC
SS
SS
SS
SS
DQ35
NC
V
SA
SA
SA
SA
C
SA
SA
SA
V
SA
SA
SA
SA
DQ9
TMS
TCK
C
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to
DQ27:DQ35.
2. A2 and B9 are the expansion addresses.
Rev: 1.02c 12/2011
2/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
4M x 18 SigmaDDR-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
NC/SA
(144Mb)
A
B
CQ
SA
SA
R/W
BW1
K
LD
SA
SA
CQ
NC/SA
(288Mb)
NC
DQ9
NC
SA
K
BW0
SA
SA
NC
NC
DQ8
C
D
E
F
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
NC
V
V
SA
SA0
V
NC
NC
NC
NC
NC
DQ7
NC
NC
NC
NC
NC
NC
SS
SS
SS
SS
DQ10
DQ11
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
NC
V
V
V
V
V
V
V
V
DQ6
DQ5
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DQ12
NC
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
DQ13
V
V
V
V
V
V
V
REF
ZQ
REF
DDQ
DDQ
NC
NC
NC
DQ14
NC
NC
DQ4
NC
NC
K
L
V
NC
NC
NC
NC
NC
SA
DQ3
DQ2
NC
DQ15
NC
V
V
V
V
V
NC
DDQ
SS
SS
SS
SS
M
N
P
R
NC
V
V
DQ1
NC
SS
SS
SS
SS
NC
DQ16
DQ17
SA
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
NC
SA
SA
SA
SA
NC
DQ0
TDI
TCK
C
TMS
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17.
2. A7 and B5 are the expansion addresses.
Rev: 1.02c 12/2011
3/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
8M x 9 SigmaDDR-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
NC/SA
(144Mb)
A
B
CQ
SA
SA
R/W
NC
K
LD
SA
SA
CQ
NC/SA
(288Mb)
NC
NC
NC
SA
K
BW0
SA
SA
NC
NC
DQ4
C
D
E
F
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
NC
NC
NC
NC
NC
V
V
SA
SA
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SS
SS
SS
SS
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DQ5
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQ3
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
DQ6
V
V
V
NC
V
V
V
V
ZQ
REF
DDQ
DDQ
REF
NC
NC
NC
NC
NC
NC
DQ8
SA
NC
DQ2
NC
K
L
NC
DQ7
NC
V
NC
NC
NC
NC
NC
SA
NC
NC
NC
V
V
V
V
V
DQ1
NC
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
NC
SS
SS
SS
SS
NC
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
NC
NC
SA
SA
SA
SA
NC
DQ0
TDI
TCK
C
TMS
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0. SA0 is set to 0 at the beginning
of each access.
2. BW0 controls writes to DQ0:DQ8.
3. A7 and B5 are the expansion addresses.
Rev: 1.02c 12/2011
4/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
8M x 8 SigmaDDR-II SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
NC/SA
(144Mb)
A
B
CQ
SA
SA
R/W
NW1
K
LD
SA
SA
CQ
NC/SA
(288Mb)
NC
NC
NC
SA
K
NW0
SA
SA
NC
NC
DQ3
C
D
E
F
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
NC
NC
NC
NC
NC
V
V
SA
SA
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ2
NC
NC
ZQ
SS
SS
SS
SS
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DQ4
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
DQ5
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
NC
NC
NC
NC
DQ7
SA
NC
DQ1
NC
NC
DQ0
NC
NC
NC
TDI
K
L
NC
DQ6
NC
V
NC
NC
NC
NC
NC
SA
NC
NC
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
NC
SS
SS
SS
SS
NC
V
SA
SA
SA
SA
C
SA
SA
SA
V
NC
NC
SA
SA
SA
SA
NC
TCK
C
TMS
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0. SA0 is set to 0 at the beginning
of each access.
2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7.
3. A7 and B5 are the expansion addresses.
Rev: 1.02c 12/2011
5/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Pin Description Table
Symbol
SA
Description
Synchronous Address Inputs
No Connect
Type
Input
—
Comments
—
—
NC
Read: Active High
Write: Active Low
R/W
Synchronous Read/Write
Synchronous Byte Writes
Nybble Write Control Pin
Input
Input
Input
Active Low
x18/x36 only
BW0–BW3
NW0–NW1
Active Low
x8 only
LD
K
Synchronous Load Pin
Input Clock
Input
Input
Active Low
Active High
K
Input Clock
Input
Active Low
C
Output Clock
Input
Active High
C
Output Clock
Input
Active Low
TMS
TDI
TCK
TDO
VREF
Test Mode Select
Test Data Input
Input
—
Input
—
Test Clock Input
Input
—
Test Data Output
HSTL Input Reference Voltage
Output Impedance Matching Input
Must Connect Low
Data I/O
Output
Input
—
—
ZQ
MCL
DQ
Input
—
—
—
Input/Output
Input
Three State
Active Low
—
Disable DLL when low
Output Echo Clock
Output Echo Clock
Power Supply
Doff
CQ
Output
Output
Supply
CQ
—
VDD
1.8 V Nominal
VDDQ
VSS
Isolated Output Buffer Supply
Power Supply: Ground
Supply
Supply
1.8 V or 1.5 V Nominal
—
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to V , output impedance is set to minimum value and it cannot be connected to ground or left
DDQ
unconnected.
3. C, C, K, K cannot be set to V
voltage.
REF
Rev: 1.02c 12/2011
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Background
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaDDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are
unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed
Common I/O SRAM data bandwidth in half.
Burst Operations
Read and write operations are "burst" operations. In every case where a read or write command is accepted by the SRAM, it will
respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in
the timing diagrams. This means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often,
if intervening deselect cycles are inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to
the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer
and then execute the deselect command, returning the output drivers to high-Z. A high on the LD pin prevents the RAM from
loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer
operations.
SigmaDDR-II B2 SRAM Read Cycles
The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read
command (LD low and R/W high) is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM
produces data out in response to the next rising edge of C (or the next rising edge of K, if C and C are tied high). The second beat
of data is transferred on the next rising edge of C, for a total of two transfers per address load.
SigmaDDR-II B2 SRAM Write Cycles
The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers.
Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command
(LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures
data in on the next rising edge of K, for a total of two transfers per address load.
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) write control is implemented on the 8-bit-wide version of the device. For the x8 version of the device,
“Nybble Write Enable” and “NBx” may be substituted in all the discussion above.
Rev: 1.02c 12/2011
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
D0–D8
Data In
D9–D17
Don’t Care
Data In
Beat 1
Beat 2
0
1
1
0
Don’t Care
Resulting Write Operation
Byte 1
D0–D8
Byte 2
D9–D17
Byte 3
D0–D8
Byte 4
D9–D17
Written
Unchanged
Unchanged
Written
Beat 1
Beat 2
Output Register Control
SigmaDDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaDDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
V
via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
SS
5X the value of the desired RAM output impedance at mid-rail. The allowable range of RQ to guarantee impedance matching
continuously is between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is
affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply
voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each
impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output
drivers implemented with discrete binary weighted impedance steps is implemented with discrete binary weighted impedance
steps.
Rev: 1.02c 12/2011
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Example Four Bank Depth Expansion Schematic
LD
LD
3
2
LD
LD
1
0
R/W
A –A
0
n
K
Bank 3
Bank 1
Bank 2
Bank 0
A
A
A
A
LD
LD
LD
LD
R/W
R/W
R/W
R/W
CQ
K
CQ
K
CQ
K
CQ
DQ
K
DQ
C
DQ
C
DQ
C
C
C
DQ1–DQn
CQ
Note:
For simplicity BWn (or NWn), K, and C are not shown.
Rev: 1.02c 12/2011
9/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Common I/O SigmaDDR-II B2 SRAM Truth Table
DQ
K
LD
R/W
Operation
n
A + 0
Hi-Z
A + 1
1
0
X
0
Hi-Z
Deselect
Write
↑
D@Kn+1
Q@Kn+1
D@Kn+1
Q@Kn+2
↑
↑
0
1
or
Cn+1
or
Cn+2
Read
Note:
Q is controlled by K clocks if C clocks are not used.
Burst of 2 Byte Write Clock Truth Table
BW
BW
Current Operation
D
D
K ↑
n + 1
K ↑
n + 1½
K ↑
n
K ↑
n + 1
K ↑
n + 1½
(t
)
(t
)
(t )
(t
)
(t
)
Write
T
T
F
T
F
D1
D2
X
Dx stored if BWn = 0 in both data transfers
Write
T
F
F
D1
X
Dx stored if BWn = 0 in 1st data transfer only
Write
D2
X
Dx stored if BWn = 0 in 2nd data transfer only
Write Abort
No Dx stored in either data transfer
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
Rev: 1.02c 12/2011
10/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Burst of 2 Nybble Write Clock Truth Table
NW
NW
Current Operation
D
D
K ↑
n + 1
K ↑
n + 1½
K ↑
n
K ↑
n + 1
K ↑
n + 1½
(t
)
(t
)
(t )
(t
)
(t
)
Write
T
T
F
T
F
D1
D2
X
Dx stored if NWn = 0 in both data transfers
Write
T
F
F
D1
X
Dx stored if NWn = 0 in 1st data transfer only
Write
D2
X
Dx stored if NWn = 0 in 2nd data transfer only
Write Abort
No Dx stored in either data transfer
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
Rev: 1.02c 12/2011
11/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
x36 Byte Write Enable (BWn) Truth Table
BW0
BW1
BW2
BW3
D0–D8
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
D18–D26
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
D27–D35
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Don’t Care
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Data In
Data In
Data In
Data In
Data In
Data In
x18 Byte Write Enable (BWn) Truth Table
BW0
BW1
D0–D8
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
1
0
1
0
1
1
0
0
Don’t Care
Data In
Data In
x8 Nybble Write Enable (NWn) Truth Table
NW0
NW1
D0–D3
Don’t Care
Data In
D4–D7
Don’t Care
Don’t Care
Data In
1
0
1
0
1
1
0
0
Don’t Care
Data In
Data In
Rev: 1.02c 12/2011
12/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
VDD
Description
Value
–0.5 to 2.9
Unit
Voltage on VDD Pins
Voltage in VDDQ Pins
Voltage in VREF Pins
V
VDDQ
VREF
VI/O
–0.5 to VDD
V
V
–0.5 to VDDQ
–0.5 to VDDQ +0.5 (≤ 2.9 V max.)
–0.5 to VDDQ +0.5 (≤ 2.9 V max.)
Voltage on I/O Pins
V
VIN
Voltage on Other Input Pins
Input Current on Any Pin
V
IIN
+/–100
+/–100
125
mA dc
mA dc
IOUT
Output Current on Any I/O Pin
Maximum Junction Temperature
Storage Temperature
oC
oC
TJ
TSTG
–55 to 125
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Supply Voltage
Symbol
VDD
Min.
1.7
Typ.
1.8
—
Max.
1.9
Unit
V
VDDQ
VREF
VDD
I/O Supply Voltage
Reference Voltage
1.4
V
0.68
—
0.95
V
Note:
The power supplies need to be powered up simultaneously or in the following sequence: V , V , V , followed by signal inputs. The power
DD DDQ REF
down sequence must be the reverse. V
must not exceed V . For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.
DD
DDQ
Operating Temperature
Parameter
Symbol
Min.
Typ.
Max.
Unit
Junction Temperature
(Commercial Range Versions)
TJ
0
25
85
°C
Junction Temperature
(Industrial Range Versions)*
TJ
–40
25
100
°C
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Rev: 1.02c 12/2011
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Thermal Impedance
Test PCB
Substrate
θ JA (C°/W)
Airflow = 0 m/s
θ JA (C°/W)
Airflow = 1 m/s
θ JA (C°/W)
Airflow = 2 m/s
θ JB (C°/W)
θ JC (C°/W)
Package
165 BGA
4-layer
22.300
18.572
17.349
9.292
2.310
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
HSTL I/O DC Input Characteristics
Parameter
Symbol
VIH (dc)
VIL (dc)
Min
Max
Units
Notes
VREF + 0.10
VDDQ + 0.3 V
VREF – 0.10
V
V
1
1
DC Input Logic High
DC Input Logic Low
–0.3 V
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers
2. These are DC test criteria. DC design criteria is V
± 50 mV. The AC V /V levels are defined separately for measuring timing parame-
REF
IH IL
ters.
3. V (Min) DC = –0.3 V, V (Min) AC = –1.5 V (pulse width ≤ 3 ns).
IL
IL
4.
V
(Max) DC = V
+ 0.3 V, V (Max) AC = V
+ 0.85 V (pulse width ≤ 3 ns).
IH
DDQ
IH
DDQ
HSTL I/O AC Input Characteristics
Parameter
AC Input Logic High
Symbol
VIH (ac)
VIL (ac)
Min
Max
—
Units
Notes
2,3
VREF + 0.20
V
V
V
VREF – 0.20
5% VREF (DC)
—
—
2,3
AC Input Logic Low
V
Peak-to-Peak AC Voltage
VREF (ac)
1
REF
Notes:
1. The peak-to-peak AC component superimposed on V
may not exceed 5% of the DC component of V
.
REF
REF
2. To guarantee AC characteristics, V ,V , Trise, and Tfall of inputs and clocks must be within 10% of each other.
IH IL
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Rev: 1.02c 12/2011
14/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKHKH
V
+ 1.0 V
50%
DD
V
SS
50%
V
DD
V
– 1.0 V
SS
20% tKHKH
V
IL
Note:
Input Undershoot/Overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 1.8 V)
A
DD
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
Typ.
Max.
Unit
pF
Input Capacitance
Output Capacitance
Clock Capacitance
4
6
5
5
7
6
COUT
CCLK
VOUT = 0 V
pF
—
pF
Note:
This parameter is sample tested.
AC Test Conditions
Parameter
Input high level
Input low level
Conditions
VDDQ
0 V
Max. input slew rate
Input reference level
Output reference level
2 V/ns
VDDQ/2
VDDQ/2
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
AC Test Load Diagram
DQ
RQ = 250 Ω (HSTL I/O)
= 0.75 V
V
REF
50Ω
VT = V /2
DDQ
Rev: 1.02c 12/2011
15/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Input and Output Leakage Characteristics
Parameter
Symbol
Test Conditions
VIN = 0 to VDD
Min.
–2 uA
–20 uA
–2 uA
Max
2 uA
2 uA
2 uA
Input Leakage Current
(except mode pins)
IIL
IILDOFF
IOL
VIN = 0 to VDD
Doff
Output Disable,
VOUT = 0 to VDDQ
Output Leakage Current
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter
Symbol
VOH1
Min.
Max.
Units
Notes
1, 3
VDDQ/2 – 0.12 VDDQ/2 + 0.12
VDDQ/2 – 0.12 VDDQ/2 + 0.12
Output High Voltage
Output Low Voltage
Output High Voltage
V
V
V
V
VOL1
2, 3
VOH2
VDDQ – 0.2
Vss
VDDQ
0.2
4, 5
VOL2
4, 6
Output Low Voltage
Notes:
1.
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).
DDQ OH DDQ
OH
2.
I
= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175Ω ≤ RQ ≤ 350Ω).
OL
DDQ
OL
DDQ
3. Parameter tested with RQ = 250Ω and V
4. 0Ω ≤ RQ ≤ ∞Ω
= 1.5 V or 1.8 V
DDQ
5.
I
= –1.0 mA
OH
6.
I
= 1.0 mA
OL
Rev: 1.02c 12/2011
16/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Operating Currents
-400
-350
-333
-300
-250
Parameter
Symbol
Test Conditions
Notes
0
to
–40
to
0
to
–40
to
0
to
–40
to
0
to
–40
to
0
to
–40
to
70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C
VDD = Max, IOUT = 0 mA
Operating Current (x36):
DDR
800
mA
810
mA
755
mA
765
mA
685
mA
695
mA
625
mA
635
mA
620
mA
630
mA
IDD
IDD
IDD
IDD
2, 3
2, 3
2, 3
2, 3
Cycle Time ≥ tKHKH Min
VDD = Max, IOUT = 0 mA
Operating Current (x18):
DDR
625
mA
635
mA
590
mA
600
mA
535
mA
545
mA
495
mA
505
mA
425
mA
435
mA
Cycle Time ≥ tKHKH Min
VDD = Max, IOUT = 0 mA
Operating Current (x9):
DDR
625
mA
635
mA
590
mA
600
mA
535
mA
545
mA
495
mA
505
mA
425
mA
435
mA
Cycle Time ≥ tKHKH Min
VDD = Max, IOUT = 0 mA
Operating Current (x8):
DDR
625
mA
635
mA
590
mA
600
mA
535
mA
545
mA
495
mA
505
mA
425
mA
435
mA
Cycle Time ≥ tKHKH Min
Device deselected,
IOUT = 0 mA, f = Max,
Standby Current (NOP):
DDR
245
mA
255
mA
240
mA
250
mA
230
mA
240
mA
220
mA
230
mA
205
mA
215
mA
ISB1
2, 4
All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V
Notes:
1.
2.
Power measured with output pins floating.
Minimum cycle, IOUT = 0 mA
Operating current is calculated with 50% read cycles and 50% write cycles.
Standby Current is only after all pending read and write burst operations are completed.
3.
4.
Rev: 1.02c 12/2011
17/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
AC Electrical Characteristics
-400
-350
-333
-300
-250
Parameter
Symbol
Units
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Clock
tKHKH
tCHCH
K, K Clock Cycle Time
C, C Clock Cycle Time
2.5
—
8.4
0.2
—
2.86
—
8.4
0.2
—
3.0
—
8.4
0.2
—
3.3
—
8.4
0.2
—
4.0
—
8.4
0.2
—
ns
ns
ns
tKCVar
tKC Variable
6
tKHKL
tCHCL
K, K Clock High Pulse Width
C, C Clock High Pulse Width
1.0
1.13
1.2
1.32
1.6
tKLKH
tCLCH
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
1.0
1.0
1.0
—
—
—
1.13
1.13
1.13
—
—
—
1.2
—
—
—
1.32
1.49
1.49
—
—
—
1.6
1.8
1.8
—
—
—
ns
ns
ns
tKHKH
tCHCH
K to K High
C to C High
1.35
1.35
tKHKH
tCHCH
K to K High
C to C High
tKHCH
tKCLock
tKCReset
K, K Clock High to C, C Clock High
DLL Lock Time
0
1.13
—
0
1.29
—
0
1.35
—
0
1.49
—
0
1.8
—
ns
cycle
ns
1024
30
1024
30
1024
30
1024
30
1024
30
7
K Static to DLL reset
—
—
—
—
—
Output Times
tKHQV
tCHQV
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
—
0.45
—
—
0.45
—
—
0.45
—
—
0.45
—
—
0.45
—
ns
ns
ns
ns
4
4
tKHQX
tCHQX
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
tKHCQV
tCHCQV
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
tKHCQX
tCHCQX
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
–0.45
–0.45
–0.45
–0.45
–0.45
tCQHQV
tCQHQX
tCQHCQH
tCQHCQH
tKHQZ
tCHQZ
tKHQX1
tCHQX1
CQ, CQ High Output Valid
CQ, CQ High Output Hold
—
0.20
—
—
0.23
—
—
0.25
—
—
0.27
—
—
0.30
—
ns
ns
8
8
–0.20
–0.23
–0.25
–0.27
–0.30
CQ Phase Distortion
0.9
—
—
0.45
—
1.0
—
—
0.45
—
1.10
—
—
0.45
—
1.24
—
—
0.45
—
1.55
—
—
0.45
—
ns
ns
ns
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
4
4
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
–0.45
–0.45
–0.45
–0.45
–0.45
Setup Times
tAVKH
tIVKH
Address Input Setup Time
0.4
0.4
—
—
0.4
0.4
—
—
0.4
0.4
—
—
0.4
0.4
—
—
0.5
0.5
—
—
ns
ns
1
2
Control Input Setup Time(R/ W) (LD)
Control Input Setup Time
(BWX) (NWX)
tIVKH
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
0.3
0.3
—
—
0.35
0.35
—
—
ns
ns
3
tDVKH
Data Input Setup Time
Rev: 1.02c 12/2011
18/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
AC Electrical Characteristics (Continued)
-400
-350
-333
-300
-250
Parameter
Symbol
Units
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Hold Times
tKHAX
tKHIX
Address Input Hold Time
0.4
0.4
—
—
0.4
0.4
—
—
0.4
0.4
—
—
0.4
0.4
—
—
0.5
0.5
—
—
ns
ns
1
2
Control Input Hold Time (R/ W) (LD)
Control Input Hold Time
(BWX) (NWX)
tKHIX
0.28
0.28
—
—
0.28
0.28
—
—
0.28
0.28
—
—
0.3
0.3
—
—
0.35
0.35
—
—
ns
ns
3
tKHDX
Data Input Hold Time
Notes:
1.
2.
3.
4.
5.
All Address inputs must meet the specified setup and hold times for all latching clock edges.
Control signals are R/ W, LD.
Control signals are BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).
If C, C are tied high, K, K become the references for C, C timing parameters
To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN
parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs
on the same board to be at such different voltages and temperatures.
6.
7.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
8.
Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands
and test setup variations.
Rev: 1.02c 12/2011
19/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Rev: 1.02c 12/2011
20/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Rev: 1.02c 12/2011
21/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Rev: 1.02c 12/2011
22/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Rev: 1.02c 12/2011
23/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DD
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 1.02c 12/2011
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
·
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1
0
·
· · ·
Control Signals
Test Access Port (TAP) Controller
TMS
TCK
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.02c 12/2011
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
ID Register Contents
GSI Technology
JEDEC Vendor
ID Code
See BSDL Model
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0 1 1 0 1 1 0 0 1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
1
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.
SAMPLE-Z
010
1
GSI
011
100
101
110
111
GSI private instruction.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
GSI private instruction.
1
1
1
1
1
SAMPLE/PRELOAD
GSI
GSI
GSI private instruction.
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.02c 12/2011
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
–0.3
Max.
Unit Notes
V
0.3 * V
Test Port Input Low Voltage
V
V
1
1
ILJ
DD
V
0.7 * V
V
+0.3
DD
Test Port Input High Voltage
IHJ
DD
I
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
–300
–1
1
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
V
V
– 0.2
DD
—
0.2
—
0.1
5, 6
5, 7
5, 8
5, 9
OHJ
V
—
V
OLJ
V
– 0.1
DD
V
OHJC
V
—
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < V
+1 V not to exceed V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
ILJn
3. 0 V ≤ V ≤ V
IN
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V supply.
DD
6.
7.
8.
9.
I
I
I
I
= –2 mA
OHJ
= + 2 mA
OLJ
= –100 uA
= +100 uA
OHJC
OLJC
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
TDO
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
*
50Ω
30pF
Input slew rate
V
/2
DD
V
V
/2
Input reference level
DD
* Distributed Test Jig Capacitance
/2
Output reference level
DD
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.02c 12/2011
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
TDI
tTH
tTH
tTS
tTS
TMS
TDO
tTKQ
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
Max
—
Unit
TCK Cycle Time
50
—
ns
ns
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
20
20
10
10
—
—
tTH
—
Rev: 1.02c 12/2011
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Package Dimensions—165-Bump FPBGA (Package D)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.60 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
1.0
13±0.05
B
0.20(4x)
SEATING PLANE
C
Rev: 1.02c 12/2011
31/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Ordering Information—GSI SigmaDDR-II SRAM
2
Org
Part Number1
Type
Package
Speed (MHz)
T
J
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
2M x 36
2M x 36
GS8662T08BD-400
GS8662T08BD-350
GS8662T08BD-333
GS8662T08BD-300
GS8662T08BD-250
GS8662T08BD-400I
GS8662T08BD-350I
GS8662T08BD-333I
GS8662T08BD-300I
GS8662T08BD-250I
GS8662T09BD-400
GS8662T09BD-350
GS8662T09BD-333
GS8662T09BD-300
GS8662T09BD-250
GS8662T09BD-400I
GS8662T09BD-350I
GS8662T09BD-333I
GS8662T09BD-300I
GS8662T09BD-250I
GS8662T18BD-400
GS8662T18BD-350
GS8662T18BD-333
GS8662T18BD-300
GS8662T18BD-250
GS8662T18BD-400I
GS8662T18BD-350I
GS8662T18BD-333I
GS8662T18BD-300I
GS8662T18BD-250I
GS8662T36BD-400
GS8662T36BD-350
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
400
350
333
300
250
400
350
333
300
250
400
350
333
300
250
400
350
333
300
250
400
350
333
300
250
400
350
333
300
250
400
350
C
C
C
C
C
I
I
I
I
I
C
C
C
C
C
I
I
I
I
I
C
C
C
C
C
I
I
I
I
I
C
C
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8662Tx36BD-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.02c 12/2011
32/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Ordering Information—GSI SigmaDDR-II SRAM
2
Org
Part Number1
Type
Package
Speed (MHz)
T
J
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 8
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
8M x 9
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
GS8662T36BD-333
GS8662T36BD-300
GS8662T36BD-250
GS8662T36BD-400I
GS8662T36BD-350I
GS8662T36BD-333I
GS8662T36BD-300I
GS8662T36BD-250I
GS8662T08BGD-400
GS8662T08BGD-350
GS8662T08BGD-333
GS8662T08BGD-300
GS8662T08BGD-250
GS8662T08BGD-400I
GS8662T08BGD-350I
GS8662T08BGD-333I
GS8662T08BGD-300I
GS8662T08BGD-250I
GS8662T09BGD-400
GS8662T09BGD-350
GS8662T09BGD-333
GS8662T09BGD-300
GS8662T09BGD-250
GS8662T09BGD-400I
GS8662T09BGD-350I
GS8662T09BGD-333I
GS8662T09BGD-300I
GS8662T09BGD-250I
GS8662T18BGD-400
GS8662T18BGD-350
GS8662T18BGD-333
GS8662T18BGD-300
GS8662T18BGD-250
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
165-bump BGA
333
300
250
400
350
333
300
250
400
350
333
300
250
400
350
333
300
250
400
350
333
300
250
400
350
333
300
250
400
350
333
300
250
C
C
C
I
165-bump BGA
165-bump BGA
165-bump BGA
165-bump BGA
I
165-bump BGA
I
165-bump BGA
I
165-bump BGA
I
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
C
C
C
C
C
I
I
I
I
I
C
C
C
C
C
I
I
I
I
I
C
C
C
C
C
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8662Tx36BD-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.02c 12/2011
33/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Ordering Information—GSI SigmaDDR-II SRAM
2
Org
Part Number1
Type
Package
Speed (MHz)
T
J
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
2M x 36
GS8662T18BGD-400I
GS8662T18BGD-350I
GS8662T18BGD-333I
GS8662T18BGD-300I
GS8662T18BGD-250I
GS8662T36BGD-400
GS8662T36BGD-350
GS8662T36BGD-333
GS8662T36BGD-300
GS8662T36BGD-250
GS8662T36BGD-400I
GS8662T36BGD-350I
GS8662T36BGD-333I
GS8662T36BGD-300I
GS8662T36BGD-250I
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
SigmaDDR-II B2 SRAM
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
RoHS-compliant 165-bump BGA
400
350
333
300
250
400
350
333
300
250
400
350
333
300
250
I
I
I
I
I
C
C
C
C
C
I
I
I
I
I
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8662Tx36BD-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.02c 12/2011
34/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8662T08/09/18/36BD-400/350/333/300/250
Revision History
Types of Changes
Format or Content
File Name
Revisions
• Creation of new datasheet
• (Rev1.00a: Updated DLL Lock time to 2048 cycles)
GS8662TxxB_r1
Format
• Removal of 200 MHz and 167 MHz speed bins
• Addition of 400 MHz and 350 MHz speed bins
GS8662TxxB_r1_01
Content
• (Rev1.01a: Removed T references)
A
• Update to MP status
• (Rev1.02a: Removed Power-up section and added AN1021 link
to Power Supplies table)
GS8662TxxB_r1_02
Content
• (Rev1.02b: Editorial updates)
• (Rev1.02c: Updated DLL lock time in AC Char table)
Rev: 1.02c 12/2011
35/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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