GS8672T20_技术文档

GS8672T20/38BE-633/550/500/450/400

633 MHz–400 MHz

72Mb SigmaDDR-II+^TM

Burst of 2 ECCRAM^TM

165-Bump BGA

Commercial Temp

Industrial Temp

1.8 V V

DD

1.5 V I/O

Features

Clocking and Addressing Schemes

• 2.5 Clock Latency

The GS8672T20/38BE SigmaDDR-II+ SRAMs are

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

• JEDEC-standard package

• Double Data Rate interface

• Byte Write capability

• Burst of 2 Read and Write

• On-Die Termination (ODT) on Data (DQ), Byte Write (BW),

and Clock (K, K) outputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with 36Mb and 144Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Each internal read and write operation in a SigmaDDR-II+ B2

ECCRAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaDDR-II+ B2 ECCRAM is always one address

pin less than the advertised index depth (e.g., the 4M x 18 has

an 2M addressable index).

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles etc. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

SigmaDDR™ ECCRAM Overview

The GS8672T20/38BE SigmaDDR-II+ ECCRAMs are built in

compliance with the SigmaDDR-II+ SRAM pinout standard

for Common I/O synchronous SRAMs. They are 

75,497,472-bit (72Mb) SRAMs. The GS8672T20/38BE

SigmaDDR SRAMs are just one element in a family of low

power, low voltage HSTL I/O SRAMs designed to operate at

the speeds needed to implement economical high performance

networking systems.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the Byte

Write Contol section for further information.

Parameter Synopsis

-633

-550

1.81 ns

0.45 ns

-500

2.0 ns

0.45 ns

-450

2.2 ns

0.45 ns

-400

2.5 ns

0.45 ns

tKHKH

tKHQV

1.57 ns

0.45 ns

Rev: 1.02a 6/2013

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

2M x 36 SigmaDDR-II+ SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

NF

(144Mb)

A

CQ

SA

R/W

BW2

K

BW1

LD

SA

CQ

B

C

D

E

F

NC

Doff

NC

TDO

DQ27

NC

DQ18

DQ28

DQ19

DQ20

DQ21

DQ22

SA

BW3

SA

K

BW0

SA

NC

DQ17

NC

DQ8

DQ7

DQ16

DQ6

DQ5

DQ14

ZQ

V

NF

V

SS

DQ29

NC

V

SS

DD

SS

DD

V

DQ15

NC

DDQ

DQ30

DQ31

V

DDQ

G

H

J

V

NC

V

REF

DDQ

NC

DQ32

DQ23

DQ24

DQ34

DQ25

DQ26

SA

NC

DQ13

DQ12

NC

DQ4

DQ3

DQ2

DQ1

DQ10

DQ0

TDI

K

L

V

NC

SA

DQ33

NC

V

DDQ

SS

M

N

P

R

V

DQ11

NC

SS

DQ35

NC

V

SA

V

SA

QVLD

ODT

SA

DQ9

TMS

TCK

2

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Note:

BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to DQ27:DQ35

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

4M x 18 SigmaDDR-II+ SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

CQ

SA

R/W

BW1

K

NF

LD

SA

CQ

NC

Doff

NC

TDO

DQ9

NC

NF

SA

NF

SA

K

BW0

SA

NC

DQ7

NC

NF

DQ8

NF

V

NF

V

SS

NF

DQ10

DQ11

NF

V

NF

SS

DD

SS

DD

NC

V

DQ6

DQ5

NF

DDQ

DQ12

NF

V

NC

DDQ

G

H

J

DQ13

V

REF

ZQ

REF

DDQ

NC

NF

DQ14

NF

NC

DQ4

NF

K

L

V

NC

SA

DQ3

DQ2

NF

DQ15

NC

V

NC

DDQ

SS

M

N

P

R

NF

V

DQ1

NC

SS

NF

DQ16

DQ17

SA

V

SA

V

NF

NC

SA

QVLD

ODT

SA

NF

DQ0

TDI

TCK

TMS

2

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Note:

BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

Pin Description Table

Description

Type

Comments

Symbol

Synchronous Address Inputs

Input

—

SA

High: Read

Low: Write

Synchronous Read/Write

Input

R/W

Synchronous Byte Writes

Synchronous Load Pin

Input Clock

Input

Output

Input

Active Low

BW0–BW3

LD

Active Low

Active High

K

Input Clock

Active Low

K

Test Mode Select

Test Data Input

—

TMS

TDI

Test Clock Input

TCK

TDO

V_REF

Test Data Output

HSTL Input Reference Voltage

Output Impedance Matching Input

Data I/O

Input

Input/Output

Input

—

Three State

Active Low

—

ZQ

DQ

Disable DLL when low

Output Echo Clock

Doff

CQ

Output

—

CQ

Power Supply

Supply

1.8 V Nominal

1.5 V Nominal

—

V_DD

Isolated Output Buffer Supply

Power Supply: Ground

V_DDQ

V_SS

Q Valid Output

On-Die Termination

No Connect

Output

Input

—

QVLD

ODT

NC

No Function

—

NF

Notes:

1. NC = Not Connected to die or any other pin

2. NF = No Function. There is an electrical connection to this input pin, but the signal has no function in the device. It can be left unconnected,

or tied to V or V

SS

DDQ.

3. K, or K cannot be set to V

voltage.

REF

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

Background

Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.

Therefore, the SigmaDDR-II+ ECCRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs

are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed

Common I/O SRAM data bandwidth in half.

Burst Operations

Read and write operations are burst operations. In every case where a read or write command is accepted by the ECCRAM, it will

respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in

the timing diagrams. This means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often,

if intervening deselect cycles are inserted.

Deselect Cycles

Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to

the ECCRAM on the next cycle after a read command captured by the ECCRAM, the device will complete the two beat read data

transfer and then execute the deselect command, returning the output drivers to High-Z. A high on the LD pin prevents the RAM

from loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst

transfer operations.

SigmaDDR-II+ B2 ECCRAM Read Cycles

The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read

command (LD low and R/W high) is clocked into the SRAM by a rising edge of K.

SigmaDDR-II+ B2 ECCRAM Write Cycles

The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The ECCRAM executes Late write data

transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write

command (LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the

ECCRAM captures data in on the next rising edge of K, for a total of two transfers per address load.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

Power-Up Sequence for SigmaDDR-II+ ECCRAMs

SigmaDDR-II+ ECCRAMs must be powered-up in a specific sequence in order to avoid undefined operations.

1. After power supplies power-up and clocks (K, K) are stablized, 163,840 cycles are required to set Output Driver

Impedance.

2. Thereafter, an additional 65,536 clock cycles are required to lock the DLL after it has been enabled.

3. Begin Read and Write operations.

For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.

On-Chip Error Correction

SigmaDDR-II ECCRAMs implement a single-bit error detection and correction algorithm (specifically, a Hamming Code) on each

DDR data word (comprising two 9-bit data bytes) transmitted on each 9-bit data bus (i.e., transmitted on D/Q[8:0], D/Q[17:9], D/

Q[26:18], or D/Q[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible to

the user).

The ECC algorithm neither corrects nor detects multi-bit errors. However, GSI ECCRAMs are architected in such a way that a

single SER event very rarely causes a multi-bit error across any given "transmitted data unit", where a "transmitted data unit"

represents the data transmitted as the result of a single read or write operation to a particular address. The extreme rarity of multi-

bit errors results in the SER mentioned previously (i.e., <0.002 FITs/Mb measured at sea level.)

Not only does the on-chip ECC significantly improve SER performance, but it also frees up the entire memory array for data

storage. Very often SRAM applications allocate 1/9th of the memory array (i.e., one "error bit" per eight "data bits", in any 9-bit

"data byte") for error detection (either simple parity error detection, or system-level ECC error detection and correction). Such

error-bit allocation is unnecessary with ECCRAMs the entire memory array can be utilized for data storage, effectively providing

12.5% greater storage capacity compared to SRAMs of the same density not equipped with on-chip ECC.

Rev: 1.02a 6/2013

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

Special Functions

Byte Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a -beat data transfer. The x18

version of the RAM, for example, may write bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

Note: If “Half Write” operations (i.e., write operations in which a BWn pin is asserted for only half of a DDR write data transfer

on the associated 9-bit data bus, causing only 9 bits of the 18-bit DDR data word to be written) are initiated, the on-chip ECC will

be disabled for as long as the SRAM remains powered up thereafter. This must be done because ECC is implemented across entire

18-bit data words, rather than across individual 9-bit data bytes.

Byte Write Truth Table

The truth table below applies to write operations to Address "m", where Address "m" is the 18-bit memory location comprising the

2 beats of DDR write data associated with each BWn pin in a given clock cycle.

BWn

Input Data Byte n

Operation

Result

K

K

(Beat 1)

(Beat 2)

(Beat 1)

(Beat 2)

0

1

0

1

0

1

D0

X

D1

X

Full Write

Half Write

Abort

D0 and D1 written to Address m

Only D0 written to Address m

Only D1 written to Address m

Address m unchanged

D1

X

Notes:

1. BW0 is associated with Input Data Byte D[8:0].

2. BW1 is associated with Input Data Byte D[17:9].

3. BW2 is associated with Input Data Byte D[26:18] (in x36 only).

4. BW3 is associated with Input Data Byte D[35:27] (in x36 only).

5. ECC is disabled if a “Half Write” operation is initiated.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

FLXDrive-II Output Driver Impedance Control

HSTL I/O SigmaDDR-II ECCRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to

VSS via an external resistor, RQ, to allow the ECCRAM to monitor and adjust its output driver impedance. The value of RQ must

be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously

is between 175 and 275. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by

drifts in supply voltage and temperature. The ECCRAM’s output impedance circuitry compensates for drifts in supply voltage and

temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance

evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is

implemented with discrete binary weighted impedance steps.

Input Termination Impedance Control

These SigmaDDR-II+ ECCRAMs are supplied with programmable input termination on Data (DQ), Byte Write (BW), and Clock

(K, K) input receivers. Input termination can be enabled or disabled via the ODT pin (6R). When the ODT pin is tied Low (or left

floating–the pin has a small pull-down resistor), input termination is disabled. When the ODT pin is tied High, input termination is

enabled. Termination impedance is programmed via the same RQ resistor (connected between the ZQ pin and V ) used to

SS

program output driver impedance, and is nominally RQ*0.6 Thevenin-equivalent when RQ is between 175 and 225. Periodic

readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same manner

as for driver impedance (see above).

Notes:

1. When ODT = 1, Byte Write (BW), and Clock (K, K) input termination is always enabled.Consequently, BW, K, K inputs

should always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are tri-stated, the

input termination will pull the signal to V

/2 (i.e., to the switch point of the diff-amp receiver), which could cause the

DDQ

receiver to enter a meta-stable state, resulting in the receiver consuming more power than it normally would. This could result

in the device’s operating currents being higher..

2. When ODT = 1, DQ input termination is enabled during Write and NOP operations, and disabled during Read operations.

Specifically, DQ input termination is disabled 0.5 cycles before the SRAM enables its DQ drivers and starts driving valid Read

Data, and remains disabled until 0.5 cycles after the SRAM stops driving valid Read Data and disables its DQ drivers; DQ

input termination is enabled at all other times. Consequently, the SRAM Controller should disable its DQ input termination,

enable its DQ drivers, and drive DQ inputs (High or Low) during Write and NOP operations. And, it should enable its DQ

input termination and disable its DQ drivers during Read operations. Care should be taken during Write or NOP -> Read

transitions, and during Read -> NOP transitions, to minimize the time during which one device (SRAM or SRAM Controller)

has enabled its DQ input termination while the other device has not yet enabled its DQ driver. Otherwise, the input termination

will pull the signal to V_DDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to enter a meta-

stable state, resulting in the receiver consuming more power than it normally would. This could result in the device’s operating

currents being higher..

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

Common I/O SigmaDDR-II+ ECCRAM Truth Table

DQ

K

LD

R/W

Operation

n

A + 0

Hi-Z / *

A + 1

Hi-Z / *

1

0

X

0

1

Deselect

Write



D@K_n+1

Q@K_n+2

D@K_n+1

Q@K_n+3



Read

Notes:

1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”.

2. When On-Die Termination is disabled (ODT = 0), DQ drivers are disabled (i.e., DQ pins are tri-stated) for one cycle in responseto NOP

and Write commands, 2.5 cycles after the command is sampled.

3. When On-Die Termination is enabled (ODT = 1), DQ drivers are disabled for one cycle in response to NOP and Write commands, 2.5

cycles after the command is sampled. The state of the DQ pins during that time (denoted by “*” in the table above) is determined by the

state of the DQ input termination. See the Input Termination Impedance Control section for more information.

Byte Write Clock Truth Table

BW

Current Operation

D

K 

(t

)

(t

)

(t )

(t

)

(t

)

n + 1

n + 1½

n

n + 1

n + 1½

Write

T

F

T

F

D1

D2

X

Dx stored if BWn = 0 in both data transfers

Write

T

F

D1

X

Dx stored if BWn = 0 in 1st data transfer only

Write

D2

X

Dx stored if BWn = 0 in 2nd data transfer only

Write Abort

No Dx stored in either data transfer

X

Notes:

1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

2. If one or more BWn = 0, then BW = “T”, else BW = “F”.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

x36 Byte Write Enable (BWn) Truth Table

BW0

BW1

BW2

BW3

D0–D8

Don’t Care

Data In

D9–D17

Don’t Care

Data In

D18–D26

Don’t Care

Data In

D27–D35

Don’t Care

Data In

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

Don’t Care

Data In

x18 Byte Write Enable (BWn) Truth Table

BW0

BW1

D0–D8

Don’t Care

Data In

D9–D17

Don’t Care

Data In

1

0

1

0

1

0

Don’t Care

Data In

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

V_DD

Description

Value

–0.5 to 2.4

Unit

Voltage on V_DDPins

Voltage in V_DDQPins

Voltage in V_REFPins

V

V_DDQ

V_REF

V_I/O

–0.5 to V_DD

V

–0.5 to V_DDQ

–0.5 to V_DDQ+0.5 ( 2.4 V max.)

Voltage on I/O Pins

V

V_IN

Voltage on Other Input Pins

Input Current on Any Pin

V

I_IN

+/–100

125

mA dc

I_OUT

Output Current on Any I/O Pin

Maximum Junction Temperature

Storage Temperature

^oC

T_J

T_STG

–55 to 125

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect

reliability of this component.

Recommended Operating Conditions

Power Supplies

Parameter

Supply Voltage

Symbol

V_DD

Min.

1.7

Typ.

1.8

—

Max.

1.9

Unit

V

V_DDQ

V_REF

I/O Supply Voltage

Reference Voltage

1.4

1.6

V

V_DDQ/2 – 0.05

V_DDQ/2 + 0.05

—

V

Note:.

The power supplies need to be powered up simultaneously or in the following sequence: V , V , V , followed by signal inputs. The power

DD DDQ REF

down sequence must be the reverse. V

must not exceed V . For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.

DD

DDQ

Operating Temperature

Parameter

Symbol

Min.

Typ.

Max.

Unit

Junction Temperature

(Commercial Range Versions)

T_J

0

25

85

C

Junction Temperature

(Industrial Range Versions)*

T_J

–40

25

100

C

Note:

* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications

quoted are evaluated for worst case in the temperature range marked on the device.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

Thermal Impedance

Test PCB

Substrate

JA (C°/W)

Airflow = 0 m/s

 JA (C°/W)

Airflow = 1 m/s

 JA (C°/W)

Airflow = 2 m/s

JB (C°/W)

 JC (C°/W)

Package

165 BGA

4-layer

15.25

12.38

11.41

4.79

1.31

Notes:

1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.

2. Please refer to JEDEC standard JESD51-6.

3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to

the PCB can result in cooling or heating of the RAM depending on PCB temperature.

HSTL I/O DC Input Characteristics

Parameter

Input Reference Voltage

Symbol

V_REF

V_IH1

Min

Max

Units

Notes

—

V_DDQ/2 – 0.05

V_REF+ 0.1

V_DDQ/2 + 0.05

V_DDQ+ 0.3

V_REF– 0.1

V_DDQ+ 0.3

0.3 * V_DDQ

V

Input High Voltage

Input Low Voltage

Input High Voltage

1

V_IL1

–0.3

1

V_IH2

0.7 * V_DDQ

2,3

V_IL2

–0.3

Input Low Voltage

Notes:

1. Parameters apply to K, K, SA, DQ, LD, R/W, BW during normal operation and JTAG boundary scan testing.

2. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing.

3. Parameters apply to ZQ during JTAG boundary scan testing only.

HSTL I/O AC Input Characteristics

Parameter

Input Reference Voltage

Symbol

V_REF

V_IH1

Min

Max

Units

Notes

—

V_DDQ/2 – 0.08

V_REF+ 0.2

V_DDQ/2 + 0.08

V_DDQ+ 0.5

V

1,2,3

4,5

Input High Voltage

Input Low Voltage

Input High Voltage

V_IL1

V_REF– 0.2

–0.5

V_IH2

V_DDQ– 0.2

V_DDQ+ 0.5

0.2

V_IL2

Input Low Voltage

–0.5

4,5

Notes:

1.

V

and V

apply for pulse widths less than one-quarter of the cycle time.

IL(MIN)

IH(MAX)

2. Input rise and fall times myust be a minimum of 1 V/ns, and within 10% of each other.

3. Parameters apply to K, K, SA, DQ, LD, R/W, BW during normal operation and JTAG boundary scan testing.

4. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing.

Rev: 1.02a 6/2013

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 1.8 V)

A

DD

Parameter

Symbol

C_IN

Test conditions

V_IN= 0 V

Typ.

4

Max.

5

Unit

pF

Input Capacitance

Output Capacitance

C_OUT

V_OUT= 0 V

4.5

5.5

pF

Note:

This parameter is sample tested.

AC Test Conditions

Parameter

Input high level

Input low level

Conditions

1.25

0 V

Max. input slew rate

Input reference level

Output reference level

2 V/ns

0.75

V_DDQ/2

Note:

Test conditions as specified with output loading as shown unless otherwise noted.

AC Test Load Diagram

DQ

RQ = 250 (HSTL I/O)

= 0.75 V

V

REF

50

VT = V /2

DDQ

Input and Output Leakage Characteristics

Parameter

Symbol

I_IL

Test Conditions

Min.

–2 uA

Max

Input Leakage Current

(except mode pins)

V_IN= 0 to V_DDQ

2 uA

I_ILDOFF

I_ILODT

V_IN= 0 to V_DDQ

Doff

–100 uA

–2 uA

2 uA

ODT

100 uA

Output Disable,

V_OUT= 0 to V_DDQ

I_OL

Output Leakage Current

–2 uA

2 uA

Rev: 1.02a 6/2013

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

HSTL I/O Output Driver DC Electrical Characteristics

Parameter

Output High Voltage

Symbol

V_OH1

Min.

Max.

Units

Notes

1

V_DDQ/2 – 0.12

V_DDQ– 0.2

V_DDQ/2 + 0.12

V

V_OL1

2

Output Low Voltage

V_OH2

—

0.2

V

3, 4

3, 5

6, 7

Output High Voltage

V_OL2

—

V

Output Low Voltage

R_OUT

(RQ/5) * 0.88

(RQ/5) * 1.12



Output Driver Impedance

Notes:

1.

I

= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175 RQ  275

DDQ OH DDQ

OH

2.

I

= (V /2) / (RQ/5) +/– 15% @ V = V /2 (for: 175  RQ  275.

OL

DDQ

OL

DDQ

3. 0RQ  

4.

I

= –1.0 mA

OH

5.

I

= 1.0 mA

OL

6. Parameter applies when 175  RQ  275

7. Tested at V = V * 0.2 and V * 0.8

OUT

DDQ

Rev: 1.02a 6/2013

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GS8672T20/38BE-633/550/500/450/400

Rev: 1.02a 6/2013

15/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

AC Electrical Characteristics

-633

-550

-500

-450

-400

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Clock

t_KHKH

t_KVar

K, K Clock Cycle Time

1.57

—

6.0

0.15

—

1.81

—

6.0

0.15

—

2.0

—

6.0

0.15

—

2.2

—

6.0

0.15

—

2.5

—

6.0

0.2

—

ns

tK Variable

4

t_KHKL

t_KLKH

t_KHKH

t_KLock

t_KReset

K, K Clock High Pulse Width

K, K Clock Low Pulse Width

K to K High

0.4

cycle

ns

0.4

—

0.4

—

0.4

—

0.4

—

0.4

0.67

—

0.77

—

0.85

—

0.94

—

1.06

K to K High

—

ns

DLL Lock Time

65,536

30

—

65,536

30

—

65,536

30

—

65,536

30

—

65,536

30

cycle

ns

5

K Static to DLL reset

—

Output Times

t_KHQV

t_KHQX

K, K Clock High to Data Output Valid

—

–0.45

—

–0.45

—

0.45

—

0.45

—

–0.45

—

0.45

—

ns

K, K Clock High to Data Output Hold

K, K Clock High to Echo Clock Valid

K, K Clock High to Echo Clock Hold

CQ, CQ High Output Valid

–0.45

—

–0.45

—

–0.45

—

–0.45

—

t_KHCQV

t_KHCQX

t_CQHQV

t_CQHQX

t_QVLD

–0.45

—

–0.45

—

0.45

—

0.45

—

0.45

—

–0.45

—

–0.45

—

–0.45

—

–0.45

—

–0.45

—

0.15

—

0.15

—

0.15

—

0.15

—

0.2

—

CQ, CQ High Output Hold

–0.15

–0.2

CQ, CQ High to QVLD

0.15

0.2

t_CQHCQH

CQ Phase Distortion

0.55

—

0.65

—

0.75

—

0.85

—

1.0

—

ns

t_KHQZ

K Clock High to Data Output High-Z

—

0.45

—

0.45

—

0.45

—

0.45

—

0.45

—

ns

5

t_KHQX1

K Clock High to Data Output Low-Z

Setup Times

–0.45

t_AVKH

t_IVKH

Address Input Setup Time

0.23

—

0.23

—

0.25

—

0.275

—

0.4

—

ns

1

2

Control Input Setup Time

(R/W)

Control Input Setup Time

(BWX)

t_IVKH

0.18

—

0.18

—

0.2

—

0.22

—

0.28

—

ns

3

t_DVKH

Data Input Setup Time

Hold Times

t_KHAX

t_KHIX

Address Input Hold Time

0.23

—

0.23

—

0.25

—

0.275

—

0.4

—

ns

1

2

Control Input Hold Time

(R/W)

Control Input Hold Time

(BWX)

t_KHIX

0.18

—

0.18

—

0.2

—

0.22

—

0.28

—

ns

3

t_KHDX

Data Input Hold Time

Notes:

1. All Address inputs must meet the specified setup and hold times for all latching clock edges.

2. Control signals are LD, R/W.

3. Control signals are BW0, BW1 and (BW2, BW3 for x36).

4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

5. slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V and input clock are stable.

V

DD

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

Rev: 1.02a 6/2013

17/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

Rev: 1.02a 6/2013

18/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output

DD

drivers are powered by V

.

DD

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

DD

SS

JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the

falling edge of TCK.

TCK

Test Clock

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state

machine. An undriven TMS input will produce the same result as a logic one input level.

TMS

TDI

Test Mode Select

Test Data In

In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed

between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP

In Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to

the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input

level.

Output that is active depending on the state of the TAP state machine. Output changes in response to the

falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.

TDO

Test Data Out

Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Rev: 1.02a 6/2013

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GS8672T20/38BE-633/550/500/450/400

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

·

Boundary Scan Register

·

0

Bypass Register

2

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1

0

·

· · ·

Control Signals

Test Access Port (TAP) Controller

TMS

TCK

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

GSI Technology

Not Used

JEDEC Vendor

ID Code

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

0

8

1

7

1

6

0

5

1

4

1

3

0

2

0

1

0

1

Bit #

X

0

Rev: 1.02a 6/2013

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

1

Run Test Idle

Select DR

Select IR

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This

occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-

tate testing of other devices in the scan path.

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GS8672T20/38BE-633/550/500/450/400

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is

loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and

I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and

are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because

the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will

not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the

TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP

operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then

places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with

all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is

still determined by its input pins.



Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.

Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output

drivers on the falling edge of TCK when the controller is in the Update-IR state.



Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-

tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-

ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR

state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-

ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

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GS8672T20/38BE-633/550/500/450/400

JTAG TAP Instruction Set Summary

Instruction

EXTEST

Code

000

Description

Notes

1

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

IDCODE

001

1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

Forces all RAM output drivers to High-Z except CQ.

SAMPLE-Z

010

1

GSI

SAMPLE/PRELOAD

GSI

101

100

101

111

GSI private instruction.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

GSI private instruction.

1

GSI

GSI private instruction.

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

V_ILJ

Min.

–0.3

Max.

Unit Notes

0.3 * V_DD

V_DD+0.3

Test Port Input Low Voltage

V

1

V_IHJ

0.7 * V_DD

Test Port Input High Voltage

I_INHJ

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

Test Port Output CMOS High

Test Port Output CMOS Low

–300

–1

1

100

1

uA

V

2

I_INLJ

3

I_OLJ

–1

4

V_OHJ

V_OLJ

V_OHJC

V_OLJC

V_DD– 0.2

—

0.2

—

0.1

5, 6

5, 7

5, 8

5, 9

—

V

V_DD– 0.1

V

—

V

Notes:

1. Input Under/overshoot voltage must be –1 V < Vi < V

+1 V not to exceed 2.4 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

2.

V

 V V

ILJ

IN

DDn

ILJn

3. 0 V V V

IN

4. Output Disable, V

= 0 to V

DDn

OUT

5. The TDO output driver is served by the V supply.

DD

6.

7.

8.

9.

I

= –2 mA

OHJ

= + 2 mA

OLJ

= –100 uA

= +100 uA

OHJC

OLJC

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GS8672T20/38BE-633/550/500/450/400

JTAG Port AC Test Conditions

Parameter

Input high level

Input low level

Conditions

JTAG Port AC Test Load

TDO

V_DD– 0.2 V

0.2 V

1 V/ns

V_DD/2

*

50

30pF

Input slew rate

V

/2

Input reference level

DD

* Distributed Test Jig Capacitance

V

_DD/2

Output reference level

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

JTAG Port Timing Diagram

tTKC

tTKH

tTKL

TCK

tTH

tTS

TDI

TMS

tTKQ

TDO

tTH

tTS

Parallel SRAM input

JTAG Port AC Electrical Characteristics

Parameter

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

Max

—

Unit

TCK Cycle Time

50

—

ns

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

20

—

20

10

—

tTH

—

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

Package Dimensions—165-Bump FPBGA (Package E)

A1 CORNER

TOP VIEW

BOTTOM VIEW

A1 CORNER

M

Ø0.10

C

Ø0.25 C A B

Ø0.40~0.60 (165x)

1

2 3 4 5 6 7 8 9 10 11

11 10 9 8

7 6 5 4 3 2 1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

M

N

P

R

A

1.0

10.0

1.0

15±0.05

B

0.20(4x)

SEATING PLANE

C

Rev: 1.02a 6/2013

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8672T20/38BE-633/550/500/450/400

Ordering Information—GSI SigmaDDR-II+ ECCRAM

Speed

(MHz)

2

1

Org

Type

Package

T

Part Number

J

4M x 18

2M x 36

4M x 18

2M x 36

GS8672T20BE-633

GS8672T20BE-550

GS8672T20BE-500

GS8672T20BE-450

GS8672T20BE-400

GS8672T20BE-633I

GS8672T20BE-550I

GS8672T20BE-500I

GS8672T20BE-450I

GS8672T20BE-400I

GS8672T38BE-633

GS8672T38BE-550

GS8672T38BE-500

GS8672T38BE-450

GS8672T38BE-400

GS8672T38BE-633I

GS8672T38BE-550I

GS8672T38BE-500I

GS8672T38BE-450I

GS8672T38BE-400I

GS8672T20BGE-633

GS8672T20BGE-550

GS8672T20BGE-500

GS8672T20BGE-450

GS8672T20BGE-400

GS8672T20BGE-633I

GS8672T20BGE-550I

GS8672T20BGE-500I

GS8672T20BGE-450I

GS8672T20BGE-400I

GS8672T38BGE-633

GS8672T38BGE-550

SigmaDDR-II+ B2 ECCRAM

165-bump BGA

633

550

500

450

400

633

550

500

450

400

633

550

500

450

400

633

550

500

450

400

633

550

500

450

400

633

550

500

450

400

633

550

C

I

165-bump BGA

I

165-bump BGA

I

165-bump BGA

I

165-bump BGA

I

165-bump BGA

C

I

165-bump BGA

I

165-bump BGA

I

165-bump BGA

I

165-bump BGA

I

RoHS-compliant 165-bump BGA

C

I

C

Notes:

1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8672TxxBE-500T.

2. C = Commercial Temperature Range. I = Industrial Temperature Range.

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GS8672T20/38BE-633/550/500/450/400

Ordering Information—GSI SigmaDDR-II+ ECCRAM (Continued)

Speed

(MHz)

2

1

Org

Type

Package

T

Part Number

J

2M x 36

GS8672T38BGE-500

GS8672T38BGE-450

GS8672T38BGE-400

GS8672T38BGE-633I

GS8672T38BGE-550I

GS8672T38BGE-500I

GS8672T38BGE-450I

GS8672T38BGE-400I

SigmaDDR-II+ B2 ECCRAM

RoHS-compliant 165-bump BGA

500

450

400

633

550

500

450

400

C

I

Notes:

1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8672TxxBE-500T.

2. C = Commercial Temperature Range. I = Industrial Temperature Range.

Revision History

Types of Changes

Format or Content

File Name

Revisions

• Creation of datasheet

• Added 633 MHz

GS8672T20_38B_r1

GS8672T20_38B_r1a

Content

• Added Operating Currents data

• (Rev1.01a: Editorial updates)

• (Rev1.01b: Corrected 165 thermal numbers)

GS8672T20_38B_r1_01

GS8672T20_38B_r1_02

• Updated to reflect MP status

• (Rev1.02a: Removed V reference in Abs Max section)

Content

TIN

Rev: 1.02a 6/2013

27/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS8672T20
厂家：	GSI TECHNOLOGY
描述：	72Mb SigmaDDR-IITM Burst of 2 ECCRAMTM 双倍数据速率
文件：	总27页 (文件大小：376K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS8672T20 [GSI]

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