GS8673ET18_技术文档

GS8673ET18/36BK-675/625/550/500

675 MHz–500 MHz

260-Ball BGA

Commercial Temp

Industrial Temp

72Mb SigmaDDR-IIIe™

Burst of 2 ECCRAM™

1.35V V

DD

1.2V to 1.5V V

DDQ

Features

Clocking and Addressing Schemes

• On-Chip ECC with virtually zero SER

• Configurable Read Latency (3.0 or 2.0 cycles)

• Simultaneous Read and Write SigmaDDR-IIIe™ Interface

• Common I/O Bus

• Double Data Rate interface

• Burst of 2 Read and Write

The GS8673ET18/36BK SigmaDDR-IIIe ECCRAMs are

synchronous devices. They employ dual, single-ended master

clocks, CK and CK. These clocks are single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. CK and CK are used to control the address and control

input registers, as well as all output timing.

• Pipelined read operation

• Fully coherent Read and Write pipelines

The KD and KD clocks are dual mesochronous (with respect to

CK and CK) input clocks that are used to control the data input

registers. Consequently, data input setup and hold windows

can be optimized independently of address and control input

setup and hold windows.

• 1.35V nominal V

DD

• 1.2V JESD8-16A BIC-3 Compliant Interface

• 1.5V HSTL Interface

• ZQ pin for programmable output drive impedance

• ZT for programmable input termination impedance

• Configurable Input Termination

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package

–K: 5/6 RoHS-compliant package

Each internal read and write operation in a SigmaDDR-IIIe B2

ECCRAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaDDR-IIIe B2 ECCRAM is always one address

pin less than the advertised index depth (e.g. the 4M x 18 has

2M addressable index).

–GK: 6/6 RoHS-compliant package

SigmaDDR-IIIe™ Family Overview

SigmaDDR-IIIe ECCRAMs are the Common I/O half of the

SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance

ECCRAMs. Although very similar to GSI's second generation

of networking SRAMs (the SigmaQuad-II/SigmaDDR-II

family), these third generation devices offer several new

features that help enable significantly higher performance.

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles, etc. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

Parameter Synopsis

V

Speed Bin

Operating Frequency

Data Rate (per pin)

Read Latency

DD

-675

-625

-550

-500

675 / 450 MHz

625 / 400 MHz

550 / 375 MHz

500 / 333 MHz

1350 / 900 Mbps

1250 / 800 Mbps

1100 / 750 Mbps

1000 / 666 Mbps

3.0 / 2.0

1.3V to 1.4V

1.25V to 1.4V

Rev: 1.06 5/2012

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

4M x 18 (Top View)

1

2

3

4

5

6

7

8

9

10

11

12

13

MCH

(CFG)

V

DD

MCL

MVQ

MCL

ZQ

PZT1

PZT0

A

B

C

D

E

F

DD

DDQ

DD

DDQ

DD

DDQ

NC

(RSVD)

MCL

(SIOM)

V

NU

V

NU

V

SS

MCL

SA

DQ0

SS

IO

SS

I

SS

NU

V

NU

V

NU

DQ17

SA

DDQ

I

DDQ

SS

DD

SS

DDQ

I

DDQ

IO

NC

(288 Mb)

NC

(144 Mb)

V

NU

V

NU

V

NU

V

SA

DQ1

SS

IO

SS

I

DDQ

I

SS

V_SS

V

NU

V

NU

V

NU

V

DQ16

SA

DDQ

I

DD

SS

DD

I

DDQ

V

NU

V

NU

V

NU

V

SA

DQ2

SS

IO

SS

I

DD

DDQ

DD

I

SS

NU

V

NU

V

DQ15

DQ14

SA

MZT1

R/W

SA

DQ3

G

H

J

I

SS

I

IO

NU

V

NU

V

DDQ

SA

DDQ

I

DDQ

I

V

NU

V

NU

V

NU

V

SA

DQ4

SS

IO

SS

I

SS

I

SS

V

DDQ

CQ1

KD1

CK

KD0

CQ0

K

L

DDQ

REF

DD

REF

V

SS

QVLD1

QVLD0

SS

DDQ

SS

V

NU

V

NU

V

NU

V

DQ13

SA

M

N

P

R

T

SS

I

SS

I

SS

IO

SS

NU

V

NU

V

NU

V

DDQ

DLL

LD

MCH

DQ5

DQ6

IO

DDQ

I

DDQ

I

NU

V

NU

V

DQ12

DQ11

SA

MZT0

SA

IO

I

SS

I

IO

V

NU

V

NU

V

MCH

RST

SS

I

DD

DDQ

DD

I

SS

NU

V

NU

V

NU

SA

DQ7

IO

DDQ

I

DD

SS

DD

I

DDQ

V

NU

V

NU

V

NU

V

DQ10

AZT1

U

V

W

Y

SS

I

DDQ

I

SS

IO

SS

SA

NU

V

NU

V

NU

V

DDQ

DQ8

IO

DDQ

I

DDQ

SS

DD

SS

DDQ

I

(x18)

(B2)

NC

(RSVD)

V

NU

V

NU

V

DQ9

TCK

TDO

RLM0

ZT

MCL

TMS

TDI

SS

I

SS

IO

SS

V

RLM1

DD

DDQ

DD

DDQ

DD

DDQ

DD

Notes:

1. Pins 5A, 6B, and 7A are reserved for future use. They must be tied Low.

2. Pins 5R and 9N are reserved for future use. They must be tied High in this device.

3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.

4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration.

5. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.

6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.

7. Pin 9D is reserved as address pin SA for 144Mb devices. It is a true no-connect in this device.

8. Pin 7D is reserved as address pin SA for 288Mb devices. It is a true no-connect in this device.

9. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low.

10. Pins 8W and 8Y are reserved for internal use only. They must be tied Low.

11. Pins 7B and 7W are reserved for future use. They are true no-connects in this device.

Rev: 1.06 5/2012

2/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

2M x 36 (Top View)

1

2

3

4

5

6

7

8

9

10

11

12

13

MCL

(CFG)

V

DD

MCL

MVQ

MCL

ZQ

PZT1

PZT0

A

B

C

D

E

F

DD

DDQ

DD

DDQ

DD

DDQ

NC

(RSVD))

MCL

(SIOM)

V

NU

V

SS

DQ35

MCL

SA

DQ0

SS

I

SS

V

NU

V

NU

V

DDQ

DQ26

SA

DQ9

DDQ

I

DDQ

SS

DD

SS

DDQ

I

NC

(288 Mb)

NC

(144 Mb)

V

NU

V

NU

V

DQ34

SA

DQ1

SS

I

DDQ

I

SS

V

NU

V

NU

V

DDQ

DQ25

SA

DQ10

DDQ

I

DD

SS

DD

I

V

NU

V

NU

V

DQ33

SA

DQ2

SS

I

DD

DDQ

DD

I

SS

NU

V

NU

DQ24 DQ32

SA

MZT1

R/W

SA

DQ3

DQ11

DQ12

G

H

J

I

SS

I

V

NU

V

NU

V

DDQ

DQ23

SA

DDQ

I

DDQ

I

V

NU

V

NU

V

DQ31

SA

DQ4

SS

I

SS

I

SS

V

DDQ

CQ1

KD1

CK

KD0

CQ0

K

L

DDQ

REF

DD

REF

V

SS

QVLD1

QVLD0

SS

DDQ

SS

V

NU

V

NU

V

DQ22

SA

DQ13

M

N

P

R

T

SS

I

SS

I

SS

V

NU

V

NU

V

DQ30

DLL

LD

MCH

DQ5

DQ6

DDQ

I

DDQ

I

DDQ

NU

V

NU

DQ29 DQ21

SA

MZT0

SA

DQ14

DQ15

I

SS

I

V

NU

V

NU

V

DQ20

MCH

RST

SS

I

DD

DDQ

DD

I

SS

V

NU

V

NU

V

DQ28

SA

DQ7

DDQ

I

DD

SS

DD

I

DDQ

V

NU

V

NU

V

DQ19

AZT1

DQ16

U

V

W

Y

SS

I

DDQ

I

SS

NU

(x18)

SA

I

V

NU

V

NU

V

DQ27

DQ8

DDQ

I

DDQ

SS

DD

SS

DDQ

I

DDQ

(B2)

NC

(RSVD)

V

NU

V

DQ18

TCK

TDO

RLM0

MCL

TMS

TDI

DQ17

SS

I

SS

V

ZT

RLM1

DD

DDQ

DD

DDQ

DD

DDQ

DD

Notes:

1. Pins 5A, 6B, and 7A are reserved for future use. They must be tied Low.

2. Pins 5R and 9N are reserved for future use. They must be tied High in this device.

3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.

4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration.

5. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.

6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.

7. Pin 9D is reserved as address pin SA for 144Mb devices. It is a true no-connect in this device.

8. Pin 7D is reserved as address pin SA for 288Mb devices. It is a true no-connect in this device.

9. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low.

10. Pins 8W and 8Y are reserved for internal use only. They must be tied Low.

11. Pins 7B and 7W are reserved for future use. They are true no-connects in this device.

Rev: 1.06 5/2012

3/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

Pin Description

Symbol

Description

Type

SA

Address—Read or Write Address is registered on ↑CK

Input

Write/Read Data—Registered on ↑KD and ↑KD during Write operations. Driven by ↑CK and ↑CK, and

synchronized with ↑CQ and ↑CQ during Read operations.

DQ[17:0]—x18 and x36.

DQ[35:0]

I/O

DQ[35:18]—x36 only.

QVLD[1:0]

CK, CK

Read Data Valid—Driven high one half cycle before valid Read Data.

Output

Input

Primary Input Clocks—Dual single-ended. For Address and Control input latching, internal timing control,

and Read Data and Echo Clock output timing control.

Write Data Input Clocks—Dual single-ended. For Write Data input latching.

KD0, KD0—latch Write Data (DQ[17:0] in x36, DQ[8:0] in x18).

KD1, KD1—latch Write Data (DQ[35:18] in x36, DQ[17:9] in x18).

KD[1:0],

KD[1:0]

Input

Output

Input

CQ[1:0],

CQ[1:0]

Echo Clocks—Free running source synchronous output clocks.

Load Enable—Registered on↑CK.

LD

LD = 0: Loads a new address and initiates a Read or Write operation.

LD = 1: Initiates a NOP operation.

Read / Write Enable—Registered on ↑CK.

R/W = 0: initiates a Write operation when LD = 0.

R/W = 1: initiates a Read operation when LD = 0.

R/W

AZT1

Input

Address Input Termination Pull-Up Enable—Registered on↑CK.

AZT1 = 0: enables termination pull-up on Address (SA)

AZT1 = 1: disables termination pull-up on Address (SA)

DLL Enable—Weakly pulled High internally.

DLL = 0: disables internal DLL.

DLL

RST

Input

DLL = 1: enables internal DLL.

Reset—Holds the device inactive and resets the device to its initial power-on state when asserted High.

Weakly pulled Low internally.

Read Latency Select 1:0—Must be tied High or Low.

RLM[1:0] = 00: reserved.

RLM[1:0]

RLM[1:0] = 01: selects 2.0 cycle Read Latency.

RLM[1:0] = 10: selects 3.0 cycle Read Latency.

RLM[1:0] = 11: reserved.

Input

Output Driver Impedance Control Resistor Input—Must be connected to V through an external

resistor RQ to program output driver impedance.

SS

ZQ

ZT

Input

Input Termination Impedance Control Resistor Input—Must be connected to V through an external

SS

resistor RT to program input termination impedance.

Rev: 1.06 5/2012

4/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

Pin Description (Continued)

Symbol

Description

Type

Input Termination Mode Select—Selects the termination mode used for all terminated inputs. Must be tied

High or Low.

MZT[1:0] = 00: disabled.

MZT[1:0]

Input

MZT[1:0] = 01: RT/2 Thevenin-equivalent (pull-up = RT, pull-down = RT).

MZT[1:0] = 10: RT Thevenin-equivalent (pull-up = 2*RT, pull-down = 2*RT).

MZT[1:0] = 11: reserved.

Input Termination Configuration Select—Selects which inputs are terminated. Must be tied High or Low.

PZT[1:0] = 00: Write Data only.

PZT[1:0]

MVQ

PZT[1:0] = 01: Write Data, Input Clocks.

PZT[1:0] = 10: Write Data, Address, Control.

PZT[1:0] = 11: Write Data, Address, Control, Input Clocks.

Input

I/O Voltage Select—Indicates what voltage is supplied to the V

pins. Must be tied High or Low.

DDQ

MVQ = 0: Configure for 1.2V to 1.35V nominal V

.

DDQ

MVQ = 1: Configure for 1.5V nominal V

.

DDQ

V

Core Power Supply—1.35V nominal core supply voltage.

—

DD

V

I/O Power Supply—1.2V to 1.5V nominal I/O supply voltage. Configured via MVQ pin.

Input Reference Voltage—Input buffer reference voltage.

DDQ

V

REF

V

Ground

—

SS

TCK

TMS

TDI

JTAG Clock

Input

Output

Input

JTAG Mode Select—Weakly pulled High internally.

JTAG Data Input—Weakly pulled High internally.

JTAG Data Output

TDO

MCH

Must Connect High—May be tied to V

directly or via a 1kΩ resistor.

DDQ

Must Connect Low—May be tied to V directly or via a 1kΩ resistor.

MCL

NC

Input

—

SS

No Connect—There is no internal chip connection to these pins. They may be left unconnected, or tied High

or Low.

Not Used, Input—There is an internal chip connection to these input pins, but they are unused by the

device. They are pulled Low internally. They may be left unconnected or tied Low. They should not be tied

High.

NU

Input

I/O

I

Not Used Input/Output—There is an internal chip connection to these I/O pins, but they are unused by the

device. The drivers are tri-stated internally. They are pulled Low internally. They may be left unconnected or

tied Low. They should not be tied High.

NU

IO

Rev: 1.06 5/2012

5/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

Power Up Requirements

For reliability purposes, power supplies must power up simultaneously, or in the following sequence:

, V , V , V and inputs.

V

SS

DD

DDQ

REF

Power supplies must power down simultaneously, or in the reverse sequence.

After power supplies power up, the following start-up sequence must be followed.

Step 1 (Recommended, but not required): Assert RST High for at least 1ms.

While RST is asserted high:

• The DLL is disabled, regardless of the state of the DLL pin.

• Read and Write operations are ignored.

Note: If possible, RST should be asserted High before input clocks (CK, CK, KD, KD) begin toggling, and remain asserted High

until input clocks are stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing

trouble in the SRAM.

Step 2: Begin toggling input clocks.

After input clocks begin toggling, but not necessarily within specification:

• DQ are placed in the non-Read state, and remain so until the first Read operation.

• QVLD are driven Low, and remain so until the first Read operation.

• CQ, CQ begin toggling, but not necessarily within specification.

Step 3: Wait until input clocks are stable and toggling within specification.

Step 4: De-assert RST Low (if asserted High).

Step 5: Wait at least 160K (163,840) cycles.

During this time:

• Output driver and input termination impedances are calibrated (i.e. set to the programmed values).

Note: The DLL pin may be asserted High or de-asserted Low during this time. If asserted High, DLL synchronization begins

immediately after output driver and input termination impedance calibration has completed. If de-asserted Low, DLL

synchronization begins after the DLL pin is asserted High (see Step 6). In either case, Step 7 must follow thereafter.

Step 6: Assert DLL pin High (if de-asserted Low).

Step 7: Wait at least 64K (65,536) cycles.

During this time:

• The DLL is enabled and synchronized properly.

After DLL synchronization has completed:

• CQ, CQ begin toggling within specification.

Step 8: Begin initiating Read and Write operations.

Rev: 1.06 5/2012

6/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

Reset (RST) Requirements

Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence

described previously, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently

de-asserted Low (as in Step 4 in the power up sequence), Steps 5~7 in the power-up sequence must be followed before Read and

Write operations are initiated.

Note: Memory array content may be perturbed/corrupted when RST is asserted High.

DLL Operation

An on-chip DLL is used to align output timing with input clocks. The DLL uses the CK input clock as a source, and is enabled

when all of the following conditions are met:

1. The DLL pin is asserted High, and

2. The RST pin is de-asserted Low, and

3. The input clock t

≤ 6.0ns.

KHKH

Once enabled, the DLL requires 64K (65,536) stable clock cycles in order to synchronize properly.

The DLL can tolerate changes in input clock frequency due to clock jitter (i.e. such jitter will not cause the DLL to lose lock/

synchronization), provided the cycle-to-cycle jitter does not exceed 200ps (see the t

specification in the AC Electrical

KJITcc

Characteristics section for more information). However, the DLL must be resynchronized (i.e. disabled and then re-enabled)

whenever the nominal input clock frequency is changed.

When the DLL is enabled, read latency is determined by the RLM mode pins, as defined in the Read Latency section. Output

timing is aligned with the input clocks.

The DLL is disabled when any of the following conditions are met:

1. The DLL pin is de-asserted Low, or

2. The RST pin is asserted High, or

3. The input clock is stopped for at least 30ns, or t

≥ 30ns.

KHKH

On-Chip Error Correction

SigmaDDR-IIIe ECCRAMs implement a single-bit error detection and correction algorithm (specifically, a Hamming Code) on

each DDR data word (comprising two 9-bit data bytes) transmitted on each 9-bit data bus (i.e., transmitted on DQ[8:0], DQ[17:9],

DQ[26:18], or DQ[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible

to the user).

The ECC algorithm neither corrects nor detects multi-bit errors. However, GSI ECCRAMs are architected in such a way that a

single SER event very rarely causes a multi-bit error across any given “transmitted data unit”, where a “transmitted data unit”

represents the data transmitted as the result of a single read or write operation to a particular address. The extreme rarity of

multi-bit errors results in the SER mentioned previously (i.e., <0.002 FITs/Mb (measured at sea level)).

Not only does the on-chip ECC significantly improve SER performance, but it also frees up the entire memory array for data

storage. Very often SRAM applications allocate 1/9th of the memory array (i.e., one “error bit” per eight “data bits”, in any 9-bit

“data byte”) for error detection (either simple parity error detection, or system-level ECC error detection and correction). Such

error-bit allocation is unnecessary with ECCRAMs the entire memory array can be utilized for data storage, effectively providing

12.5% greater storage capacity compared to SRAMs of the same density not equipped with on-chip ECC.

Rev: 1.06 5/2012

7/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

Read Latency (RL)

Read Latency is the Read pipeline length, and directly impacts the maximum operating frequency of the device. It is user-

programmable through mode pins RLM [1:0].

GS8673ET18/36BK-675 Read Latency

Read Latency (RL)

3.0 cycles

RLM1

RLM0

Frequency

1

0

1

167 MHz–675 MHz

167 MHz–450 MHz

2.0 cycles

GS8673ET18/36BK-625 Read Latency

Read Latency (RL)

3.0 cycles

RLM1

RLM0

Frequency

1

0

1

167 MHz–625 MHz

167 MHz–400 MHz

2.0 cycles

GS8673ET18/36BK-550 Read Latency

Read Latency (RL)

3.0 cycles

RLM1

RLM0

Frequency

1

0

1

167 MHz–550 MHz

167 MHz–375 MHz

2.0 cycles

GS8673ET18/36BK-500 Read Latency

Read Latency (RL)

3.0 cycles

RLM1

RLM0

Frequency

1

0

1

167 MHz–500 MHz

167 MHz–333 MHz

2.0 cycles

Rev: 1.06 5/2012

8/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

Functional Description

Common I/O ECCRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.

Therefore, the SigmaDDR-IIIe ECCRAM interface and truth table are optimized for burst reads and writes. Common I/O

ECCRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high

speed Common I/O ECCRAM data bandwidth in half. Applications of this sort are better served by Separate I/O ECCRAMs such

as the SigmaQuad-IIIe series.

Truth Table

SA

LD

R/W

Current Operation

DQ (D)

DQ (Q)

↑CK

n

↑CK

n

↑CK

n

↑KD

n+1

↑KD

n+1½

↑CK

(t )

↑CK

(t )

n

(t )

(t

)

(t

)

(t

)

m

m+½

Hi-Z / *

Q2

V

1

0

X

0

1

NOP

Write

Read

X

Hi-Z / *

Q1

D1

X

D2

X

1. 1 = input High 0 = input Low; V = input valid; X = input don’t care.

2. t = t , where RL = Read Latency of the device.

m

n + RL

3. D1 and D2 indicate the first and second pieces of Write Data transferred during Write operations.

4. Q1 and Q2 indicate the first and second pieces of Read Data transferred during Read operations.

5. When DQ input termination is disabled (MZT[1:0] = 00), DQ drivers are disabled (i.e. DQ pins are tri-stated) for one cycle in response to

NOP and Write commands, RL cycles after the command is sampled.

6. When DQ input termination is enabled (MZT[1:0] = 01 or 10), DQ drivers are disabled for one cycle in response to NOP and Write

commands, RL cycles after the command is sampled. The state of the DQ pins during that time (denoted by * in the table above) is

determined by the state of the DQ input termination, as depicted in the Extended DQ Truth Tables below.

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GS8673ET18/36BK-675/625/550/500

DQ Input Termination Control

A robust methodology has been developed for these devices for controlling when DQ input termination is enabled and disabled

during Write-to-Read and Read-to-Write transitions. Specifically, the methodology can ensure that the DQ bus is never pulled to

V

/2 by the ECCRAM and/or Memory Controller input termination during the transitions (or at any other time). Such a

DDQ

condition is best avoided, because if an input signal is pulled to V

/2 (i.e. to V

- the switch point of the diff-amp receiver), it

REF

DDQ

could cause the receiver to enter a meta-stable state and consume more power than it normally would. This could result in the

device’s operating currents being higher.

The fundamental concept of the methodology is - both the ECCRAM and the Memory Controller drive the DQ bus Low (with DQ

input termination disabled) at all times except:

1. When a particular device is driving the DQ bus with valid data, and

2. From shortly before to shortly after a particular device is receiving valid data on the DQ bus, during which time the receiving

device enables its DQ termination.

And, during Write-to-Read and Read-to-Write transitions, each device enables and disables its DQ termination while the other

device is driving DQ Low, thereby ensuring that the DQ bus is never pulled to V

/2.

DDQ

Note: This methodology also reduces power consumption, since there will be no DC current through either device’s DQs when

both devices are driving Low.

In order for this methodology to work as described, the Memory Controller must have the ability to:

1. Place the ECCRAM into “DQ Drive Low Mode” at the appropriate times (i.e. before and after the ECCRAM drives valid Read

Data), and

2. Place the ECCRAM into “DQ Termination Mode” at the appropriate times (i.e. before, during, and after the ECCRAM receives

valid Write Data).

That ability is provided via the existing R/W control pin.

When the ECCRAM samples R/W High (regardless of the state of LD), it disables its DQ termination, and drives the DQ bus Low

except while driving valid Read Data in response to Read operations.

When the ECCRAM samples R/W Low (regardless of the state of LD), it disables its DQ drivers, and enables its DQ termination.

Note that NOPs initiated with R/W High and LD High are referred to as “NOPr” operations.

Note that NOPs initiated with R/W Low and LD High are referred to as “NOPw” operations.

This extended definition of the R/W control pin allows the Memory Controller to:

•

Place the ECCRAM in DQ Termination Mode, via NOPw operations, before initiating Write operations.

Keep the ECCRAM in DQ Termination Mode, via NOPw operations, after initiating Write operations.

Place the ECCRAM in DQ Drive Low Mode, via NOPr operations, before initiating Read operations.

Keep the ECCRAM in DQ Drive Low Mode, via NOPr operations, after initiating Read operations.

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Extended DQ Truth Table - RL = 2

LD

R/W

Current Operation

DQ State

↑CK

n

↑CK

n

↑CK

n+2

(t )

(t

)

n

1

0

1

0

1

NOPw

Write

NOPr

Read

Termination Enabled

Termination Disabled, Drive Low

Termination Disabled, Drive Read Data

Extended DQ Truth Table - RL = 3

LD

R/W

Current Operation

DQ State

↑CK

n

↑CK

n

↑CK

(t

↑CK

n+3

(t )

)

(t

)

n

n+2

1

0

1

0

1

NOPw

Write

NOPr

Read

Termination Enabled

---

Termination Disabled, Drive Low

Drive Read Data

Note:

When a Read operation is initiated in cycle “n”, R/W must be “High” at ↑CK of cycle “n+1” (i.e. a Read operation must always be followed by a

Read or NOPr operation). In that case, the DQ state in cycle “n+3” is “Drive Read Data”, as indicated above.

NOPr/NOPw Requirements vs. Read Latency

When DQ input termination is enabled, the number of NOPw + NOPr needed during Write-to-Read transitions, and the number of

NOPr + NOPw needed during Read-to-Write transitions, vary with Read Latency, as follows:

Read Latency

Write-to-Read Transition

Read-to-Write

0 NOPw + 2 NOPr

2 NOPr + 3 NOPw

2

(0 NOPw after Write is the minimum requirement)

(1 NOPr before Read is the minimum requirement)

(1 NOPr after Read is the minimum requirement)

(2 NOPw before Write is the minimum requirement)

0 NOPw + 1 NOPr

3 NOPr + 3 NOPw

3

(0 NOPw after Write is the minimum requirement)

(0 NOPr before Read is the minimum requirement)

(2 NOPr after Read is the minimum requirement)

(2 NOPw before Write is the minimum requirement)

Note:

The non-parenthetical information listed in the table above depicts the NOPr / NOPw requirements during Write-to-Read and Read-to-Write

transitions that should be sufficient, in most applications, to ensure that the DQ bus is never pulled to V /2. They are not, however, absolute

DDQ

requirements. In some applications fewer NOPr / NOPw may be sufficient, and in other applications more NOPr / NOPw may be required.

DQ State Transition Timing Specifications

Parameter

Symbol

Min

Max

Units

CK Clock High to DQ State Transition

tKHDQT

–0.4

0.4

ns

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DQ Input Termination Control Timing Diagram (RL = 3 example)

Write1

NOPr1

NOPr2

NOPr3

NOPr4

NOPw1

NOPw2

NOPw3

Write2

(Notes 1)

(Note 2)

(Note 3)

(Note 4)

(Note 5)

(Note 6)

(Note 7)

(Note 8)

CK, KD

SA

LD

R/W

DQ

t1

t2

t3

t4

t5

t6

Notes (all timing depicted at the ECCRAM pins):

1. The Controller initiates Write1. It stops driving DQ Low and begins driving valid Write Data ~0.75 cycles later.

Note: At the moment Write1 is initiated, the Controller is driving DQ Low and the ECCRAM is enabling its DQ termination.

2. The Controller initiates one NOPr (NOPr1) before Read1. It completes driving valid Write Data and begins driving DQ Low again ~0.75 cycles later.

In response to NOPr1, the ECCRAM disables its DQ termination and begins driving DQ Low 2 cycles later (in NOPr2), “t1” after the Controller completes

driving valid Write Data and begins driving DQ Low.

Note: t1 = “~1.25 cycles + tKHDQT” above; if it were depicted at the Controller pins, it would increase by 2*tPD, where “tPD” is the trace propagation delay

between Controller and ECCRAM. So, t1 must be >0 at the ECCRAM. As shown, t1 is the minimum it can be, because R/W is driven High in the cycle after

Write1 above. It can be increased by initiating NOPw after Write1, but that is unnecessary to ensure the successful completion of Write1.

Note: This one NOPr before Read1 causes the ECCRAM to drive DQ Low 2 cycles (instead of 1 cycle, without it) before valid Read Data.

3. The Controller initiates Read1. It stops driving DQ Low and enables its DQ termination 2.5 cycles later (in NOPr3), “t2” after the ECCRAM disables its DQ

termination and begins driving DQ Low (in NOPr2), and “t3” before the ECCRAM begins driving valid Read Data (in NOPr4).

In response to Read1, the ECCRAM stops driving DQ Low, and begins driving valid Read Data 3 cycles later (in NOPr4).

Note: t2 = “1.5 cycles - tKHDQT” above; if it were depicted at the Controller pins, t2 would decrease by 2*tPD. So, t2 must be >0 at the Controller.

t2 can be increased by initiating more NOPr in step 2, and decreased by initiating fewer NOPr in step 2.

Note: t3 = “0.5 cycles + tKHDQT” above; if it were depicted at the Controller pins, t3 would increase by 2*tPD. So, t3 must be >0 at the ECCRAM.

As shown, t3 is the minimum it could realistically be. It can be increased if the Controller enables its DQ termination earlier, but then t2 would decrease

accordingly.

4. The Controller initiates two NOPr (NOPr2 ~ NOPr3), to meet the minimum ECCRAM requirement after a Read. It continues to enable its DQ termination.

In response to NOPr3, the ECCRAM completes driving valid Read Data and begins driving DQ Low again 2 cycles later (in NOPw1).

5. The Controller initiates one additional NOPr (NOPr4) before initiating NOPw1. It continues to enable its DQ termination.

Note: This 3rd NOPr before NOPw1 causes the ECCRAM to drive DQ Low 2 cycles (instead of 1 cycle, without it) after valid Read Data.

6. The Controller initiates two NOPw (NOPw1 ~ NOPw2), to meet the minimum ECCRAM requirement before a Write. It disables its DQ termination and

begins driving DQ Low 1.5 cycles later (in NOPw2), “t4” after the ECCRAM stops driving valid Read data and begins driving DQ Low, and “t5” before the

ECCRAM stops driving DQ Low and enables its DQ termination.

In response to NOPw1, the ECCRAM stops driving DQ Low and enables its DQ termination 2 cycles later (in NOPw3).

Note: t4 = “1.5 cycles - tKHDQT” above; if it were depicted at the Controller pins, t4 would decrease by 2*tPD. So, t4 must be >0 at the Controller.

t4 can be increased by initiating more NOPr in step 5, and decreased by initiating fewer NOPr in step 5.

Note: t5 = “0.5 cycles + tKHDQT” above; if it were depicted at the Controller pins, t5 would increase by 2*tPD. So, t5 must be >0 at the ECCRAM.

As shown, t5 is the minimum it could realistically be. It can be increased if the Controller disables its DQ termination earlier, but then t4 would decrease

accordingly.

7. The Controller initiates one additional NOPw (NOPw3) before initiating Write2. It continues to drive DQ Low.

Note: This 3rd NOPw before Write2 causes the ECCRAM to enable its DQ termination “t6” (instead of “t6 - 1 cycle”, without it) before the Controller begins

driving valid Write Data.

8. The Controller initiates Write2. It stops driving DQ Low and begins driving valid Write Data later ~0.75 cycles later, “t6” after the ECCRAM stops driving

DQ Low and enables its termination.

Note: t6 = “~1.75 cycles - tKHDQT” above; if it were depicted at the Controller pins, t6 would decrease by 2*tPD. So, t6 must be >0 at the Controller.

t6 can be increased by initiating more NOPw in step 7, and decreased by initiating fewer NOPw in step 7.

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GS8673ET18/36BK-675/625/550/500

Low Power NOP Mode

When input termination is enabled on the Address (SA) inputs, those inputs can be place in Low Power NOP (LP NOP) mode via

the synchronous AZT1 input. When NOP operations are initiated with AZT1 High, the termination pull-ups on the SA inputs are

disabled, thereby reducing the DC power associated with those inputs.

Note: When input termination is enabled on the Write Data (DQ) inputs, those inputs can also be place in a similar Low Power

mode via NOPr operations. When NOPr operations are initiated, DQ termination is disabled and DQ drivers are in a “Drive Low”

state, thereby reducing the DC power associated with those inputs.

LP NOP Truth Table

LD

R/W

AZT1

Current Operation

SA Pull-Up

↑CK

n

↑CK

n

↑CK

n

↑CK

n+2

(t )

(t

)

n

X

0

1

Any

Enabled

Disabled

Notes:

1. 1 = input High; 0 = input Low; X = input don’t care.

2. AZT1 should only be driven High during NOP operations; SA input timing is not guaranteed in LP NOP Mode.

3. SA should be driven Low (or tri-stated) during LP NOP Mode, to take advantage of the power-savings feature.

LP NOP Timing Specifications

Parameter

Symbol

Min

Max

Units

t

CK Clock High to SA Pull-up Enable / Disable

0

2.0

ns

KHAZTV

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GS8673ET18/36BK-675/625/550/500

LP NOP Timing Diagram

Write1

NOPr1

NOPr2

NOPr3

NOPw4

NOPw5

NOPw6

NOPw7

NOPw8

Write2

(Notes 1)

(Note 2)

(Note 3)

(Note 4)

CK, KD

tKHAZTV(min)

tKHAZTV(max)

SA

A

B

LD

R/ W

AZT1

tKHDZTV(min)

tKHDZTV(max)

DQ

Notes:

1. The Controller initiates Write1. The ECCRAM is enabling SA and DQ termination.

2. The Controller initiates three NOPr (NOPr1 ~ NOPr3) with AZT1 High, to cause the ECCRAM to enter LP NOP mode for three cycles.

The ECCRAM disables SA termination pull up at ↑CK in NOP3, 2 cycles after sampling AZT1 = 1 at ↑CK in NOPr1.

The ECCRAM disables DQ termination and begins driving DQ Low at ↑CK in NOPr3, 2 cycles after sampling R/W = 1 at ↑CK in NOPr1.

The Controller drives SA and DQ Low during NOP1 ~ NOP8.

3. The Controller initiates five more NOPr (NOPr4 ~ NOPr8) with AZT1 Low, to allow time for the ECCRAM to exit LP NOP mode.

The ECCRAM enables SA pull up at ↑CK in NOP6, 2 cycles after sampling AZT1 = 0 at ↑CK in NOPr4.

The ECCRAM stops driving DQ Low and enables DQ termination at ↑CK in NOPr6, 2 cycles after sampling R/W = 0 at ↑CK in NOPr4.

4. The Controller initiates Write2. The ECCRAM is enabling SA and DQ termination.

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GS8673ET18/36BK-675/625/550/500

Input Timing

Address (SA) inputs are latched with CK.

Address input timing is clock-centered; that is, CK edges must be driven such that adequate setup and hold time is provided to the

address input registers, as specified by the ECCRAM.

Control (LD, R/W, AZT1) inputs are latched with CK.

Control input timing is clock-centered; that is, CK edges must be driven such that adequate setup and hold time is provided to the

control input registers, as specified by the ECCRAM.

Write Data (DQ) inputs are latched with KD[1:0] and KD[1:0].

1. KD0 and KD0 are used to latch DQ[17:0] in x36, and DQ[8:0] in x18.

2. KD1 and KD1 are used to latch DQ[35:18] in x36, and DQ[17:9] in x18.

Write Data (DQ) input timing is clock-centered; that is, KD and KD edges must be driven such that adequate setup and hold time is

provided to the data input registers, as specified by the ECCRAM.

Output Timing

The SigmaDDR-IIIe ECCRAMs feature source-synchronous output clocks, also known as echo clocks. These outputs, CQ0, CQ0,

CQ1, and CQ1 are designed to be electrically identical to data output pins. They are designed to behave just like data output pins.

They are designed to track variances demonstrated by the data outputs due to influences of temperature, voltage, process, or other

factors. As a result, the specifications that describe the relationship between the CQ clock edges and the data output edges are much

tighter than those that describe the relationship between the data outputs and the incoming CK clock.

Note that the CQ clock-to-data output specifications apply to specific combinations of clocks and data, as follows:

1. CQ0 and CQ0 are associated with DQ[17:0] in x36, and with DQ[8:0] in x18. They are also associated with QVLD0.

2. CQ1 and CQ1 are associated with DQ[35:18] in x36, and with DQ[17:9] in x18. They are also associated with QVLD1.

As can be seen, the echo clock pairs are, in each case, associated with data output pins on the nearest side of the chip. The left vs.

right side groupings prevent skew across the device and pinout from degrading the data output valid window.

Output Alignment

Q1

Active

Q2

Inactive

Q1

Inactive

Q2

Active

QVLD

Active/Inactive

↑CQ

↓CQ

↑CQ

↓CQ

Generated from ↑CK

Notes:

1. Q1 and Q2 indicate the first and second pieces of read data transferred in any given cycle.

2. Output timing is aligned with input clocks.

3. Output timing is clock-aligned. That is, CQ, CQ edges are aligned with Q edges.

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GS8673ET18/36BK-675/625/550/500

Output Driver Impedance Control

Programmable output drivers have been implemented on Read Data (DQ), Read Data Valid (QVLD), and Echo Clocks (CQ, CQ).

The output driver impedance can be programmed via the ZQ pin. When an external impedance-matching resistor (RQ) is

connected between ZQ and V_SS, output driver impedance is set to RQ/5 nominally.

Output driver impedance is set to the programmed value within 160K cycles after input clocks are operating within specification,

and RST is de-asserted Low. It is updated periodically thereafter, to compensate for temperature and voltage fluctuations in the

system.

Input Termination Impedance Control

On-die input termination can be enabled on Write Data (DQ) Address (SA), Control (LD, R/W, AZT1), and Input Clocks (CK, CK,

KD, KD) via the MZT[1:0] and PZT[1:0] pins. The termination impedance can be programmed via the ZT pin. When an external

impedance-matching resistor (RT) is connected between ZT and V_SS, termination impedance is set according to the table below.

Termination impedance is set to the programmed value within 160K cycles after input clocks are operating within specification,

and RST is de-asserted Low. It is updated periodically thereafter, to compensate for temperature and voltage fluctuations in the

system.

Note: When termination impedance is enabled on a particular input, that input should always be driven High or Low; it should

never be tri-stated (i.e., in a High-Z state). If the input is tri-stated, the termination will pull the signal to V

/ 2 (i.e., to the

DDQ

switch point of the diff-amp receiver), which could cause the receiver to enter a meta-stable state and consume more power than it

normally would. This could result in the device’s operating currents being higher.

The following table specifies the pull-up and pull-down termination impedances for each terminated input:

Pull-up and Pull-Down Termination Impedance

Pull-Down

Impedance

Pull-Up

Impedance

Terminated Inputs

PZT[1:0]

MZT[1:0]

X0

XX

01

10

XX

01

10

01

10

disabled

RT

disabled

RT

CK, CK, KD, KD

X1

0X

1X

2 * RT

disabled

RT

2 * RT

disabled

RT

SA, LD, R/W, AZT1

2 * RT

RT

2 * RT

RT

DQ

XX

2 * RT

Notes:

1. When MZT[1:0] = 00, input termination is disabled on all inputs.

2. When MZT[1:0] = 11, input termination state is not specified; it is reserved for future use.

3. During JTAG EXTEST and SAMPLE-Z instructions, input termination is disabled on all inputs.

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GS8673ET18/36BK-675/625/550/500

Electrical Specifications

Absolute Maximum Ratings

Parameter

Symbol

Rating

Units

V

Core Supply Voltage

I/O Supply Voltage when MVQ = 0

I/O Supply Voltage when MVQ = 1

Input Voltage when MVQ = 0

Input Voltage when MVQ = 1

Junction Temperature

-0.3 to +1.6

V

DD

V

-0.3 to V

DDQ

DD

V

-0.3 to V + 0.3

V

DDQ

DD

V

-0.3 to V

+ 0.3 (1.7 max)

V

IN

DDQ

V

-0.3 to V

+ 0.3 (2.0 max)

V

IN

T

0 to 125

-55 to 125

°C

J

T

Storage Temperature

STG

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions for an extended period of time may affect

reliability of this component.

Recommended Operating Conditions

Parameter

Symbol

Min

Typ

Max

Units

V

Core Supply Voltage: -675 and -625 speed bins

Core Supply Voltage: -550 and -500 speed bins

I/O Supply Voltage when MVQ = 0

1.3

1.25

1.15

1.4

1.35

1.3 ~ 1.35

1.2 ~ 1.35

1.5

1.4

V

DD

V

DD

V

DDQ

DD

V

I/O Supply Voltage when MVQ = 1

1.6

85

V

DDQ

T

Commercial Junction Temperature

0

—

°C

JC

T

Industrial Junction Temperature

–40

—

100

JI

Note:

For reliability purposes, power supplies must power up simultaneously, or in the following sequence:

, V , V , V , and Inputs.

V

SS DD DDQ REF

Power supplies must power down simultaneously, or in the reverse sequence.

Thermal Impedance

θ JA (C°/W)

Airflow = 0 m/s

θ JA (C°/W)

Airflow = 1 m/s

θ JA (C°/W)

Airflow = 2 m/s

Package

θ JB (C°/W) θ JC (C°/W)

FBGA

15.5

13.1

12.1

4.4

0.2

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GS8673ET18/36BK-675/625/550/500

I/O Capacitance

Parameter

Symbol

Min

—

Max

5.0

Units Notes

C

Input Capacitance

Output Capacitance

pF

1, 3

2, 3

IN

C

—

5.5

OUT

Notes:

1.

V

= V /2.

DDQ

IN

2.

V

= V /2.

OUT

DDQ

3. T = 25°C, f = 1 MHz.

A

Input Electrical Characteristics when MVQ = 0

Parameter

Symbol

Min

Max

Units Notes

V

0.48 * V

0.52 * V

DDQ

DC Input Reference Voltage

DC Input High Voltage

DC Input Low Voltage

DC Input High Voltage

DC Input Low Voltage

AC Input Reference Voltage

AC Input High Voltage

AC Input Low Voltage

AC Input High Voltage

AC Input Low Voltage

Notes:

V

—

4

REFdc

DDQ

V

+ 0.08

V

DDQ

+ 0.15

– 0.08

+ 0.15

IH1dc

REF

V

–0.15

0.75 * V

4

IL1dc

REF

V

5

IH2dc

DDQ

V

0.25 * V

0.53 * V

–0.15

5

IL2dc

DDQ

V

0.47 * V

1

REFac

DDQ

V

+ 0.15

V

DDQ

+ 0.25

– 0.15

+ 0.25

2, 3, 4

2, 5

IH1ac

REF

V

–0.25

– 0.2

IL1ac

REF

V

IH2ac

DDQ

V

– 0.25

0.2

IL2ac

1. V

is equal to V

plus noise.

REFdc

REFac

2. V max and V min apply for pulse widths less than one-quarter of the cycle time.

IH

IL

3. Input rise and fall times must be a minimum of 1 V/ns, and within 10% of each other.

4. Applies to: CK, CK, KD[1.0], KD[1.0], SA, DQ[35:0], LD, R/W, AZT1.

5. Applies to: DLL, RST, RLM[1:0], MZT[1:0], PZT[1:0].

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GS8673ET18/36BK-675/625/550/500

Input Electrical Characteristics when MVQ = 1

Parameter

Symbol

Min

Max

Units Notes

V

0.47 * V

0.53 * V

DDQ

DC Input Reference Voltage

DC Input High Voltage

DC Input Low Voltage

DC Input High Voltage

DC Input Low Voltage

AC Input Reference Voltage

AC Input High Voltage

AC Input Low Voltage

AC Input High Voltage

AC Input Low Voltage

Notes:

V

—

4

REFdc

DDQ

V

+ 0.1

V

+ 0.15

– 0.1

IH1dc

REF

DDQ

V

–0.15

0.75 * V

4

IL1dc

REF

V

+ 0.15

5

IH2dc

DDQ

V

0.25 * V

0.54 * V

–0.15

5

IL2dc

DDQ

V

0.46 * V

1

REFac

DDQ

V

+ 0.2

V

+ 0.25

– 0.2

2, 3, 4

2, 5

IH1ac

REF

DDQ

V

–0.25

– 0.2

IL1ac

REF

V

+ 0.25

IH2ac

DDQ

V

–0.25

0.2

IL2ac

1. V

is equal to V

plus noise.

REFdc

REFac

2. V max and V min apply for pulse widths less than one-quarter of the cycle time.

IH

IL

3. Input rise and fall times must be a minimum of 1V/ns, and within 10% of each other.

4. Applies to: CK, CK, KD[1.0], KD[1.0], SA, DQ[35:0], LD, R/W, AZT1.

5. Applies to: DLL, RST, RLM[1:0], MZT[1:0], PZT[1:0].

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GS8673ET18/36BK-675/625/550/500

Input Termination Impedance

Parameter

Symbol MZT[1:0]

Min

Max

Units Notes

01

RT * 0.85

(2*RT) * 0.8

RT * 0.8

RT * 1.15

(2*RT) * 1.2

RT * 1.2

R

Input Termination Impedance when MVQ = 0

Input Termination Impedance when MVQ = 1

Ω

1, 2, 3

IN

10

01

R

IN

10

(2*RT) * 0.75

(2*RT) * 1.25

Notes:

1. Applies to pull-up and pull-down individually.

2. Parameter applies when 105 < RT < 135.

3. Tested at V = V

* 0.2 and V

* 0.8.

IN

DDQ

Output Electrical Characteristics

Parameter

Symbol

Min

—

Max

Units Notes

V

+ 0.15

DC Output High Voltage

DC Output Low Voltage

AC Output High Voltage

AC Output Low Voltage

V

1

OHdc

DDQ

V

-0.15

—

OLdc

V

+ 0.25

OHac

DDQ

V

-0.25

—

OLac

Notes:

1. Parameters apply to: CQ, CQ, DQ, QVLD.

Output Driver Impedance

Parameter

Symbol

Min

Max

Units Notes

R

Output Driver Impedance when MVQ = 0

Output Driver Impedance when MVQ = 1

(RQ/5) * 0.9

(RQ/5) * 0.85

(RQ/5) * 1.1

Ω

1, 2

OUT

R

(RQ/5) * 1.15

OUT

Notes:

1. Parameter applies when 175Ω < RQ < 225Ω

2. Tested at V

= V

* 0.2 and V

* 0.8.

OUT

DDQ

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

Leakage Currents

Parameter

Symbol

Min

–2

Max

Units Notes

I

2

uA

1, 2

1, 3

1, 4

5, 6

LI1

I

Input Leakage Current

Output Leakage Current

–20

–2

LI2

I

20

2

LI3

I

–2

LO

Notes:

1. V = V to V .

DDQ

IN

SS

2. Parameters apply to CK, CK, KD, KD, SA, DQ, LD, R/W, AZT1 when input termination is disabled.

Parameters apply to RLM, MZT, PZT, MVQ, TCK.

3. Parameters apply to DLL, TMS, TDI (weakly pulled up).

4. Parameters apply to RST (weakly pulled down).

5. V

= V to V

.

OUT

SS

DDQ

6. Parameters apply to DQ, CQ, CQ, QVLD, TDO.

Operating Currents

I

DD

(V = 1.25V)

DD

(V = 1.3V)

DD

(V = 1.35V)

DD

(V = 1.4V)

Operating

DD

P/N

RL

Units

Frequency

x18

x36

x18

1560

1140

1470

1040

1330

990

x36

2130

1540

2000

1400

1820

1340

1670

1230

x18

1650

1210

1550

1110

1410

1060

1300

990

x36

2250

1630

2110

1480

1930

1420

1770

1300

x18

1750

1290

1650

1190

1490

1130

1380

1050

x36

2380

1720

2230

1560

2030

1510

1870

1380

3

2

3

2

3

2

3

2

675 MHz

450 MHz

625 MHz

400 MHz

550 MHz

375 MHz

500 MHz

333 MHz

GS8673ET18/36BK-675

GS8673ET18/36BK-625

GS8673ET18/36BK-550

GS8673ET18/36BK-500

n/a

mA

n/a

1260

940

1730

1260

1580

1150

860

1220

920

Notes:

1.

2. Applies at 50% Reads + 50% Writes.

I

= 0 mA; V = V or V .

IN IH IL

OUT

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

AC Test Conditions for 1.2V nominal V

Parameter

(MVQ = 0)

DDQ

Symbol

Conditions

1.3 to 1.4

1.25 to 1.4

1.15 to 1.25

0.6

Units

V

Core Supply Voltage: -675 and -625 speed bins

Core Supply Voltage: -550 and -500 speed bins

I/O Supply Voltage

V

DD

V

DDQ

V

Input Reference Voltage

REF

V

Input High Level

0.9

IH

V

Input Low Level

0.3

2.0

0.6

V

V/ns

V

IL

—

Input Rise and Fall Time

Input and Output Reference Level

Note:

Output Load Conditions RQ = 200Ω. Refer to figure below.

AC Test Conditions for 1.5V nominal V

Parameter

(MVQ = 1)

DDQ

Symbol

Conditions

1.3 to 1.4

1.25 to 1.4

1.4 to 1.6

0.75

Units

V

Core Supply Voltage: -675 and -625 speed bins

Core Supply Voltage: -550 and -500 speed bins

I/O Supply Voltage

V

DD

V

DD

V

DDQ

V

Input Reference Voltage

REF

V

Input High Level

1.25

IH

V

Input Low Level

0.25

2.0

V

V/ns

V

IL

Input Rise and Fall Time

—

Input and Output Reference Level

0.75

Note:

Output Load Conditions RQ = 200Ω. Refer to figure below.

AC Test Output Load

50Ω

DQ, CQ

V

/2

DDQ

5 pF

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GS8673ET18/36BK-675/625/550/500

AC Electrical Characteristics (independent of device speed grade)

Parameter

Symbol

Min

Max

Units Notes

Input Clock Timing

t

Clk High Pulse Width

Clk Low Pulse Width

0.45

—

cycles

ps

1

KHKL

t

0.45

KLKH

t

Clk High to Clk High

0.45

0.55

200

—

2

KHKH

t

Clk High to Write Data Clk High

DLL Lock Time

-200

3

KHKDH

t

65,536

cycles

ns

4

Klock

t

Clk Static to DLL Reset

30

—

5,11

Kreset

Output Timing

t

Clk High to Data Output Valid

Clk High to Data Output Hold

Clk High to Data Output High-Z

Clk High to Data Output Low-Z

Clk High to Echo Clock High

—

400

ps

6

KHQV

t

-400

—

KHQX

t

400

7

KHQHZ

t

-400

—

7

KHQLZ

t

400

8

KHCQH

t

(min) - 50

t

(max) + 50

Echo Clk High to Echo Clock High

9,11

10,11

CQHCQH

KHKH

t

CQHCQH

Notes:

All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal unless otherwise noted.

1. Parameters apply to CK, CK, KD, KD.

2. Parameter specifies ↑CK → ↑CK and ↑KD → ↑KD requirements.

3. Parameter specifies ↑CK → ↑KD and ↑CK → ↑KD requirements.

4. V_DDslew rate must be < 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once V_DDand input clock are stable.

5. Parameter applies to CK.

6. Parameters apply to DQ, and are referenced to ↑CK.

7. Parameters apply to DQ when MZT[1:0] = 00, and are referenced to ↑CK. They are measured at 50 mV from steady state voltage.

8. Parameter specifies ↑CK → ↑CQ timing.

9. Parameter specifies ↑CQ → ↑CQ timing. t

(min) and t

(max) are the minimum and maximum input delays from ↑CK to ↑CK

KHKH

applied to the device, as determined by the Absolute Jitter associated with those clock edges.

10. Parameter specifies ↑CQ → ↑CQ timing. t (min) and t (max) are the minimum and maximum input delays from ↑CK to ↑CK

KHKH

applied to the device, as determined by the Absolute Jitter associated with those clock edges.

11. Parameters are not tested. They are guaranteed by design, and verified through extensive corner-lot characterization.

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GS8673ET18/36BK-675/625/550/500

AC Electrical Characteristics (variable with device speed grade)

–675

–625

–550

–500

Parameter

Symbol

Min Max Min Max Min Max Min Max

Input Clock Timing

1.48

2.2

—

6.0

60

1.6

2.5

—

6.0

60

1.8

2.66

—

6.0

60

2.0

3.0

—

6.0

60

ns 1,2

ns 1,3

ps 1,4,5

t

Clk Cycle Time

KHKH

t

Clk Cycle-to-Cycle Jitter

KJITcc

Input Setup & Hold Timing

t

Address Input Valid to Clk High

Control Input Valid to Clk High

Data Input Valid to Clk High

Clk High to Address Input Hold

Clk High to Control Input Hold

Clk High to Data Input Hold

190

150

190

150

—

210

160

210

160

—

230

180

230

180

—

250

200

250

200

—

ps

6

7

8

6

7

8

AVKH

t

IVKH

t

DVKH

t

KHAX

t

KHIX

t

KHDX

Output Timing

t

Echo Clk High to Data Output Valid

Echo Clk High to Data Output Hold

—

150

—

150

—

150

—

150

—

ps 9,10

CQHQV

t

-150

CQHQX

Notes:

All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal.

1. Parameters apply to CK, CK, KD, KD.

2. Parameter applies when RL=3.

3. Parameter applies when RL=2.

4. Parameter specifies Cycle-to-Cycle (C2C) Jitter (i.e. the maximum variation from clock rising edge to the next clock rising edge).

As such, it limits Period Jitter (i.e. the maximum variation in clock cycle time from nominal) to 30ps.

And as such, it limits Absolute Jitter (i.e. the maximum variation in clock rising edge from its nominal position) to 15ps.

5. The device can tolerated C2C Jitter greater than 60ps, up to a maximum of 200ps. However, when using a device from a particular speed

bin, t (min) of that speed bin must be derated (increased) by half the difference between the actual C2C Jitter and 60ps. For example,

KHKH

if the actual C2C Jitter is 100ps, then t

(min) for the -675 speed bin (RL=3) is derated to 1.5ns (1.48ns + 0.5*(100ps - 60ps)).

KHKH

6. Parameters apply to SA, and are referenced to ↑CK.

7. Parameters apply to LD, R/W, AZT1, and are referenced to ↑CK.

8. Parameters apply to DQ, and are referenced to ↑KD & ↑KD.

9. Parameters apply to DQ, QVLD and are referenced to ↑CQ & ↑CQ.

10. Parameters are not tested. They are guaranteed by design, and verified through extensive corner-lot characterization.

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GS8673ET18/36BK-675/625/550/500

SigmaDDR-IIIe Burst of 2, RL = 3

Write

NOPr

Read

NOPr

NOPw

KD

t_KHKH

t_KHKLt_KLKHt_KHKH

t_KHKDH

CK

t_KHKH

t_KHKLt_KLKHt_KHKH

CK

t_AVKHt_KHAX

SA A1

A2

A3

A4

t_IVKHt_KHIX

LD

R/W

t_KHDX

t_KHDX(to KD)

(to KD) t_DVKH

t_DVKH

t_KHQV

t_KHQX

D11 D12 D21 D22

Q31 Q32 Q41 Q42

DQ

QVLD

t_CQHQX

t_CQHQV

t_CQHQX

t_KHCQH

t_CQHQV

CQ

t_CQHCQH

CQ

Note: The DQ = Low states depicted in this diagram apply when DQ input termination is enabled (MZT = 01 or 10). See the DQ Input

Termination Control section for more information. When DQ input termination is disabled (MZT = 00), the DQ output state during

non-Reads is High-Z.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

JTAG Test Mode Description

These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1

functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller,

etc.), ECCRAM, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, these devices

contain a TAP Controller and multiple TAP Registers. The TAP Registers consist of one Instruction Register and multiple Data

Registers.

The TAP consists of the following four signals:

Pin Name

I/O

Description

TCK

Test Clock

I

Induces (clocks) TAP Controller state transitions.

Inputs commands to the TAP Controller.

Sampled on the rising edge of TCK.

TMS

TDI

Test Mode Select

Test Data In

I

Inputs data serially to the TAP Registers.

Sampled on the rising edge of TCK.

Outputs data serially from the TAP Registers.

Driven from the falling edge of TCK.

TDO

Test Data Out

O

Concurrent TAP and Normal ECCRAM Operation

According to IEEE std. 1149.1, most public TAP Instructions do not disrupt normal device operation. In these devices, the only

exceptions are EXTEST and SAMPLE-Z. See the Tap Registers section for more information.

Disabling the TAP

When JTAG is not used, TCK should be tied Low to prevent clocking the ECCRAM. TMS and TDI should either be tied High

through a pull-up resistor or left unconnected. TDO should be left unconnected.

JTAG DC Operating Conditions

Parameter

Symbol

Min

Max

Units

Notes

V

0.75 * V

V

+ 0.15

DDQ

JTAG Input High Voltage

JTAG Input Low Voltage

JTAG Output High Voltage

JTAG Output Low Voltage

V

1

TIH

DDQ

V

0.25 * V

—

–0.15

– 0.2

1

TIL

DDQ

V

2, 3

2, 4

TOH

DDQ

V

—

0.2

TOL

Notes:

1. Parameters apply to TCK, TMS, and TDI during JTAG Testing.

2. Parameters apply to TDO during JTAG testing.

3.

4.

I

= –2.0 mA.

= 2.0 mA.

TOH

TOL

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

JTAG AC Timing Specifications

Parameter

Symbol

Min

Max

Unit

t

TCK Cycle Time

TCK High Pulse Width

50

20

10

—

0

—

10

—

ns

THTH

t

THTL

t

TCK Low Pulse Width

TLTH

t

TMS Setup Time

MVTH

t

TMS Hold Time

THMX

t

TDI Setup Time

DVTH

t

TDI Hold Time

THDX

t

Capture Setup Time (Address, Control, Data, Clock)

Capture Hold Time (Address, Control, Data, Clock)

TCK Low to TDO Valid

CS

t

CH

t

TLQV

t

TCK Low to TDO Hold

TLQX

JTAG Timing Diagram

t_THTL

t_TLTH

t_THTH

TCK

TMS

TDI

t_MVTHt_THMX

t_DVTHt_THDX

t_TLQV

t_TLQX

TDO

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

TAP Controller

The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations

associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK.

The TAP Controller enters the Test-Logic Reset state in one of two ways:

1. At power up.

2. When a logic 1 is applied to TMS for at least 5 consecutive rising edges of TCK.

The TDI input receiver is sampled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.

The TDO output driver is enabled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.

TAP Controller State Diagram

1

0

Test-Logic Reset

0

1

Run-Test / Idle

Select DR-Scan

Select IR-Scan

0

1

Capture-DR

Capture-IR

0

Shift-DR

0

Shift-IR

0

1

Exit1-DR

0

1

Exit1-IR

0

1

Pause-DR

1

0

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

1

0

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

TAP Registers

TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output

data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: Instruction Registers (IR), which are

manipulated via the IR states in the TAP Controller, and Data Registers (DR), which are manipulated via the DR states in the TAP

Controller.

Instruction Register (IR—3 bits)

The Instruction Register stores the various TAP Instructions supported by ECCRAM. It is loaded with the IDCODE instruction

(logic 001) at power-up, and when the TAP Controller is in the Test-Logic Reset and Capture-IR states. It is inserted between TDI

and TDO when the TAP Controller is in the Shift-IR state, at which time it can be loaded with a new instruction. However, newly

loaded instructions are not executed until the TAP Controller has reached the Update-IR state.

The Instruction Register is 3 bits wide, and is encoded as follows:

Code

(2:0)

Instruction

Description

Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Reg-

ister when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register

between TDI and TDO when the TAP Controller is in the Shift-DR state.

Also transfers the contents of the Boundary Scan Register associated with all output signals (DQ,

QVLD, CQ, CQ) directly to their corresponding output pins. However, newly loaded Boundary Scan

Register contents do not appear at the output pins until the TAP Controller has reached the

Update-DR state.

000

EXTEST

Also disables all input termination.

See the Boundary Scan Register description for more information.

Loads a predefined device- and manufacturer-specific identification code into the ID Register when

the TAP Controller is in the Capture-DR state, and inserts the ID Register between TDI and TDO

when the TAP Controller is in the Shift-DR state.

001

010

IDCODE

See the ID Register description for more information.

Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Reg-

ister when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register

between TDI and TDO when the TAP Controller is in the Shift-DR state.

Also disables all input termination.

SAMPLE-Z

Also forces DQ output drivers to a High-Z state.

See the Boundary Scan Register description for more information.

011

100

PRIVATE

SAMPLE

Reserved for manufacturer use only.

Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Reg-

ister when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register

between TDI and TDO when the TAP Controller is in the Shift-DR state.

See the Boundary Scan Register description for more information.

101

110

PRIVATE

Reserved for manufacturer use only.

Loads a logic 0 into the Bypass Register when the TAP Controller is in the Capture-DR state, and

inserts the Bypass Register between TDI and TDO when the TAP Controller is in the Shift-DR

state.

111

BYPASS

See the Bypass Register description for more information.

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GS8673ET18/36BK-675/625/550/500

Bypass Register (DR—1 bit)

The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic

0 when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the Capture-DR state. It is

inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP

Controller is in the Shift-DR state.

ID Register (DR—32 bits)

The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE

instruction has been loaded into the Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between

TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the

Shift-DR state.

The ID Register is 32 bits wide, and is encoded as follows:

See BSDL Model

(31:12)

GSI ID

(11:1)

Start Bit

(0)

XXXX XXXX XXXX XXXX XXXX

0001 1011 001

1

Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB,

and the LSB serially shifts data out through TDO.

Boundary Scan Register (DR—127 bits)

The Boundary Scan Register is equal in length to the number of active signal connections to the ECCRAM (excluding the TAP

pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the logic states of all

signals composing the ECCRAM’s I/O ring when the EXTEST, SAMPLE, or SAMPLE-Z instruction has been loaded into the

Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between TDI and TDO when the EXTEST,

SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the Shift-DR state.

Additionally, the contents of the Boundary Scan Register associated with the ECCRAM outputs (DQ, QVLD, CQ, CQ) are driven

directly to the corresponding ECCRAM output pins when the EXTEST instruction is selected. However, after the EXTEST

instruction has been selected, any new data loaded into Boundary Scan Register when the TAP Controller is in the Shift-DR state

does not appear at the output pins until the TAP Controller has reached the Update-DR state.

The value captured in the boundary scan register for NU pins is determined by the external pin state while the NC pins are 0

regardless of the external pin state. The value captured in the internal cells is 1.

Output Driver State During EXTEST

EXTEST allows the Internal Cell (Bit 127) in the Boundary Scan Register to control the state of DQ drivers. That is, when Bit 127

= 1, DQ drivers are enabled (i.e., driving High or Low), and when Bit 127 = 0, DQ drivers are disabled (i.e., forced to High-Z

state). See the Boundary Scan Register section for more information.

Input Termination State During EXTEST and SAMPLE-Z

Input termination on all inputs is disabled during EXTEST and SAMPLE-Z.

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GS8673ET18/36BK-675/625/550/500

Boundary Scan Register Bit Order Assignment

The table below depicts the order in which the bits are arranged in the Boundary Scan Register. Bit 1 is the LSB and Bit 127 is the

MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out

through TDO.

Bit

1

Pad

7L

Bit

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

Pad

11G

13G

10G

12G

11H

13H

10J

Bit

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

Pad

10W

8V

9U

8T

Bit

85

Pad

4R

2R

3P

1P

4P

2P

3N

1N

4M

2M

3L

Bit

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

Pad

3C

2

7K

86

2B

3

9L

87

4B

4

9K

88

6A

5

8J

9R

8P

9N

8M

6M

7N

5N

7P

6P

5R

6T

89

6B

6

7H

90

6C

7

9H

91

5D

8

7G

8G

9F

12J

92

6E

9

13K

13L

11L

93

5F

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

94

6G

5H

8E

95

7D

12M

10M

13N

11N

12P

10P

13P

11P

12R

10R

13T

11T

12U

10U

13V

11V

12W

96

1L

6J

9D

97

1K

2J

5K

8C

98

5L

8B

99

4J

Internal

9B

7U

5U

6V

6W

7Y

4W

2W

3V

1V

4U

2U

3T

100

101

102

103

104

105

106

107

108

109

110

111

112

1H

3H

2G

4G

1G

3G

2F

7A

9A

10B

12B

11C

13C

10D

12D

11E

13E

10F

12F

4F

1E

3E

2D

4D

1C

1T

Rev: 1.06 5/2012

31/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

260-Pin BGA Package Drawing (Package K)

C

Ø0.08 S

Ø0.08 S C

B S

A S

Ø0.50~Ø0.70(260x)

PIN #1 CORNER

13 12 11 10

9 8 7 6 5 4 3

2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

12.60 0.05

14.00 0.05

B

1.00

A

12.00

0.05(4X)

HEAT SPREADER

4–R0.5 (MAX)

C

SEATING PLANE

Ball Pitch:

1.00 Substrate Thickness: 0.51

0.60 Mold Thickness:

Ball Diameter:

—

Rev: 1.06 5/2012

32/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

Ordering Information—GSI SigmaDDR-IIIe ECCRAM

Speed

T

Org

Part Number

Type

Package

Status

A

(MHz)

675

625

550

500

675

625

550

500

675

625

550

500

675

625

550

500

675

625

550

500

675

625

550

500

675

625

550

500

4M x 18

2M x 36

4M x 18

2M x 36

GS8673ET18BK-675

GS8673ET18BK-625

GS8673ET18BK-550

GS8673ET18BK-500

GS8673ET18BK-675I

GS8673ET18BK-625I

GS8673ET18BK-550I

GS8673ET18BK-500I

GS8673ET36BK-675

GS8673ET36BK-625

GS8673ET36BK-550

GS8673ET36BK-500

GS8673ET36BK-675I

GS8673ET36BK-625I

GS8673ET36BK-550I

GS8673ET36BK-500I

GS8673ET18BGK-675

GS8673ET18BGK-625

GS8673ET18BGK-550

GS8673ET18BGK-500

GS8673ET18BGK-675I

GS8673ET18BGK-625I

GS8673ET18BGK-550I

GS8673ET18BGK-500I

GS8673ET36BGK-675

GS8673ET36BGK-625

GS8673ET36BGK-550

GS8673ET36BGK-500

SigmaDDR-IIIe B2 ECCRAM

260-ball BGA

Qual

C

I

C

I

SigmaDDR-IIIe B2 ECCRAM RoHS-compliant 260-ball BGA

C

I

C

Notes: C = Commercial Temperature Range. I = Industrial Temperature Range.

Rev: 1.06 5/2012

33/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET18/36BK-675/625/550/500

Ordering Information—GSI SigmaDDR-IIIe ECCRAM

Speed

(MHz)

T

Org

Part Number

Type

Package

Status

A

2M x 36

GS8673ET36BGK-675I

GS8673ET36BGK-625I

GS8673ET36BGK-550I

GS8673ET36BGK-500I

SigmaDDR-IIIe B2 ECCRAM RoHS-compliant 260-ball BGA

Qual

675

I

625

I

550

500

Notes: C = Commercial Temperature Range. I = Industrial Temperature Range.

Revision History

Types of Changes

Rev. Code

Revisions

Format or Content

• Creation of new datasheet

• Changed speed bins to 625, 550, & 500 MHz.

GS8673ET1836BK_r1

• Increased V (min) spec from 1.25V to 1.3V for 625 MHz speed

DD

bin.

• Improved t

GS8673ET1836BK_r1_01

Content

/ t

specs from +/-500ps to +/-400ps.

KHQV KHQX

• Updated the DQ Input Termination Control section.

• Updated the Low Power NOP Mode section.

• Added 675 MHz speed bin.

• Updated to MP status.

GS8673ET1836BK_r1_02

• Re-added t

(max) specs (previously inadvertently deleted).

KHKH

GS8673ET1836BK_r1_02a

GS8673ET1836BK_r1_03

Content

• Updated I specs.

DD

• Added part numbers for lead-free RoHS-compliant BGA package.

• Updated Addressing Schemes section, and moved to p.1.

• Updated Absolute Maximum Ratings.

• Updated Input Electrical Characteristics.

• Corrected JTAG BScan Register bit order.

GS8673ET1836BK_r1_04

GS8673ET1836BK_r1_05

Content

• Updated status of lead-free RoHS-compliant BGA pkg to “Qual”.

• Updated Absolute Maximum Ratings.

• Updated Recommended Operating Conditions.

• Updated AC Electrical Specifications:

GS8673ET1836BK_r1_06

Content

Updated t

spec, and associated note.

CQHCQH

Added t

and t

specs, and associated notes.

KJITcc

CQHCQH

Removed t

and t

specs.

CQvar

Kvar

Rev: 1.06 5/2012

34/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS8673ET18
厂家：	GSI TECHNOLOGY
描述：	72Mb SigmaDDR-IIIeâ¢ Burst of 2 ECCRAMâ¢ 双倍数据速率
文件：	总34页 (文件大小：454K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS8673ET18 [GSI]

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GS8673ET18BGK-500

GS8673ET18BGK-550

GS8673ET18BGK-550IS

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GS8673ET18BGK-625IS

GS8673ET18BGK-625S

GS8673ET18BGK-675I

GS8673ET36BGK-500

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