GS88018CGT-150 [GSI]
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs;
| 型号： | GS88018CGT-150 |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs 时钟 静态存储器 内存集成电路 |
| 文件： | 总24页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS88018/32/36CT-xxx
333 MHz–150 MHz
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
100-Pin TQFP
Commercial Temp
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS88018/32/36CT is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Functional Description
Applications
The GS88018/32/36CT is a 9,437,184-bit (8,388,608-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Controls
Sleep Mode
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88018/32/36CT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
) pins are used to decouple output noise
DDQ
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-333
-300
-250
-200
-150
Unit
tKQ
2.5
3.0
2.5
3.3
2.5
4.0
3.0
5.0
3.8
6.7
ns
ns
tCycle
Pipeline
3-1-1-1
Curr (x18)
Curr (x32/x36)
240
280
225
260
195
225
170
195
140
160
mA
mA
tKQ
4.5
4.5
5.0
5.0
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
tCycle
Flow Through
2-1-1-1
Curr (x18)
Curr (x32/x36)
180
205
165
190
160
180
140
160
128
145
mA
mA
Rev: 1.04 6/2012
1/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
GS88018C 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
NC
NC
V
V
NC
DQPA
DQA
DQA
V
V
DQA
DQA
V
NC
V
ZZ
DQA
DQA
V
V
DQA
DQA
NC
NC
V
V
NC
NC
NC
1
2
3
4
5
6
7
8
9
80
79
78
V
DDQ
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SS
SS
NC
NC
DQB
DQB
512K x 18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
Top View
V
DDQ
DDQ
DQB
DQB
FT
SS
V
DD
NC
DD
V
SS
DQB
DQB6
V
DDQ
DDQ
V
SS
SS
DQB
DQB
DQPB
NC
V
SS
SS
V
DDQ
DDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either V or V . These pins can also be left floating.
DD
SS
Rev: 1.04 6/2012
2/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
GS88032C 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
DQB
DQB
NC
DQC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
V
V
DDQ
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
V
SS
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
256K x 32
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
Top View
V
DDQ
DDQ
DQB
DQB
DQC
DQC
V
SS
FT
NC
V
DD
V
NC
DD
ZZ
V
SS
DQA
DQA
V
DQD
DQD
V
DDQ
DDQ
V
V
SS
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
SS
V
V
DDQ
DDQ
DQA
DQA
NC
DQD
DQD
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
Rev: 1.04 6/2012
3/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
GS88036C 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPB
DQB
DQB
DQPC
DQC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
V
V
V
DDQ
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
256K x 36
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
Top View
V
DDQ
DDQ
DQB
DQB
DQC
DQC
V
SS
FT
NC
V
DD
V
NC
DD
ZZ
V
SS
DQA
DQA
V
DQD
DQD
V
DDQ
DDQ
V
V
SS
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
SS
V
V
DDQ
DDQ
DQA
DQA
DQPA
DQD
DQD
DQPD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
Rev: 1.04 6/2012
4/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
TQFP Pin Description
Symbol
A0, A1
A
Type
Description
I
I
Address field LSBs and Address Counter preset Inputs
Address Inputs
DQA
DQB
DQC
DQD
I/O
Data Input and Output pin
NC
—
No Connect
I
I
I
I
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Clock Input Signal; active high
BW
BA, BB, BC, BD
CK
Global Write Enable—Writes all bytes; active low
GW
I
I
I
I
Chip Enable; active low
Chip Enable; active high
E1, E3
E2
G
Output Enable; active low
Burst address counter advance enable; active low
ADV
I
I
I
I
I
I
I
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
ADSP, ADSC
ZZ
FT
LBO
V
DD
V
I/O and Core Ground
SS
V
Output driver power supply
DDQ
Rev: 1.04 6/2012
5/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
GS88018/32/36C Block Diagram
Register
A0–An
D
Q
A0
A0
A1
D0
Q0
Q1
A1
D1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
36
36
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E2
E3
D
Q
Register
D
Q
FT
G
1
Power Down
Control
DQx1–DQx9
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.04 6/2012
6/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
Mode Pin Functions
Mode Name
Pin Name
State
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
L
Burst Order Control
Output Register Control
Power Down Control
LBO
H
L
FT
ZZ
H or NC
L or NC
H
Active
Standby, IDD = ISB
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0]
00
A[1:0]
01
A[1:0]
10
A[1:0]
11
A[1:0]
A[1:0]
01
A[1:0]
10
A[1:0]
11
1st address
2nd address
3rd address
4th address
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
10
11
00
00
11
10
11
00
01
11
00
01
00
01
10
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.04 6/2012
7/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
BA
X
BB
X
BC
X
BD
X
Notes
1
Write No Bytes
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
Write all bytes
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.04 6/2012
8/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
Synchronous Truth Table
State
Diagram
Key
Address
Used
3
Operation
E1
E2
E3
ADSP
ADSC
ADV
W
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
None
None
X
X
L
L
L
L
H
L
L
L
X
H
X
H
X
H
X
H
X
L
H
X
H
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
L
L
L
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
X
X
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
High-Z
None
X
X
L
X
X
L
High-Z
None
X
L
High-Z
None
X
X
H
H
H
X
X
X
X
X
X
X
X
X
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
R
H
H
H
X
H
X
H
X
H
X
W
CR
CR
CW
CW
L
H
H
H
H
H
H
H
H
Next
Next
Next
Current
Current
Current
Current
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.04 6/2012
9/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.04 6/2012
10/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.04 6/2012
11/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
VDD
Description
Value
Unit
V
Voltage on VDD Pins
Voltage in VDDQ Pins
–0.5 to 4.6
–0.5 to 4.6
VDDQ
VI/O1
VI/O2
VIN
V
–0.5 to VDD +0.5 (≤ 4.6 V max.)
Voltage on I/O Pins
Voltage on I/O Pins
V
V
–0.5 to VDDQ +0.5 (≤ 4.6 V max.)
–0.5 to VDD +0.5 (≤ 4.6 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
IIN
+/–20
+/–20
mA
mA
W
IOUT
PD
1.5
oC
oC
TSTG
–55 to 125
–55 to 125
TBIAS
Temperature Under Bias
Notes:
1. Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recom-
mended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect
reliability of this component.
2. Both V
V
must be met.
I/O1 and I/O2
Power Supply Voltage Ranges
Parameter
3.3 V Supply Voltage
Symbol
VDD3
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
V
VDD2
2.5 V Supply Voltage
2.3
2.5
2.7
V
3.3 V VDDQ I/O Supply Voltage
VDDQ3
VDDQ2
VDD
VDD
3.0
3.3
V
2.5 V VDDQ I/O Supply Voltage
2.3
2.5
V
Note:
V
must be less than or equal to V + 0.3 V at all times.
DD
DDQ
Rev: 1.04 6/2012
12/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
V
Range Logic Levels
DD3
Parameter
Symbol
VIH
Min.
2.0
Typ.
—
Max.
Unit
V
VDD + 0.3
VDD + 0.3
VDDQ + 0.3
Input High Voltage
Input High Voltage for Data I/O pins
Input High Voltage for Data I/O pins
Input Low Voltage
VIH(I/O)1
VIH(I/O)2
VIL
2.0
—
V
2.0
—
V
–0.3
—
0.8
V
Notes:
1.
2.
3.
4.
V
V
V
V
(max) must be met for any instantaneous value of V .
DD
IH
(max) must be met for any instantaneous value of V
(max) must be met for any instantaneous value of V
.
DD
IH(I/O)1
.
IH(I/O)2
DDQ
needs to power-up before or at the same time as V
to make sure V (max) is not exceeded.
IH
DD
DDQ
V
Range Logic Levels
DD2
Parameter
Symbol
VIH
Min.
Typ.
—
Max.
Unit
V
0.6*VDD
0.6*VDD
0.6*VDD
V
DD + 0.3
Input High Voltage
Input High Voltage for Data I/O pins
Input High Voltage for Data I/O pins
Input Low Voltage
VIH(I/O)1
VIH(I/O)2
VIL
VDD + 0.3
—
V
V
DDQ + 0.3
0.3*VDD
—
V
–0.3
—
V
Notes:
1.
2.
3.
4.
V
V
V
V
(max) must be met for any instantaneous value of V .
DD
IH
(max) must be met for any instantaneous value of V
(max) must be met for any instantaneous value of V
.
DD
IH(I/O)1
.
IH(I/O)2
DDQ
needs to power-up before or at the same time as V
to make sure V (max) is not exceeded.
IH
DD
DDQ
Recommended Operating Temperatures
Parameter
Symbol
Min.
Typ.
Max.
Unit
TA
Ambient Temperature (Commercial Range Versions)
0
25
70
°C
Note:
Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
Thermal Impedance
Test PCB
Substrate
θ JA (C°/W)
Airflow = 0 m/s
θ JA (C°/W)
Airflow = 1 m/s
θ JA (C°/W)
Airflow = 2 m/s
Package
θ JB (C°/W)
θ JC (C°/W)
100 TQFP
4-layer
38.7
33.5
31.9
27.6
10.6
Notes:
1. Thermal Impedance data is based on a number of samples from multiple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
Rev: 1.04 6/2012
13/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
50%
DD
V
SS
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Note:
Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
Typ.
Max.
Unit
pF
Input Capacitance
4
6
5
7
CI/O
VOUT = 0 V
Input/Output Capacitance
pF
Note:
These parameters are sample tested.
AC Test Conditions
Parameter
Conditions
VDD – 0.2 V
Input high level
Input low level
0.2 V
1 V/ns
VDD/2
Input slew rate
Input reference level
VDDQ/2
Output reference level
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
*
50Ω
30pF
V
DDQ/2
* Distributed Test Jig Capacitance
Rev: 1.04 6/2012
14/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
–1 uA
–1 uA
1 uA
100 uA
IIN1
ZZ Input Current
FT Input Current
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–100 uA
–1 uA
1 uA
1 uA
IIN2
IOL
Output Disable, VOUT = 0 to VDD
IOH = –8 mA, VDDQ = 2.375 V
IOH = –8 mA, VDDQ = 3.135 V
IOL = 8 mA
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
–1 uA
1.7 V
2.4 V
—
1 uA
—
VOH2
VOH3
VOL
—
0.4 V
Rev: 1.04 6/2012
15/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
Operating Currents
-333
-300
-250
-200
-150
Parameter
Test Conditions
Mode
Symbol
Unit
0
0
0
0
0
to 70°C
to 70°C
to 70°C
to 70°C
to 70°C
IDD
240
40
225
35
195
30
170
25
140
20
Pipeline
mA
mA
mA
mA
IDDQ
(x32/
x36)
IDD
Flow
Through
180
25
165
25
155
25
140
20
130
15
Device Selected;
All other inputs
≥VIH or ≤ VIL
IDDQ
Operating
Current
IDD
220
20
205
20
180
15
155
15
130
10
Pipeline
Output open
IDDQ
(x18)
IDD
Flow
Through
165
15
150
15
145
15
130
10
120
8
IDDQ
ISB
ISB
IDD
IDD
Pipeline
25
25
70
70
25
25
65
65
25
25
65
65
25
25
65
65
25
25
60
60
mA
mA
mA
mA
Standby
Current
ZZ ≥ VDD – 0.2 V
—
—
Flow
Through
Pipeline
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
Deselect
Current
Flow
Through
Notes:
1.
2. All parameters listed are worst case scenario.
I
and I
apply to any combination of V , V , V
, and V
operation.
DDQ2
DD
DDQ
DD3 DD2 DDQ3
Rev: 1.04 6/2012
16/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
AC Electrical Characteristics
-333
-300
-250
-200
-150
Parameter
Symbol
Unit
Min
3.0
—
Max
—
2.5
—
—
—
—
—
4.5
—
—
—
—
—
Min
3.3
—
Max
—
2.5
—
—
—
—
—
5.0
—
—
—
—
—
Min
4.0
—
Max
—
2.5
—
—
—
—
—
5.5
—
—
—
—
—
Min
5.0
—
Max
—
3.0
—
—
—
—
—
6.5
—
—
—
—
—
Min
6.7
—
Max
—
3.8
—
—
—
—
—
7.5
—
—
—
—
—
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
tKC
tKQ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
1.5
1.5
1.0
0.1
4.5
—
1.5
1.5
1.0
0.1
5.0
—
1.5
1.5
1.2
0.2
5.5
—
1.5
1.5
1.4
0.4
6.5
—
1.5
1.5
1.5
0.5
7.5
—
Pipeline
tLZ1
tS
Clock to Output in Low-Z
Setup time
Hold time
tH
Clock Cycle Time
Clock to Output Valid
tKC
tKQ
tKQX
Clock to Output Invalid
2.0
2.0
1.3
0.3
1.0
2.0
2.0
1.4
0.4
1.0
2.0
2.0
1.5
0.5
1.3
2.0
2.0
1.5
0.5
1.3
2.0
2.0
1.5
0.5
1.5
Flow
Through
tLZ1
tS
Clock to Output in Low-Z
Setup time
Hold time
tH
Clock HIGH Time
tKH
Clock LOW Time
tKL
1.2
1.5
—
1.2
1.5
—
1.5
1.5
—
1.5
1.5
—
1.7
1.5
—
ns
ns
Clock to Output in
High-Z
tHZ1
2.5
2.5
2.5
3.0
3.0
G to Output Valid
G to output in Low-Z
G to output in High-Z
ZZ setup time
tOE
—
0
2.5
—
2.5
—
—
—
—
0
2.5
—
2.5
—
—
—
—
0
2.5
—
2.5
—
—
—
—
0
3.0
—
3.0
—
—
—
—
0
3.8
—
3.8
—
—
—
ns
ns
ns
ns
ns
ns
tOLZ1
tOHZ1
tZZS2
tZZH2
tZZR
—
5
—
5
—
5
—
5
—
5
ZZ hold time
1
1
1
1
1
ZZ recovery
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.04 6/2012
17/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
Pipeline Mode Timing
Begin
Read A Cont
Single Read
Cont
Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont
Deselect
Single Write
tKL
Burst Read
tKH
tKC
CK
ADSP
tS
tS
tH
ADSC initiated read
ADSC
ADV
tS
tH
tH
A
B
C
A0–An
GW
tS
tS
tH
tH
BW
tS
Ba–Bd
E1
tS
tS
tS
Deselected with E1
tH
E1 masks ADSP
tH
tH
E2 and E3 only sampled with ADSP and ADSC
E2
E3
G
tS
D(B)
tKQ
tKQX
tHZ
tOE
tOHZ
Q(A)
tH
tLZ
Q(C)
Q(C+1)
Q(C+2) Q(C+3)
DQa–DQd
Rev: 1.04 6/2012
18/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
Flow Through Mode Timing
Begin
Read A Cont
tKH
Cont
Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont
Deselect
tKL
tKC
CK
Fixed High
ADSP
tS
tH
tS
tH
ADSC initiated read
ADSC
ADV
A0–An
GW
tS
tH
tS
tH
A
B
C
tS
tH
tS
tH
BW
tS
tH
Ba–Bd
E1
tS
tS
Deselected with E1
tH
tH
E2 and E3 only sampled with ADSC
E2
tS
tH
E3
G
tH
tS
tKQ
tLZ
tHZ
tOE
tOHZ
D(B)
tKQX
Q(A)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
DQa–DQd
Rev: 1.04 6/2012
19/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
Setup
Hold
ADSP
ADSC
tZZR
tZZS
tZZH
ZZ
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.
Rev: 1.04 6/2012
20/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
TQFP Package Drawing (Package T)
θ
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
0.10
7°
θ
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.04 6/2012
21/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 32
256K x 32
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 32
256K x 32
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
GS88018CT-333
GS88018CT-300
GS88018CT-250
GS88018CT-200
GS88018CT-150
GS88032CT-333
GS88032CT-300
GS88032CT-250
GS88032CT-200
GS88032CT-150
GS88036CT-333
GS88036CT-300
GS88036CT-250
GS88036CT-200
GS88036CT-150
GS88018CGT-333
GS88018CGT-300
GS88018CGT-250
GS88018CGT-200
GS88018CGT-150
GS88032CGT-333
GS88032CGT-300
GS88032CGT-250
GS88032CGT-200
GS88032CGT-150
GS88036CGT-333
GS88036CGT-300
GS88036CGT-250
GS88036CGT-200
GS88036CGT-150
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
Pipeline/Flow Through
TQFP
TQFP
333/4.5
300/5
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
TQFP
250/5.5
200/6.5
150/7.5
333/4.5
300/5
TQFP
TQFP
TQFP
TQFP
TQFP
250/5.5
200/6.5
150/7.5
333/4.5
300/5
TQFP
TQFP
TQFP
TQFP
TQFP
250/5.5
200/6.5
150/7.5
333/4.5
300/5
TQFP
TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
RoHS-compliant TQFP
250/5.5
200/6.5
150/7.5
333/4.5
300/5
250/5.5
200/6.5
150/7.5
333/4.5
300/5
250/5.5
200/6.5
150/7.5
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88018CT-150T.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. T = C = Commercial Temperature Range.
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.04 6/2012
22/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36CT-xxx
9Mb Sync SRAM Datasheet Revision History
Types of Changes
File Name
Revision
Format or Content
• Creation of new datasheet
• Update to MP datasheet
880xxC_r1
880xxC_r1_01
880xxC_r1_02
Content
Content
• Updated Absolute Maximum Ratings
• Deleted conditional text
• Updated Absolute Maximum Ratings
• Added thermal information
• Updated Ordering Information
880xxC_r1_03
Content
Content
• Updated Absolute Maximum Ratings
• Removed Ind Temp references
880xxC_r1_04_Com
Rev: 1.04 6/2012
23/23
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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