GS88136CGT-200_技术文档

GS88118/32/36C(T/D)-xxx

333 MHz–150 MHz

512K x 18, 256K x 32, 256K x 36

9Mb Sync Burst SRAMs

100-pin TQFP & 165-bump BGA

Commercial Temp

2.5 V or 3.3 V V

DD

2.5 V or 3.3 V I/O

Flow Through/Pipeline Reads

Features

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

SCD Pipelined Reads

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP and 165-bump BGA

packages

• RoHS-compliant 100-lead TQFP and 165-bump BGA

packages available

The GS88118C(T/D)/GS88132C(88132CT/D)/GS88136C(T/

D) is a SCD (Single Cycle Deselect) pipelined synchronous

SRAM. DCD (Dual Cycle Deselect) versions are also

available. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers.

Functional Description

Byte Write and Global Write

Applications

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

The GS88118C(T/D)/GS88132C(T/D)/GS88136C(T/D) is a

9,437,184-bit high performance synchronous SRAM with a 2-

bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enable (E1, E2), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Core and Interface Voltages

The GS88118C(T/D)/GS88132C(T/D)/GS88136C(T/D)

operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V

and 2.5 V compatible. Separate output power (V

) pins are

DDQ

used to decouple output noise from the internal circuits and are

3.3 V and 2.5 V compatible.

Parameter Synopsis

-333

-300

-250

-200

-150

Unit

t_KQ

2.5

3.0

2.5

3.3

2.5

4.0

3.0

5.0

3.8

6.7

ns

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

240

280

225

260

195

225

170

195

140

160

mA

t_KQ

4.5

5.0

5.5

6.5

7.5

ns

tCycle

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

180

205

165

190

160

180

140

160

128

145

mA

Rev: 1.04a 10/2012

1/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

GS88118C 100-Pin TQFP Pinout (Package T)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

A

NC

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NC

V

NC

DQPA

DQA

V

DQA

V

NC

V

ZZ

DQ^A

DQA

V

DDQ

V

SS

NC

DQB

512K x 18

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

Top View

V

DDQ

DQB

FT

SS

V

DD

NC

DD

V

SS

DQB

V

DDQ

V

SS

DQA

NC

V

DQB

DQPB

NC

V

SS

V

DDQ

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Note:

Pins marked with NC can be tied to either V or V . These pins can also be left floating.

DD

SS

Rev: 1.04a 10/2012

2/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

GS88132C 100-Pin TQFP Pinout (Package T)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

NC

DQB

DQ^B

V

NC

DQC

DQ^C

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V

DDQ

V

SS

DQB

DQC

DQ^C

DQC

256K x 32

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

V

Top View

V

DDQ

DQB

DQC

FT

V

SS

NC

V

DD

V

NC

DD

ZZ

V

SS

DQ^A

DQA

V

DQD

V

DDQ

V

SS

DQA

DQD

V

SS

V

DDQ

DQA

NC

DQD

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Note:

Pins marked with NC can be tied to either V or V . These pins can also be left floating.

DD

SS

Rev: 1.04a 10/2012

3/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

GS88136C 100-Pin TQFP Pinout (Package T)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

DQPB

DQB

DQPC

DQC

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V

DDQ

V

SS

DQB

DQC

256K x 36

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

V

Top View

V

DDQ

DQB

DQC

FT

V

SS

NC

V

DD

V

NC

DD

ZZ

DQ^A

DQA

V

SS

DQD

V

DDQ

V

SS

DQA

DQD

V

SS

V

DDQ

DQA

DQPA

DQD

DQPD

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Note:

Pins marked with NC can be tied to either V or V . These pins can also be left floating.

DD

SS

Rev: 1.04a 10/2012

4/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

TQFP Pin Description

Symbol

A0, A1

A

Type

Description

I

Address field LSBs and Address Counter preset Inputs

Address Inputs

DQ^A

DQB

DQC

DQD

I/O

Data Input and Output pins

—

No Connect

Byte Write—Writes all enabled bytes; active low

Byte Write Enable for DQA, DQB Data I/Os; active low

Clock Input Signal; active high

NC

I

BW

BA, BB, BC, BD

I

CK

GW

I

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

I

E1

I

Chip Enable; active high

E²

I

Output Enable; active low

G

I

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Scan Test Mode Select

ADV

ADSP, ADSC

ZZ

I

TMS

TDI

I

Scan Test Data In

O

I

Scan Test Data Out

TDO

TCK

FT

Scan Test Clock

I

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Core power supply

I

LBO

V

I

DD

V

I

I/O and Core Ground

SS

V

Output driver power supply

DDQ

Rev: 1.04a 10/2012

5/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

165 Bump BGA—x18 Commom I/O—Top View (Package D)

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

NC

A

E1

BB

NC

E3

BW

ADSC

ADV

A

B

C

D

E

F

NC

A

E2

NC

BA

CK

GW

G

ADSP

A

NC

DQA

NC

A

NC

DQA

ZZ

NC

V

DDQ

SS

DD

SS

DD

DDQ

NC

DQB

MCL

NC

V

NC

G

H

J

NC

G

H

J

FT

NC

DQB

NC

V

NC

DDQ

K

L

NC

V

NC

K

L

NC

M

N

P

R

NC

M

N

P

R

NC

V

NC

TDI

NC

A1

A0

NC

V

NC

DDQ

SS

DDQ

NC

A

TDO

TCK

A

LBO

NC

A

TMS

A

11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch

Rev: 1.04a 10/2012

6/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

165 Bump BGA—x32 Common I/O—Top View (Package D)

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

NC

A

E1

BC

BB

E3

BW

ADSC

ADV

NC

A

B

C

D

E

F

NC

A

E2

BD

BA

CK

GW

G

ADSP

A

NC

V

NC

DDQ

SS

DD

SS

DD

DDQ

DQC

FT

DQC

MCL

DQD

NC

V

DQB

NC

DQB

ZZ

G

H

J

G

H

J

NC

DQD

NC

V

DQA

NC

DQA

NC

DDQ

K

L

V

K

L

M

N

P

R

M

N

P

R

V

NC

TDI

NC

A1

A0

NC

V

SS

DDQ

SS

DDQ

NC

A

TDO

TCK

A

LBO

NC

A

TMS

A

11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch

Rev: 1.04a 10/2012

7/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

165 Bump BGA—x36 Common I/O—Top View (Package D)

1

2

3

4

5

6

7

8

9

10

A

11

A

B

C

D

E

F

NC

A

E1

BC

BB

E3

BW

ADSC

ADV

NC

A

B

C

D

E

F

NC

DQPC

DQC

FT

A

E2

BD

BA

CK

GW

G

ADSP

A

NC

DQPB

DQB

ZZ

NC

V

NC

DDQ

SS

DD

SS

DD

DDQ

DQC

MCL

DQD

NC

V

DQB

NC

G

H

J

G

H

J

NC

DQD

DQPD

NC

V

DQA

NC

DQA

DQPA

A

DDQ

K

L

V

K

L

M

N

P

R

M

N

P

R

V

NC

TDI

NC

A1

A0

NC

V

SS

DDQ

SS

DDQ

NC

A

TDO

TCK

A

LBO

NC

A

TMS

A

11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch

Rev: 1.04a 10/2012

8/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

165-Bump BGA Pin Description

Symbol

A0, A1

A

Type

Description

I

Address field LSBs and Address Counter Preset Inputs

Address Inputs

DQ^A

DQB

DQC

DQD

I/O

Data Input and Output pins

I

—

I

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

No Connect

BA, BB, BC, BD

NC

CK

Clock Input Signal; active high

Byte Write—Writes all enabled bytes; active low

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

I

BW

I

GW

I

E1

I

Chip Enable; active low

E3

I

Chip Enable; active high

E²

I

Output Enable; active low

G

I

Burst address counter advance enable; active l0w

Address Strobe (Processor, Cache Controller); active low

Sleep mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Scan Test Mode Select

ADV

ADSC, ADSP

ZZ

I

FT

I

LBO

TMS

TDI

I

Scan Test Data In

O

I

Scan Test Data Out

TDO

TCK

MCL

Scan Test Clock

—

I

Must Connect Low

V

Core power supply

DD

V

I

I/O and Core Ground

SS

V

Output driver power supply

DDQ

Rev: 1.04a 10/2012

9/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

GS88118/32/36C(T/D) Block Diagram

Register

A0–An

D

Q

A0

A1

D0

Q0

Q1

A1

D1

Counter

Load

A

LBO

ADV

Memory

Array

CK

ADSC

ADSP

Q

D

Register

GW

BW

BA

D

Q

Register

36

D

Q

BB

BC

BD

4

Register

D

Q

Register

D

Q

Register

D

Q

Register

E1

E2

E3

D

Q

Register

D

Q

FT

G

1

Power Down

Control

DQx1–DQx9

ZZ

Note: Only x36 version shown for simplicity.

Rev: 1.04a 10/2012

10/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Byte Write Truth Table

Function

Read

GW

H

BW

H

L

BA

X

BB

X

BC

X

BD

X

Notes

1

Write No Bytes

Write byte a

Write byte b

Write byte c

Write byte d

Write all bytes

H

L

H

L

H

L

H

L

1

H

L

2, 3

H

L

H

L

2, 3

H

L

H

L

2, 3, 4

H

L

H

L

H

L

Write all bytes

L

X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.

2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x32 and x36 versions.

Rev: 1.04a 10/2012

11/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Synchronous Truth Table

State

Diagram

Key

Address

Used

3

Operation

E1

E2

E3

ADSP

ADSC

ADV

W

DQ

Deselect Cycle, Power Down

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

Notes:

None

X

L

H

L

X

H

X

H

X

H

X

H

X

L

H

X

H

X

L

X

L

X

L

H

X

F

T

F

T

F

T

High-Z

None

X

L

X

L

High-Z

None

X

L

High-Z

None

X

H

X

L

High-Z

External

X

L

Q

D

Q

D

Q

D

R

H

X

H

X

H

X

H

X

W

CR

CW

L

H

Current

1. X = Don’t Care, H = High, L = Low

2. E = T (True) if E²= 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.04a 10/2012

12/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Simplified State Diagram

X

Deselect

W

R

W

R

X

R

X

First Write

First Read

CW

CR

W

R

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and

that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

Rev: 1.04a 10/2012

13/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Simplified State Diagram with G

X

Deselect

W

R

W

R

X

W

R

X

First Write

First Read

CR

CW

CR

W

R

W

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.04a 10/2012

14/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

V_DD

Description

Value

Unit

V

Voltage on V_DDPins

Voltage in V_DDQPins

–0.5 to 4.6

V_DDQ

V_I/O1

V_I/O2

V_IN

V

–0.5 to V_DD+0.5 (≤ 4.6 V max.)

Voltage on I/O Pins

V

–0.5 to V_DDQ+0.5 (≤ 4.6 V max.)

–0.5 to V_DD+0.5 (≤ 4.6 V max.)

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

V

I_IN

+/–20

mA

W

I_OUT

P_D

1.5

^oC

T_STG

–55 to 125

T_BIAS

Temperature Under Bias

Notes:

1. Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recom-

mended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect

reliability of this component.

2. Both V

V

must be met.

I/O1 and I/O2

Power Supply Voltage Ranges

Parameter

3.3 V Supply Voltage

Symbol

V_DD3

Min.

3.0

Typ.

3.3

Max.

3.6

Unit

V

V_DD2

2.5 V Supply Voltage

2.3

2.5

2.7

V

3.3 V V_DDQI/O Supply Voltage

V_DDQ3

V_DDQ2

V_DD

3.0

3.3

V

2.5 V V_DDQI/O Supply Voltage

2.3

2.5

V

Note:

V

must be less than or equal to V + 0.3 V at all times.

DD

DDQ

Rev: 1.04a 10/2012

15/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

V

Range Logic Levels

DD3

Parameter

Symbol

V_IH

Min.

2.0

Typ.

—

Max.

Unit

V

V_DD+ 0.3

V_DDQ+ 0.3

Input High Voltage

Input High Voltage for Data I/O pins

Input Low Voltage

V_IH(I/O)1

V_IH(I/O)2

V_IL

2.0

—

V

2.0

—

V

–0.3

—

0.8

V

Notes:

1.

2.

3.

4.

V

(max) must be met for any instantaneous value of V .

DD

IH

(max) must be met for any instantaneous value of V

.

DD

IH(I/O)1

.

IH(I/O)2

DDQ

needs to power-up before or at the same time as V

to make sure V (max) is not exceeded.

IH

DD

DDQ

V

Range Logic Levels

DD2

Parameter

Symbol

V_IH

Min.

Typ.

—

Max.

Unit

V

0.6*V_DD

V

_DD+ 0.3

Input High Voltage

Input High Voltage for Data I/O pins

Input Low Voltage

V_IH(I/O)1

V_IH(I/O)2

V_IL

V_DD+ 0.3

—

V

_DDQ+ 0.3

0.3*V_DD

—

V

–0.3

—

V

Notes:

1.

2.

3.

4.

V

(max) must be met for any instantaneous value of V .

DD

IH

(max) must be met for any instantaneous value of V

.

DD

IH(I/O)1

.

IH(I/O)2

DDQ

needs to power-up before or at the same time as V

to make sure V (max) is not exceeded.

IH

DD

DDQ

Recommended Operating Temperatures

Parameter

Symbol

Min.

Typ.

Max.

Unit

T_A

Ambient Temperature (Commercial Range Versions)

0

25

70

°C

Note:

Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.

Rev: 1.04a 10/2012

16/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Thermal Impedance

Test PCB

Substrate

θ JA (C°/W)

Airflow = 0 m/s

θ JA (C°/W)

Airflow = 1 m/s

θ JA (C°/W)

Airflow = 2 m/s

Package

θ JB (C°/W)

θ JC (C°/W)

100 TQFP

165 BGA

4-layer

38.7

27.4

33.5

24.2

31.9

23.2

27.6

15.3

10.6

7.8

4-layer

Notes:

1. Thermal Impedance data is based on a number of samples from multiple lots and should be viewed as a typical number.

2. Please refer to JEDEC standard JESD51-6.

3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to

the PCB can result in cooling or heating of the RAM depending on PCB temperature.

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V

IH

20% tKC

V

+ 2.0 V

DD

V

SS

50%

V

DD

V

– 2.0 V

SS

20% tKC

V

IL

Note:

Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 2.5 V)

A

DD

Parameter

Symbol

C_IN

Test conditions

V_IN= 0 V

Typ.

Max.

Unit

pF

Input Capacitance

4

6

5

7

C_I/O

V_OUT= 0 V

Input/Output Capacitance

pF

Note:

These parameters are sample tested.

Rev: 1.04a 10/2012

17/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

AC Test Conditions

Parameter

Input high level

Input low level

Conditions

V_DD– 0.2 V

0.2 V

Input slew rate

1 V/ns

V_DD/2

Input reference level

V_DDQ/2

Output reference level

Output load

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

Output Load 1

DQ

*

50Ω

30pF

V

DDQ/2

* Distributed Test Jig Capacitance

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I_IL

V_IN= 0 to V_DD

–1 uA

1 uA

V_DD≥ V_IN≥ V_IH

0 V ≤ V_IN≤ V_IH

–1 uA

1 uA

100 uA

I_IN1

ZZ Input Current

FT Input Current

V_DD≥ V_IN≥ V_IL

0 V ≤ V_IN≤ V_IL

–100 uA

–1 uA

1 uA

I_IN2

I_OL

Output Disable, V_OUT= 0 to V_DD

I_OH= –8 mA, V_DDQ= 2.375 V

I_OH= –8 mA, V_DDQ= 3.135 V

I_OL= 8 mA

Output Leakage Current

Output High Voltage

Output Low Voltage

–1 uA

1.7 V

2.4 V

—

1 uA

—

V_OH2

V_OH3

V_OL

—

0.4 V

Rev: 1.04a 10/2012

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Operating Currents

-333

-300

-250

-200

-150

Parameter

Test Conditions

Mode

Symbol

Unit

0

to 70°C

I_DD

240

40

225

35

195

30

170

25

140

20

Pipeline

mA

I_DDQ

(x32/

x36)

I_DD

Flow

Through

180

25

165

25

155

25

140

20

130

15

Device Selected;

All other inputs

≥V_IHor ≤ V_IL

I_DDQ

Operating

Current

I_DD

220

20

205

20

180

15

155

15

130

10

Pipeline

Output open

I_DDQ

(x18)

I_DD

Flow

Through

165

15

150

15

145

15

130

10

120

8

I_DDQ

I_SB

I_DD

Pipeline

25

70

25

65

25

65

25

65

25

60

mA

Standby

Current

ZZ ≥ V_DD– 0.2 V

—

Flow

Through

Pipeline

Device Deselected;

All other inputs

≥ V_IHor ≤ V_IL

Deselect

Current

Flow

Through

Notes:

1.

2. All parameters listed are worst case scenario.

I

and I

apply to any combination of V , V , V

, and V

operation.

DDQ2

DD

DDQ

DD3 DD2 DDQ3

Rev: 1.04a 10/2012

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

AC Electrical Characteristics

-333

-300

-250

-200

-150

Parameter

Symbol

Unit

Min

3.0

—

Max

—

2.5

—

4.5

—

Min

3.3

—

Max

—

2.5

—

5.0

—

Min

4.0

—

Max

—

2.5

—

5.5

—

Min

5.0

—

Max

—

3.0

—

6.5

—

Min

6.7

—

Max

—

3.8

—

7.5

—

Clock Cycle Time

Clock to Output Valid

Clock to Output Invalid

tKC

tKQ

ns

tKQX

1.5

1.0

0.1

4.5

—

1.5

1.0

0.1

5.0

—

1.5

1.2

0.2

5.5

—

1.5

1.4

0.4

6.5

—

1.5

0.5

7.5

—

Pipeline

tLZ¹

tS

Clock to Output in Low-Z

Setup time

Hold time

tH

Clock Cycle Time

Clock to Output Valid

tKC

tKQ

tKQX

Clock to Output Invalid

2.0

1.3

0.3

1.0

2.0

1.4

0.4

1.0

2.0

1.5

0.5

1.3

2.0

1.5

0.5

1.3

2.0

1.5

0.5

1.5

Flow

Through

tLZ¹

tS

Clock to Output in Low-Z

Setup time

Hold time

tH

Clock HIGH Time

tKH

Clock LOW Time

tKL

1.2

1.5

—

1.2

1.5

—

1.5

—

1.5

—

1.7

1.5

—

ns

Clock to Output in

High-Z

tHZ¹

2.5

3.0

G to Output Valid

G to output in Low-Z

G to output in High-Z

ZZ setup time

tOE

—

0

2.5

—

2.5

—

0

2.5

—

2.5

—

0

2.5

—

2.5

—

0

3.0

—

3.0

—

0

3.8

—

3.8

—

ns

tOLZ¹

tOHZ¹

tZZS²

tZZH²

tZZR

—

5

—

5

—

5

—

5

—

5

ZZ hold time

1

ZZ recovery

20

Notes:

1. These parameters are sampled and are not 100% tested

2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Rev: 1.04a 10/2012

20/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Pipeline Mode Timing

Begin

Read A Cont

Single Read

Cont

Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont

Deselect

Single Write

tKL

Burst Read

tKH

tKC

CK

ADSP

tS

tH

ADSC initiated read

ADSC

ADV

tS

tH

A

B

C

A0–An

GW

tS

tH

BW

tS

Ba–Bd

E1

tS

Deselected with E1

tH

E1 masks ADSP

tH

E2 and E3 only sampled with ADSP and ADSC

E2

E3

G

tS

D(B)

tKQ

tKQX

tHZ

tOE

tOHZ

Q(A)

tH

tLZ

Q(C)

Q(C+1)

Q(C+2) Q(C+3)

DQa–DQd

Rev: 1.04a 10/2012

21/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Flow Through Mode Timing

Begin

Read A Cont

tKH

Cont

Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont

Deselect

tKL

tKC

CK

Fixed High

ADSP

tS

tH

tS

tH

ADSC initiated read

ADSC

ADV

A0–An

GW

tS

tH

tS

tH

A

B

C

tS

tH

tS

tH

BW

tS

tH

Ba–Bd

E1

tS

Deselected with E1

tH

E2 and E3 only sampled with ADSC

E2

tS

tH

E3

G

tH

tS

tKQ

tLZ

tHZ

tOE

tOHZ

D(B)

tKQX

Q(A)

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

Q(C)

DQa–DQd

Rev: 1.04a 10/2012

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of

SB

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

SB

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKH

tKC

tKL

CK

Setup

Hold

ADSP

ADSC

tZZR

tZZS

tZZH

ZZ

Application Tips

Single and Dual Cycle Deselect

SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with

the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually

assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste

bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at

bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.

Rev: 1.04a 10/2012

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output

DD

drivers are powered by V

.

DDQ

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

DD

SS

JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TCK

Test Clock

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

TMS

TDI

Test Mode Select

Test Data In

In controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in

Out response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

TDO

Test Data Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Rev: 1.04a 10/2012

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

·

Boundary Scan Register

·

0

Bypass Register

2

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1

0

·

· · ·

Control Signals

Test Access Port (TAP) Controller

TMS

TCK

* For the value of M, see the BSDL file, which is available at by contacting us at apps@gsitechnology.com.

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Rev: 1.04a 10/2012

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

ID Register Contents

GSI Technology

JEDEC Vendor

ID Code

Not Used

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

0 1 1 0 1 1 0 0 1

0

1

X

0

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

Rev: 1.04a 10/2012

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

1

Run Test Idle

Select DR

Select IR

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

0

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This

occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-

tate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is

loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and

I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and

are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because

the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will

not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the

TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP

operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then

places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with

all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is

still determined by its input pins.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.

Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output

drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-

tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-

ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR

state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-

ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction

EXTEST

Code

000

Description

Notes

1

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

IDCODE

001

1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z

RFU

010

011

TDO.

1

Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

100

101

110

111

1

GSI

RFU

GSI private instruction.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Rev: 1.04a 10/2012

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

JTAG Port Recommended Operating Conditions and DC Characteristics (2.5/3.3 V Version)

Parameter

Symbol

Min.

Max.

Unit Notes

V

0.6 * V

V

+0.3

DD2

2.5 V Test Port Input High Voltage

2.5 V Test Port Input Low Voltage

3.3 V Test Port Input High Voltage

3.3 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

V

1

IHJ2

DD2

V

–0.3

0.3 * V

DD2

ILJ2

V

+0.3

DD3

2.0

–0.3

–300

–1

V

1

IHJ3

V

0.8

V

1

ILJ3

I

1

100

1

uA

V

2

INHJ

I

3

INLJ

I

–1

4

OLJ

V

Test Port Output High Voltage

1.7

—

0.4

—

5, 6

5, 7

5, 8

5, 9

OHJ

V

Test Port Output Low Voltage

—

V

OLJ

V

– 100 mV

DDQ

Test Port Output CMOS High

V

OHJC

V

Test Port Output CMOS Low

—

100 mV

V

OLJC

Notes:

1. Input Under/overshoot voltage must be –2 V < Vi < V

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

2.

V

≤ V ≤ V

ILJ

IN

DDn

3. 0 V ≤ V ≤ V

IN

ILJn

4. Output Disable, V

= 0 to V

DDn

OUT

5. The TDO output driver is served by the V

supply.

DDQ

6.

7.

8.

9.

I

= –4 mA

OHJ

= + 4 mA

OLJ

= –100 uA

= +100 uA

OHJC

OLJC

JTAG Port AC Test Conditions

Parameter

Conditions

JTAG Port AC Test Load

DQ

V

– 0.2 V

Input high level

Input low level

DD

0.2 V

1 V/ns

*

50Ω

30pF

Input slew rate

V

/2

DDQ

V

/2

Input reference level

DDQ

* Distributed Test Jig Capacitance

/2

Output reference level

DDQ

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

Rev: 1.04a 10/2012

29/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

JTAG Port Timing Diagram

tTKC

tTKH

tTKL

TCK

tTH

tTS

TDI

TMS

TDO

tTKQ

tTH

tTS

Parallel SRAM input

JTAG Port AC Electrical Characteristics

Parameter

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

Max

—

Unit

TCK Cycle Time

50

—

ns

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

Boundary Scan (BSDL Files)

20

—

20

10

—

tTH

—

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications

Engineering Department at: apps@gsitechnology.com.

Rev: 1.04a 10/2012

30/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

TQFP Package Drawing (Package T)

θ

L

c

L1

Symbol

Description

Standoff

Min. Nom. Max

A1

A2

b

0.05

1.35

0.20

0.09

0.10

1.40

0.30

—

0.15

1.45

0.40

0.20

22.1

20.1

16.1

14.1

—

Body Thickness

Lead Width

c

Lead Thickness

D

Terminal Dimension 21.9

Package Body 19.9

Terminal Dimension 15.9

22.0

20.0

16.0

14.0

0.65

0.60

1.00

e

D1

E

b

E1

e

Package Body

Lead Pitch

13.9

—

L

Foot Length

Lead Length

Coplanarity

Lead Angle

0.45

—

0.75

—

L1

Y

A1

A2

E1

E

0.10

7°

θ

0°

—

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

Rev: 1.04a 10/2012

31/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Package Dimensions—165-Bump FPBGA (Package D)

A1 CORNER

TOP VIEW

BOTTOM VIEW

A1 CORNER

M

Ø0.10

C

Ø0.25 C A B

Ø0.40~0.60 (165x)

1

2 3 4 5 6 7 8 9 10 11

11 10 9 8

7 6 5 4 3 2 1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

M

N

P

R

A

1.0

10.0

1.0

13±0.05

B

0.20(4x)

SEATING PLANE

C

Rev: 1.04a 10/2012

32/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Ordering Information for GSI Synchronous Burst RAMs

2

Speed

3

1

Org

Type

Package

T

Part Number

A

(MHz/ns)

512K x 18

256K x 32

256K x 36

512K x 18

256K x 32

256K x 36

GS88118CT-333

GS88118CT-300

GS88118CT-250

GS88118CT-200

GS88118CT-150

GS88136CT-333

GS88132CT-300

GS88136CT-250

GS88132CT-200

GS88132CT-150

GS88136CT-333

GS88136CT-300

GS88136CT-250

GS88136CT-200

GS88136CT-150

GS88118CGT-333

GS88118CGT-300

GS88118CGT-250

GS88118CGT-200

GS88118CGT-150

GS88136CGT-333

GS88132CGT-300

GS88136CGT-250

GS88132CGT-200

GS88132CGT-150

GS88136CGT-333

GS88136CGT-300

GS88136CGT-250

GS88136CGT-200

Pipeline/Flow Through

TQFP

333/4.5

300/5

C

TQFP

250/5.5

200/6.5

150/7.5

333/4.5

300/5

TQFP

250/5.5

200/6.5

150/7.5

333/4.5

300/5

TQFP

250/5.5

200/6.5

150/7.5

333/4.5

300/5

TQFP

RoHS-compliant TQFP

250/5.5

200/6.5

150/7.5

333/4.5

300/5

250/5.5

200/6.5

150/7.5

333/4.5

300/5

250/5.5

200/6.5

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88118CT-150T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.04a 10/2012

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

Ordering Information for GSI Synchronous Burst RAMs (Continued)

2

Speed

3

1

Org

Type

Package

T

Part Number

A

(MHz/ns)

256K x 36

512K x 18

256K x 32

256K x 36

512K x 18

256K x 32

256K x 36

GS88136CGT-150

GS88118CD-333

GS88118CD-300

GS88118CD-250

GS88118CD-200

GS88118CD-150

GS88132CD-333

GS88132CD-300

GS88132CD-250

GS88132CD-200

GS88132CD-150

GS88136CD-333

GS88136CD-300

GS88136CD-250

GS88136CD-200

GS88136CD-150

GS88118CGD-333

GS88118CGD-300

GS88118CGD-250

GS88118CGD-200

GS88118CGD-150

GS88132CGD-333

GS88132CGD-300

GS88132CGD-250

GS88132CGD-200

GS88132CGD-150

GS88136CGD-333

GS88136CGD-300

GS88136CGD-250

GS88136CGD-200

GS88136CGD-150

Pipeline/Flow Through

RoHS-compliant TQFP

165 BGA

150/7.5

333/4.5

300/5

C

165 BGA

250/5.5

200/6.5

150/7.5

333/4.5

300/5

165 BGA

250/5.5

200/6.5

150/7.5

333/4.5

300/5

165 BGA

250/5.5

200/6.5

150/7.5

333/4.5

300/5

165 BGA

RoHS-compliant 165 BGA

250/5.5

200/6.5

150/7.5

333/4.5

300/5

250/5.5

200/6.5

150/7.5

333/4.5

300/5

250/5.5

200/6.5

150/7.5

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88118CT-150T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.04a 10/2012

34/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88118/32/36C(T/D)-xxx

9Mb Sync SRAM Datasheet Revision History

Types of Changes

File Name

Revision

Format or Content

• Creation of new datasheet

• Update to MP datasheet

88118C_r1

88118C_r1_01

88118C_r1_02

Content

• Updated Absolute Maximum Ratings

• Deleted conditional text

• Updated Absolute Maximum Ratings

• Added thermal information

• Updated Ordering Information

88118C_r1_03

Content

• Updated Absolute Maximum Ratings

• Removed all Ind Temp references

88118C_r1_04_Com

• (Rev1.04a: Replaced erroneous Sync Truth Table)

Rev: 1.04a 10/2012

35/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS88136CGT-200
厂家：	GSI TECHNOLOGY
描述：	Cache SRAM, 256KX36, CMOS, ROHS COMPLIANT, TQFP-100 静态存储器内存集成电路
文件：	总35页 (文件大小：514K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS88136CGT-200 [GSI]

相关型号：

GS88136CGT-200IV

GS88136CGT-250

GS88136CGT-250I

GS88136CGT-250IT

GS88136CGT-250IV

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GS88136CGT-250T

GS88136CGT-250V

GS88136CGT-250VT

GS88136CGT-300I

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GS88136CT-150IVT