GS881E18TT-11I_技术文档

Preliminary

GS881E18/36T-11/11.5/100/80/66

100-Pin TQFP

Commercial Temp

Industrial Temp

100 MHz–66 MHz

3.3 V V_DD

3.3 V and 2.5 V I/O

512K x 18, 256K x 36 ByteSafe™

8Mb Sync Burst SRAMs

counter may be configured to count in either linear or

1.10 9/2000Features

• FT pin for user-configurable flow through or pipelined

operation

• Dual Cycle Deselect (DCD) operation

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• 3.3 V +10%/–5% core power supply

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• 100-lead TQFP package

DCD Pipelined Reads

The GS881E18//36T is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. SCD (Single Cycle Deselect)

versions are also available. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of

clock.

-11

-11.5

10 ns

-100

-80

-66

Pipeline tCycle 10 ns

10 ns 12.5 ns 15 ns

Byte Write and Global Write

3-1-1-1

t

4.0 ns 4.0 ns 4.0 ns 4.5 ns 5.0 ns

225 mA 225 mA 225 mA 200 mA 185 mA

KQ

DD

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the byte write

control inputs.

I

Flow

Through

2-1-1-1

t

11 ns 11.5 ns 12 ns

15 ns 15 ns 15 ns

14 ns

15 ns

18 ns

20 ns

KQ

tCycle

180 mA 180 mA 180 mA 175 mA 165 mA

I

DD

ByteSafe™ Parity Functions

The GS881E18/36T features ByteSafe data security functions.

See detailed discussion following.

Functional Description

Sleep Mode

Applications

Low power (Sleep mode) is attained through the assertion

(high) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

The GS881E18//36T is a 9,437,184-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Core and Interface Voltages

The GS881E18//36T operates on a 3.3 V power supply, and all

inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

Controls

output power (V

) pins are used to decouple output noise

DDQ

Addresses, data I/Os, chip enables (E1, E2), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

from the internal circuit.

Rev: 1.10 9/2000

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

GS881E18 100-Pin TQFP Pinout

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

A18

NC

V

NC

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

2

3

V

4

DDQ

V

5

SS

NC

6

NC

DQB1

DQB2

DQA9

DQA8

DQA7

7

8

9

512K X 18

Top View

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

V

DDQ

DQA6

DQA5

DQB3

DQB4

FT

V

SS

QE

V

DD

V

DP

DD

ZZ

DQA4

DQA3

V

SS

DQB5

DQB6

V

DDQ

V

SS

DQA2

DQA1

NC

DQB7

DQB8

DQB9

NC

V

SS

V

DDQ

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Rev: 1.10 9/2000

2/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

GS881E36 100-Pin TQFP Pinout

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

DQB9

DQB8

DQB7

DQC9

DQC8

DQC7

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

2

3

V

4

DDQ

V

5

SS

DQB6

DQB5

DQB4

DQB3

6

DQC6

DQC5

DQC4

DQC3

7

8

9

256K x 36

Top View

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

V

DDQ

DQB2

DQB1

DQC2

DQC1

V

FT

SS

QE

V

DD

V

DP

DD

ZZ

DQA1

DQA2

V

SS

DQD1

DQD2

V

DDQ

V

SS

DQA3

DQA4

DQA5

DQA6

DQD3

DQD4

DQD5

DQD6

V

SS

V

DDQ

DQA7

DQA8

DQA9

DQD7

DQD8

DQD9

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Rev: 1.10 9/2000

3/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

TQFP Pin Descriptio

Pin Location

Typ

e

Symbol

Description

37, 36

A0, A1

A2–A17

A18

I

Address field LSBs and Address Counter preset Inputs

35, 34, 33, 32, 100, 99, 82, 81, 44, 45,

46, 47, 48, 49, 50, 92

Address Inputs

80

63, 62, 59, 58, 57, 56, 53, 52

68, 69, 72, 73, 74, 75, 78, 79

13, 12, 9, 8, 7, 6, 3, 2

DQA1–DQA8

DQB1–DQB8

DQC1–DQC8

DQD1–DQD8

I/O

Data Input and Output pins ( x36 Version)

18, 19, 22, 23, 24, 25, 28, 29

DQA9, DQB9,

DQC9, DQD9

51, 80, 1, 30

I/O

Data Input and Output pins

58, 59, 62, 63, 68, 69, 72, 73, 74

8, 9, 12, 13, 18, 19, 22, 23, 24

DQA1–DQA9

DQB1–DQB9

51, 52, 53, 56, 57

75, 78, 79,

NC

—

No Connect

1, 2, 3, 6, 7

25, 28, 29, 30

16

66

DP

QE

I

O

I

Parity Input; 1 = Even, 0 = Odd

Parity Error Out; Open Drain Output

87

BW

Byte Write—Writes all enabled bytes; active low

Byte Write Enable for DQA, DQB Data I/Os; active low

Byte Write Enable for DQC, DQD Data I/Os; active low ( x36 Version)

No Connect (x18 Version)

93, 94

95, 96

89

BA, BB

B^C, BD

NC

I

—

I

CK

Clock Input Signal; active high

88

GW

I

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

98

E1

I

97

E2

I

Chip Enable; active high

86

G

I

Output Enable; active low

83

ADV

ADSP, ADSC

I

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

84, 85

I

Rev: 1.10 9/2000

4/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Typ

e

Pin Location

Symbol

Description

64

ZZ

FT

I

Sleep mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Scan Test Mode Select

14

31

LBO

TMS

TDI

I

38

I

39

I

Scan Test Data In

42

43

TDO

TCK

O

I

Scan Test Data Out

Scan Test Clock

V

15, 41, 65, 91

I

Core power supply

DD

V

5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90

4, 11, 20, 27, 54, 61, 70, 77

I

I/O and Core Ground

SS

V

Output driver power supply

DDQ

Rev: 1.10 9/2000

5/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

GS881E18/36 Block Diagram

Register

A0–An

D

Q

A0

A1

A0

A1

D0

D1

Q0

Q1

Counter

Load

A

LBO

ADV

Memory

Array

CK

ADSC

ADSP

Q

D

Register

GW

BW

BA

D

Q

36

Register

D

Q

BB

BC

BD

4

Register

D

Q

Register

D

Q

Register

36

D

Q

36

32

Register

E1

E2

D

Q

4

36

Parity

Encode

Register

D

Q

4

Parity

Compare

FT

G

36

0

Power Down

Control

DQx0–DQx9

QE

DP

ZZ

Note: Only x36 version shown for simplicity.

Rev: 1.10 9/2000

6/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

ByteSafe™ Parity Functions

This SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow

Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are

reported one clock cycle later. (See Write Parity Error Output Timing Diagram.) The Data Parity Mode (DP) pin must be tied

high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data.

Validity is best established at the data’s destination. The Parity Error Output is an open drain output and drives low to indicate a

parity error. Multiple Parity Error Output pins may share a common pull-up resistor.

Write Parity Error Output Timing Diagram

CK

DQ

D In A

D In B

D In C

D In D

D In E

tKQ

tLZ

tHZ

tKQX

QE

DQ

Err A

Err C

D In A

D In B

D In C

D In D

D In E

tKQ

tLZ

tHZ

tKQX

QE

Err A

Err C

BPR 1999.05.18

Rev: 1.10 9/2000

7/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Mode Pin Functions

Mode Name

Pin Name

State

Function

Linear Burst

Interleaved Burst

Flow Through

Pipeline

L

H or NC

L

Burst Order Control

Output Register Control

Power Down Control

LBO

FT

ZZ

DP

H or NC

L or NC

H

Active

Standby, I = I

DD SB

L

Check for Odd Parity

Check for Even Parity

ByteSafe Data Parity Control

H or NC

Note:

There are pull-up devices on the LBO, DP and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the

chip will operate in the default states as specified in the above table.

Burst Counter Sequences

Linear Burst Sequence

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

1st address

2nd address

3rd address

4th address

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Note: The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Rev: 1.10 9/2000

8/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Byte Write Truth Table

Function

Read

GW

BW

H

L

B

A

B

C

B

D

Notes

1

H

L

X

Read

H

L

H

L

H

L

H

L

1

Write byte a

Write byte b

Write byte c

Write byte d

Write all bytes

L

2, 3

L

H

L

2, 3

L

H

L

2, 3, 4

L

H

L

X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x36 version.

Rev: 1.10 9/2000

9/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Synchronous Truth Table

Operation

State

2

Address

Used

E2

3

4

Diagram

E1

ADSP ADSC ADV

W

DQ

(x36only)

5

Key

Deselect Cycle, Power Down

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

Notes:

None

X

H

L

X

F

T

X

L

X

L

X

L

X

F

T

F

T

F

T

High-Z

None

X

L

H

L

High-Z

External

X

L

Q

D

Q

D

Q

D

R

L

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

W

L

CR

CW

H

Current

H

1. X = Don’t Care, H = High, L = Low.

2. For x36 Version, E = T (True) if E2 = 1; E = F (False) if E2 = 0.

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.10 9/2000

10/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Simplified State Diagram

X

Deselect

W

R

W

R

X

R

X

CR

First Write

First Read

CW

CR

W

R

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1 and E2) and Write (BA, BB, BC, BD, BW, and GW) control

inputs, and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

Rev: 1.10 9/2000

11/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Simplified State Diagram with G

X

Deselect

W

R

W

R

X

W

R

X

CR

First Write

First Read

CR

CW

W

R

W

X

Burst Write

X

Burst Read

CR

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.10 9/2000

12/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Absolute Maximum Ratings

(All voltages reference to V

)

SS

Symbol

Description

Value

Unit

V

Voltage on V Pins

–0.5 to 4.6

DD

V

Voltage in V

Pins

–0.5 to V

V

DDQ

DD

V

Voltage on Clock Input Pin

Voltage on I/O Pins

–0.5 to 6

V

CK

V

–0.5 to V

+0.5 (£ 4.6 V max.)

DDQ

V

I/O

V

–0.5 to V +0.5 (£ 4.6 V max.)

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

V

IN

DD

I

+/–20

mA

W

IN

I

OUT

P

1.5

D

o

T

–55 to 125

C

STG

o

T

Temperature Under Bias

C

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Recommended Operating Conditions

Parameter

Supply Voltage

Symbol

Min.

3.135

2.375

1.7

Typ.

3.3

2.5

—

Max.

Unit

V

Notes

V

3.6

DD

V

I/O Supply Voltage

V

1

2

3

DDQ

DD

V

+0.3

DD

Input High Voltage

V

IH

V

Input Low Voltage

–0.3

0

—

0.8

V

IL

T

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

25

70

85

°C

A

T

–40

25

A

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V £ V

£ 2.375 V

DDQ

(i.e., 2.5 V I/O) and 3.6 V £ V

£ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.

DDQ

2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.

3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of

Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated

for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be –2 V > Vi < V +2 V with a pulse width not to exceed 20% tKC.

DD

Rev: 1.10 9/2000

13/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V_IH

20% tKC

V_DD+ 2.0 V

50%

V_SS

50%

V_DD

V_SS– 2.0 V

20% tKC

V_IL

Capacitance

o

(T = 25 C, f = 1 MHZ, V = 3.3 V)

A

DD

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

pF

C

V = 0 V

IN

Input Capacitance

4

6

5

7

IN

C

V

= 0 V

Input/Output Capacitance

pF

I/O

OUT

Note: These parameters are sample tested.

Package Thermal Characteristics

Rating

Junction to Ambient (at 200 lfm)

Junction to Case (TOP)

Notes:

Layer Board

Symbol

Max

40

Unit

Notes

1,2

R

single

four

—

°C/W

QJA

R

24

1,2

QJA

R

9

3

QJC

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-

ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Rev: 1.10 9/2000

14/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

AC Test Conditions

Parameter

Input high level

Input low level

Conditions

2.3 V

0.2 V

Input slew rate

1 V/ns

Input reference level

Output reference level

Output load

1.25 V

Fig. 1& 2

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output Load 2 for t , t , t and t

LZ HZ OLZ

OHZ

4. Device is deselected as defined by the Truth Table.

Output Load 2

2.5 V

Output Load 1

DQ

225W

DQ

*

50W

VT = 1.25 V

30pF

*

225W

5pF

* Distributed Test Jig Capacitance

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I

V = 0 to V

IN DD

–1 uA

1 uA

IL

V

³ V ³ V

IN

–1 uA

1 uA

300 uA

DD

IH

I

ZZ Input Current

INZZ

0 V £ V £ V

IN

V

³ V ³ V

IN

–300 uA

–1 uA

1 uA

DD

IL

I

Mode Pin Input Current

Output Leakage Current

INM

0 V £ V £ V

IN

IL

Output Disable,

V

I

–1 uA

1 uA

OL

= 0 to V

OUT

DD

V

I

= –8 mA, V

= 2.375 V

Output High Voltage

Output Low Voltage

1.7 V

2.4 V

—

OH

DDQ

V

= 3.135 V

OH

V

I

= 8 mA

OL

0.4 V

OL

Rev: 1.10 9/2000

15/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Operating Currents

-11

-11.5

-100

-80

-66

0

to

–40

to

0

to

–40

to

0

to

–40

to

0

to

–40

to

0

to

–40

to

Parameter

Test Conditions

Symbol

Unit

70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C

I

DD

Device Selected;

All other inputs

³ V or £ V

225

180

30

235

190

40

225

180

30

235

190

40

225

180

30

235

190

40

200

175

30

210

185

40

185

165

30

195

175

40

mA

Pipeline

Operating

Current

IH

IL

I

DD

Output open

Flow-Thru

I

SB

Pipeline

Standby

Current

ZZ ³ V - 0.2V

DD

I

SB

30

40

30

40

30

40

30

40

30

40

Flow-Thru

I

DD

80

90

80

90

80

90

70

80

60

70

Device Deselected;

All other inputs

Pipeline

Deselect

Current

I

DD

³ V or £ V

IH

IL

65

75

65

75

65

75

55

65

50

60

Flow-Thru

Rev: 1.10 9/2000

16/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

AC Electrical Characteristics

-11

-11.5

-100

-80

-66

Parameter

Symbol

Unit

Min Max Min Max Min Max Min Max Min Max

Clock Cycle Time

Clock to Output Valid

Clock to Output Invalid

Clock to Output in Low-Z

tKC

tKQ

10

—

4.0

—

10

—

4.0

—

10

—

4.0

—

12.5

—

4.5

—

15

—

5

ns

Pipeline

tKQX

1.5

—

1

—

tLZ

Clock Cycle Time

Clock to Output Valid

Clock to Output Invalid

Clock to Output in Low-Z

Clock HIGH Time

tKC

tKQ

15.0

—

11.0

—

15.0

—

11.5

—

15.0

—

12.0

—

15.0

—

14.0

—

20

—

18

—

ns

Flow-

Thru

tKQX

3.0

1.7

2

3.0

1.7

2

3.0

2

3.0

2

3.0

2.3

2.5

1.5

—

1

—

tLZ

tKH

tKL

—

Clock LOW Time

—

2.2

1.5

—

2.2

1.5

—

1

Clock to Output in High-Z

G to Output Valid

1.5

—

4.0

1.5

—

4.2

4.5

4.8

tHZ

tOE

1

G to output in Low-Z

G to output in High-Z

0

—

0

—

0

—

0

—

0

—

ns

tOLZ

1

—

4.0

—

4.2

—

4.5

—

4.5

—

4.8

tOHZ

tS

Setup time

Hold time

1.5

0.5

—

2.0

0.5

—

2.0

0.5

—

2.0

0.5

—

2.0

0.5

—

ns

tH

2

ZZ setup time

ZZ hold time

ZZ recovery

5

1

—

5

1

—

5

1

—

5

1

—

5

1

—

ns

tZZS

tZZH

2

tZZR

20

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

Rev: 1.10 9/2000

17/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Write Cycle Timing

Single Write

Burst Write

Deselected

Write

CK

tH

tS

ADSP is blocked by E inactive

tKC

tKL

tKH

ADSP

tH

tS

ADSC initiated write

ADSC

ADV

ADV must be inactive for ADSP Write

tH

tS

WR2

WR3

WR1

A0–An

tS tH

GW

BW

tH

tS

tH

WR3

WR1

WR2

BA–BD

tS

tH

E1 masks ADSP

E1

E2

tS

Deselected with E2

E2 only sampled with ADSP or ADSC

G

tS

tH

Write specified byte for 2A and all bytes for 2B, 2C& 2D

D2C D2D D3A

Hi-Z

D1A

DQA–DQD

D2A

D2B

Rev: 1.10 9/2000

18/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Flow Through Read Cycle Timing

Single Read

Burst Read

tKL

CK

tKH

tS

tH

ADSP is blocked by E inactive

tKC

ADSP

ADSC

ADV

tS tH

ADSC initiated read

tH

tS

Suspend Burst

tS

tH

RD1

RD2

RD3

A0–An

GW

tS

tH

BW

BA–BD

tH

tS

E1 masks ADSP

E¹

tS tH

E2 only sampled with ADSP or ADSC

Deselected with E2

E2

tOHZ

tOE

G

tKQX

tOLZ

Hi-Z

Q2B

Q2c

Q3A

Q1A

Q2A

Q2D

DQA–DQD

tLZ

tHZ

tKQ

Rev: 1.10 9/2000

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Flow Through Read-Write Cycle Timing

Single Write

Burst Read

Single Read

CK

tH

tS

tKC

ADSP is blocked by E inactive

ADSC initiated read

tKH tKL

ADSP

ADSC

ADV

tS tH

tS

tH

RD2

RD1

WR1

A0–An

GW

tS tH

tH

tS

BW

tS

tH

WR1

BA–BD

tS

tH

E1 masks ADSP

E1

E2 only sampled with ADSP and ADSC

E2

tOHZ

tOE

G

tS

D1A

tH

tKQ

Hi-Z

DQA–DQD

Q1A

Q2A

Q2B

Q2c

Q2D

Burst wrap around to it’s initial state

Rev: 1.10 9/2000

20/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Pipelined DCD Read Cycle Timing

Single Read

Burst Read

tKL

CK

tH

tS

ADSP is blocked by E1 inactive

tKC

tKH

tH

ADSP

ADSC

tS

ADSC initiated read

tS

tH

Suspend Burst

ADV

A0–An

GW

tS

tH

RD3

RD1

RD2

tS

tH

BW

B^A–BD

tS tH

E1 masks ADSP

E1

E2

tH

tS

E2 only sampled with ADSP or ADSC

tOE

G

tOHZ

tKQX

Q2A

tKQX

Q3A

tHZ

tOLZ

tLZ

Hi-Z

Q1A

Q2B

Q2D

Q2c

DQA–DQD

tKQ

Rev: 1.10 9/2000

21/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Pipelined DCD Read-Write Cycle Timing

Single Write

Burst Read

Single Read

tKL

CK

ADSP

ADSC

ADV

tS

tH

tKH

tKC

ADSP is blocked by E1 inactive

tS tH

ADSC initiated read

tS

tH

tS

tH

RD2

WR1

RD1

A0–An

tS

GW

BW

tS

tH

tS

WR1

BA–BD

tS tH

E1 masks ADSP

E

1

tS tH

E2 only sampled with ADSP and ADSC

E2

tOE

tOHZ

G

tS

tH

tKQ

Hi-Z

Q1A

D1a

Q2A

Q2B

Q2c

DQA–DQD

Q2D

Rev: 1.10 9/2000

22/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Sleep Mode Timing Diagram

CK

tH

tS

tKC

tKL

tKH

ADSP

ADSC

ZZ

tZZH

tZZS

tZZR

Snooze

Application Tips

Single and Dual Cycle Deselect

SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output

drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there

will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on

dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address

boundary crossings) but greater care must be exercised to avoid excessive bus contention.

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface

standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Some

functions have been modified or eliminated because they can slow the RAM. Nevertheless, the RAM supports 1149.1-1990 TAP

(Test Access Port) Controller architecture, and can be expected to function in a manner that does not conflict with the operation of

Standard 1149.1 compliant devices. The JTAG Port interfaces with conventional TTL / CMOS logic level signaling.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits. To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

DD

SS

Rev: 1.10 9/2000

23/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

JTAG Pin Descriptions

Pin Name I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the

falling edge of TCK.

TCK

Test Clock

In

Test Mode

Select

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state

machine. An undriven TMS input will produce the same result as a logic one input level.

TMS

TDI

In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed

between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP

In Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to

Test Data In

the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input

level.

Output that is active depending on the state of the TAP state machine. Output changes in response to the

falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.

TDO Test Data Out Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

JTAG Port Registers

Overview

The various JTAG registers, refered to as TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS

as TCK is strobed. Each of the TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and

push serial data out on the next falling edge of TCK. When a register is selected it is placed between the TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAMs JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The

flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. Two TAP

instructions can be used to activate the Boundary Scan Register.

Rev: 1.10 9/2000

24/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

JTAG TAP Block Diagram

0

Bypass Register

2

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1 0

·

· · ·

Boundary Scan Register

n

2

1 0

· · · · · · · · ·

TMS

TCK

Test Access Port (TAP) Controller

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

Die

Revision

Code

GSI Technology

JEDEC Vendor

ID Code

I/O

Not Used

Configuration

1

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12

10 9 8 7 6 5 4 3 2 1

0

x36

x18

X

0

1

0

0 1 1 0 1 1 0 0 1

1

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1-

compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor

all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This

device will not perform EXTEST, INTEST or the SAMPLE/PRELOAD command.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

Rev: 1.10 9/2000

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

1

Run Test Idle

Select DR

Select IR

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when

the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices

in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruc-

tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan

Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring con-

tents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm

the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data cap-

ture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O

ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the

TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-

DR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This

functionality is not Standard 1149.1-compliant.

Rev: 1.10 9/2000

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in

the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, this device is not 1149.1-compliant. Neverthe-

less, this RAM’s TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the instruction regis-

ter the RAM responds just as it does in response to the BYPASS instruction described above.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID

register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any

time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the

Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction

EXTEST

Code

000

Description

Notes

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

This RAM does not implement 1149.1 EXTEST function. *Not 1149.1 Compliant *

1

1, 2

1

IDCODE

001

Preloads ID Register and places it between TDI and TDO.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

Forces all RAM output drivers to High-Z.

SAMPLE-Z

010

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

011

1

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1 Compliant *

100

101

110

111

1

GSI

GSI private instruction.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Rev: 1.10 9/2000

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol Min. Max. Unit Notes

V

+0.3

DD

Test Port Input High Voltage

1.7

–0.3

–300

–1

V

1, 2

IHT

V

Test Port Input Low Voltage

0.8

ILT

I

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

1

uA

V

3

4

INTH

I

INTL

I

–1

1

5

OLT

V

2.4

—

0.4

6, 7

6, 8

OHT

V

OLT

Notes:

1. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V with a pulse width not to exceed 20%

DD

tTKC.

3.

V

³ V ³ V

DD

IN

IL

4. 0 V £ V £ V

IN

5. Output Disable, V

= 0 to V

DD

OUT

6. The TDO output driver is served by the V supply.

DD

7.

8.

I

= –4 mA

= +4 mA

OH

OL

JTAG Port AC Test Conditions

Parameter

Input high level

Conditions

2.3 V

JTAG Port AC Test Load

DQ

Input low level

0.2 V

*

Input slew rate

1 V/ns

50W

30pF

Input reference level

Output reference level

1.25 V

V = 1.25 V

T

1.25 V

* Distributed Test Jig Capacitance

Notes:

1. Include scope and jig capacitance.

Rev: 1.10 9/2000

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

JTAG Port Timing Diagram

tTKL

tTKH

tTKC

TCK

tTS tTH

TMS

TDI

TDO

tTKQ

JTAG Port AC Electrical Characteristics

Parameter

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

20

—

10

5

Max

Unit

ns

TCK Cycle Time

—

10

—

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

ns

tTH

5

ns

Rev: 1.10 9/2000

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

GS811E18/36T TQFP Boundary Scan Register

Order

1

x36

x18 Pin

Order

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

x36

x18 Pin

Order

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

x36

x18 Pin

PH = 0

n/a

A9

A8

81

FT

14

16

2

PH = 0

A10

n/a

82

DP

3

44

ADV

ADSP

83

PH = 0

n/a

4

A11

45

46

84

DQD1

DQB5

DQB6

DQB7

DQB8

DQB9

18

19

22

23

24

5

A12

ADSC

G

85

DQD2

DQD3

6

A13

47

86

7

A14

48

BW

87

DQD4

8

A15

49

GW

CK

88

DQD5

9

A16

50

89

DQD6

NC = 1 25

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

x36 = DQA9

NC = 1 51

NC = 1 52

NC = 1 53

NC = 1 56

NC = 1 57

PH = 0

A17

n/a

DQD7

NC = 1 28

DQA8

DQA7

DQA6

DQA5

DQA4

DQA3

DQA2

DQA1

n/a

DQD8

NC = 1 29

92

x36 = DQD9

NC = 1 30

B^A

93

LBO

31

32

33

34

35

36

BB

94

A5

A4

DQA1

DQA2

DQA3

DQA4

58

59

62

63

64

66

68

69

72

73

74

BC

B^D

NC = 1 95

NC = 1 96

A3

E2

E1

A7

A6

97

98

A2

A1

ZZ

99

A0

37

n/a

QE

100

PH = 0

BPR 1999.08.11

DQB1

DQB2

DQB3

DQB4

DQB5

DQB6

DQB7

DQB8

DQA5

DQA6

DQA7

DQA8

DQA9

x36 = DQC9

DQC8

NC = 1

DQB1

1

2

DQC7

3

DQC6

6

DQC5

7

NC = 1 75

NC = 1 78

NC = 1 79

DQC4

8

DQC3

DQB2

9

DQC2

DQB3

12

13

x36 = DQB9

A18

80

DQC1

DQB4

Notes:

1. The Boundary Scan Register contains a number of registers that are not connected to any pin. They default to the value shown at reset.

2. Registers are listed in exit order (i.e. Location 1 is the first out of the TDO pin.

3. NC = No Connect, NA = Not Active, PH = Place Holder (No associated pin)

Rev: 1.10 9/2000

30/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Output Driver Characteristics

120.0

100.0

Pull Down Drivers

80.0

60.0

40.0

VD D Q

20.0

I O u t

0.0

VO u t

VS S

-20.0

-40.0

-60.0

-80.0

-100.0

-120.0

-140.0

Pull Up Drivers

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

V Out (Pull Down)

VDDQ - V Out (Pull Up)

3.6V PD HD

3.3V PD HD

3.1V PD HD

3.1V PU HD

3.3V PU HD

3.6V PU HD

BPR 1999.05.18

Rev: 1.10 9/2000

31/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

TQFP Package Drawing

q

L

c

L1

Symbol

Description

Standoff

Min. Nom. Max

A1

A2

b

0.05

1.35

0.20

0.09

0.10

1.40

0.30

—

0.15

1.45

0.40

0.20

22.1

20.1

16.1

14.1

—

Body Thickness

Lead Width

c

Lead Thickness

D

Terminal Dimension 21.9

Package Body 19.9

Terminal Dimension 15.9

22.0

20.0

16.0

14.0

0.65

0.60

1.00

—

e

D1

E

b

E1

e

Package Body

Lead Pitch

13.9

—

L

Foot Length

Lead Length

Coplanarity

Lead Angle

0.45

—

0.75

—

L1

Y

A1

A2

E1

E

—

0.10

7°

q

0°

—

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

BPR 1999.05.18

Rev: 1.10 9/2000

32/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Ordering Information for GSI Synchronous Burst RAMs

2

Speed

3

1

Org

Type

Package

Status

T

Part Number

A

(MHz/ns)

514K x 18

256K x 36

514K x 18

256K x 36

Notes:

GS881E18T-11

GS881E18T-11.5

GS881E18T-100

GS881E18T-80

GS881E18T-66

GS881E36T-11

GS881E36T-11.5

GS881E36T-100

GS881E36T-80

GS881E36T-66

GS881E18T-11I

GS881E18T-11.5I

GS881E18T-100I

GS881E18T-80I

GS881E18T-66I

GS881E36T-11I

GS881E36T-11.5I

GS881E36T-100I

GS881E36T-80I

GS881E36T-66I

ByteSafe DCD Pipeline/Flow Through

TQFP

100/11

100/11.5

100/12

80/14

C

I

66/18

100/11

100/11.5

100/12

80/14

66/18

100/11

100/11.5

100/12

80/14

I

66/18

I

100/11

100/11.5

100/12

80/14

I

66/18

I

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS881E18TT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.10 9/2000

33/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS881E18/36T-11/11.5/100/80/66

Revision History

Types of Changes

Format or Content

DS/DateRev. Code: Old;

Page;Revisions;Reason

New

• Last Page/Fixed “GSGS..” in Ordering Information Note.

• Fromatted Pin Outs and Pin Description to new small caps.

• Formatted Block diagrams to new small caps.

Format/Typos

• Formatted Timing Diagrams to new small caps.

• Changed “Flow thru” to “Flow Through” in Timing Diagrams.

• Boundary Scan Register/Formatted to new small caps.

• Package Diagram/Changed “Dimesion” to “Dimension”.

GS881E18/36TRev1.04h 5/

1999;

• 5/Fixed pin description table to match pinouts.

• Pin Description/Changed chip enables to match pins.

• Pin Description/Changed pin 80 from NC to Address Input.

1.05 9/1999I

• Pin Description/Rearranged Address Inputs to match order of

Content

Pinout

• Changed I to O for TDO

• Package Diagram/Changed Dimension D Max from 20.1 to

22.1

•

• First Release of 880 F.

GS881E18/36T1.05 9/

1999I;1.05 11/1999J

Content

• Changed order of TQFP Address Inputs to match pinout.

• Changed order of TQFP DATA Input and Output pins to

match pinout.

GS881E18/36T1.05 11/

1999K881E18/36T1.06 1/

200010L

• New GSI Logo.

• Changed all speed bin information (headings, references,

tables, ordering info..) to reflect 150 - 80Mhz

GS881E18/36T1.06 1/

2000L;

GS881E18/36T1.07 3/

2000N;

Content

• Corrections to AC Electrical Characteristics Table -

• Fixed Boundary Scan Register Added Pin 29

GS881E18/36T1.07 3/

2000N;

GS881E18/36T1.08 3/

2000O;

• Removed 150 MHz speed bin

881E GS881E18/36T1.08 3/

2000O;

• Changed 133 MHz and 117 MHz speed bins to 11 ns and

11.5 ns (100 MHz) numbers

• Updated format to comply with Technical Publications

standards

Content/Format

Content

881E183236_r1_09

• Updated Capitance table—removed Input row and changed

Output row to I/O

881E18_r1_09;

881E18_r1_10

Rev: 1.10 9/2000

34/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS881E18TT-11I
厂家：	GSI TECHNOLOGY
描述：	Standard SRAM, 512KX18, 11ns, CMOS, PQFP100 静态存储器内存集成电路
文件：	总34页 (文件大小：467K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS881E18TT-11I [GSI]

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