GS881E32AD-200IT [GSI]

512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs; 512K ×18 ， 256K ×36 9MB同步突发静态存储器


型号：	GS881E32AD-200IT
厂家：	GSI TECHNOLOGY
描述：	512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs 512K ×18 ， 256K ×36 9MB同步突发静态存储器存储内存集成电路静态存储器
文件：	总37页 (文件大小：841K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Revision: 2/3/05

GS881E18/32/36AD

Supplemental Datasheet Information

This supplemental information applies to the GS881E18/36AT datasheet, which you will

find attached to this document. This supplement includes a new package offering (the

165-bump BGA—Package D), as well as an additional organization (x32, which is only

offered in the 165 BGA for this part).

Revision: 2/3/05

GS881E18/32/36AD

Supplemental Datasheet Information

165 Bump BGA—x18 Commom I/O—Top View (Package D)

ADSC

ADV

ADSP

DQA

DDQ

DQB

MCL

DQB

DDQ

TDI

DDQ

TDO

TCK

LBO

TMS

11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch

Revision: 2/3/05

GS881E18/32/36AD

Supplemental Datasheet Information

165 Bump BGA—x32 Common I/O—Top View (Package D)

ADSC

ADV

ADSP

DDQ

DQC

MCL

DQD

DQB

DQD

DQA

DDQ

TDI

DDQ

TDO

TCK

LBO

TMS

11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch

Revision: 2/3/05

GS881E18/32/36AD

Supplemental Datasheet Information

165 Bump BGA—x36 Common I/O—Top View (Package D)

ADSC

ADV

ADSP

DQC

DQB

DDQ

DQC

MCL

DQD

DQB

DQD

DQA

DDQ

TDI

DDQ

TDO

TCK

LBO

TMS

11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch

Revision: 2/3/05

GS881E18/32/36AD

Supplemental Datasheet Information

GS881E18/32/36AD 165-Bump BGA Pin Description

Symbol

A0, A1

Type

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

Address Input

A^17,A18

DQ^A1–DQA9

DQB1–DQB9

DQC1–DQC9

DQD1–DQD9

I/O

Data Input and Output pins

B^A, BB, BC, BD

—

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

No Connect

Clock Input Signal; active high

Byte Write—Writes all enabled bytes; active low

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

E¹

E³

Chip Enable; active low

E²

Chip Enable; active high

Output Enable; active low

ADV

ADSC, ADSP

Burst address counter advance enable; active l0w

Address Strobe (Processor, Cache Controller); active low

Sleep mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Scan Test Mode Select

LBO

TMS

TDI

Scan Test Data In

Scan Test Data Out

TDO

TCK

MCL

Scan Test Clock

—

Must Connect Low

Core power supply

I/O and Core Ground

Output driver power supply

DDQ

Revision: 2/3/05

GS881E18/32/36AD

Supplemental Datasheet Information

Package Dimensions—165-Bump FPBGA (Package D; Variation 1)

TOP

BOTTOM

Ø0.10

Ø0.25 C AB

Ø0.40~0.50

1 2 3 4 5 6 7 8 9 10

11 10 9 8

6 5 4 3 2

1.0

10.

13±0.0

0.20(4

SEATING

Revision: 2/3/05

GS881E18/32/36AD

Supplemental Datasheet Information

Ordering Information

Org

Speed

Type

Package

Status

Part Number

(MHz/ns)

250/5.5

225/6

512K x 18

256K x 32

256K x 36

GS881E18AD-250

GS881E18AD-225

GS881E18AD-200

GS881E18AD-166

GS881E18AD-150

GS881E18AD-133

GS881E32AD-250

GS881E32AD-225

GS881E32AD-200

GS881E32AD-166

GS881E32AD-150

GS881E32AD-133

GS881E36AD-250

GS881E36AD-225

GS881E36AD-200

GS881E36AD-166

GS881E36AD-150

GS881E36AD-133

Pipeline/Flow Through

165 BGA

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

512K x 18 GS881E18AD-250I

512K x 18 GS881E18AD-225I

512K x 18 GS881E18AD-200I

512K x 18 GS881E18AD-166I

512K x 18 GS881E18AD-150I

512K x 18 GS881E18AD-133I

256K x 32 GS881E32AD-250I

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

256K x 32 GS881E32AD-225I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88136AD-100IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

Revision: 2/3/05

GS881E18/32/36AD

Supplemental Datasheet Information

Ordering Information

Org

Speed

Type

Package

Status

Part Number

(MHz/ns)

200/6.5

166/7

256K x 32 GS881E32AD-200I

256K x 32 GS881E32AD-166I

256K x 32 GS881E32AD-150I

256K x 32 GS881E32AD-133I

256K x 36 GS881E36AD-250I

256K x 36 GS881E36AD-225I

256K x 36 GS881E36AD-200I

256K x 36 GS881E36AD-166I

256K x 36 GS881E36AD-150I

Pipeline/Flow Through

165 BGA

150/7.5

133/8.5

250/5.5

225/6

200/6.5

166/7

150/7.5

133/8.5

256K x 36 GS881E36AD-133I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88136AD-100IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

GS881E18/36AT-250/225/200/166/150/133

250 MHz–133 MHz

100-Pin TQFP

Commercial Temp

Industrial Temp

512K x 18, 256K x 36

9Mb Synchronous Burst SRAMs

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Flow Through/Pipeline Reads

Features

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

• Dual Dycle Deselect (DCD) operation

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard package

DCD Pipelined Reads

The GS881E18/36AT is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. SCD (Single Cycle Deselect)

versions are also available. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of

clock.

Functional Description

Applications

The GS881E18/36AT is a 9,437,184-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Controls

Sleep Mode

Addresses, data I/Os, chip enable (E1, E2), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS881E18/36AT operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

2.5 2.7 3.0 3.4 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.7 7.5 ns

tCycle

Curr (x18) 280 255 230 200 185 165 mA

Curr (x36) 330 300 270 230 215 190 mA

Flow

Through

2-1-1-1

5.5 6.0 6.5 7.0 7.5 8.5 ns

tCycle

Curr (x18) 175 165 160 150 145 135 mA

Curr (x36) 200 190 180 170 165 150 mA

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS881E18/36AT-250/225/200/166/150/133

GS881E18A 100-Pin TQFP Pinout (Package T)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

DDQ

DQPA

DQA

DQB

512K x 18

Top View

DDQ

DQA

DQB

DQ^A

DQA

DQB

DQB6

DQA

DDQ

DQB

DQPB

DDQ

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS881E18/36AT-250/225/200/166/150/133

GS881E36A 100-Pin TQFP Pinout (Package T)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

DQPB

DQB

DQPC

DQC

DQB

DQC

DDQ

DQB

DQC

256K x 36

Top View

DDQ

DQB

DQC

DQ^A

DQA

DQD

DDQ

DQA

DQD

DDQ

DQA

DQD

DQA

DQD

DQPA

DQPD

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS881E18/36AT-250/225/200/166/150/133

TQFP Pin Description

Symbol

A0, A1

Aⁿ

Type

Description

Address field LSBs and Address Counter preset Inputs

Address Inputs

DQ^A

DQB

DQC

DQD

I/O

Data Input and Output pins

—

No Connect

Byte Write—Writes all enabled bytes; active low

Byte Write Enable for DQA, DQB Data I/Os; active low

Clock Input Signal; active high

B^A, BB, BC, BD

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

E¹

E²

Chip Enable; active high

Output Enable; active low

ADV

ADSP, ADSC

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Scan Test Mode Select

TMS

TDI

Scan Test Data In

TDO

TCK

Scan Test Data Out

Scan Test Clock

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Core power supply

LBO

I/O and Core Ground

Output driver power supply

DDQ

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS881E18/36AT-250/225/200/166/150/133

GS881E18/36A Block Diagram

^RegisteQ^r

A0–An

Counter

Load

LBO

ADV

Memory

Array

ADSC

ADSP

Parity

Encode

Parity

Compare

Power Down

Control

DQx1–DQx9

Note: Only x36 version shown for simplicity.

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GS881E18/36AT-250/225/200/166/150/133

Mode Pin Functions

Mode Name

Pin Name

State

Function

Linear Burst

Interleaved Burst

Flow Through

Pipeline

Burst Order Control

Output Register Control

Power Down Control

LBO

H or NC

L or NC

Active

Standby, I = I

DD SB

Note:

There are pull-up devices on the ZQ and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip

will operate in the default states as specified in the above tables.

Burst Counter Sequences

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

1st address

2nd address

3rd address

4th address

Note:

The burst counter wraps to initial state on the 5th clock.

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS881E18/36AT-250/225/200/166/150/133

Byte Write Truth Table

Function

Read

Notes

Read

Write byte a

Write byte b

Write byte c

Write byte d

Write all bytes

2, 3

2, 3, 4

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x36 version.

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GS881E18/36AT-250/225/200/166/150/133

Synchronous Truth Table

Operation

State

Diagram

Address Used

ADSP ADSC

ADV

Key

Deselect Cycle, Power Down

Read Cycle, Begin Burst

None

External

High-Z

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

Current

Notes:

1. X = Don’t Care, H = High, L = Low

2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS881E18/36AT-250/225/200/166/150/133

Simplified State Diagram

Deselect

First Write

First Read

Burst Write

Burst Read

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and

that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

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GS881E18/36AT-250/225/200/166/150/133

Simplified State Diagram with G

Deselect

First Write

First Read

Burst Write

Burst Read

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

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GS881E18/36AT-250/225/200/166/150/133

Absolute Maximum Ratings

(All voltages reference to V )

Symbol

Description

Value

Unit

Voltage on V Pins

–0.5 to 4.6

Voltage in V

Pins

DDQ

–0.5 to 4.6

DDQ

–0.5 to V

+0.5 (≤ 4.6 V max.)

DDQ

Voltage on I/O Pins

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

I/O

–0.5 to V +0.5 (≤ 4.6 V max.)

+/–20

OUT

1.5

–55 to 125

STG

Temperature Under Bias

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Power Supply Voltage Ranges

Parameter

Symbol

Min.

3.0

Typ.

3.3

Max.

3.6

Unit

Notes

3.3 V Supply Voltage

2.5 V Supply Voltage

DD3

2.3

2.5

2.7

DD2

3.3 V V

I/O Supply Voltage

3.0

3.3

3.6

DDQ

DDQ3

2.5 V V

I/O Supply Voltage

2.3

2.5

2.7

DDQ2

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS881E18/36AT-250/225/200/166/150/133

Range Logic Levels

Parameter

DDQ3

Symbol

Min.

2.0

Typ.

—

Max.

Unit

Notes

Input High Voltage

+ 0.3

Input Low Voltage

–0.3

2.0

—

0.8

+ 0.3

I/O Input High Voltage

I/O Input Low Voltage

—

1,3

DDQ

IHQ

DDQ

–0.3

—

0.8

DDQ

ILQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

(max) is voltage on V

pins plus 0.3 V.

IHQ

DDQ

Range Logic Levels

Parameter

DDQ2

Symbol

Min.

Typ.

—

Max.

Unit

Notes

Input High Voltage

0.6*V

+ 0.3

Input Low Voltage

0.3*V

–0.3

—

I/O Input High Voltage

I/O Input Low Voltage

0.6*V

+ 0.3

DDQ

—

1,3

DDQ

IHQ

0.3*V

–0.3

—

DDQ

ILQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

(max) is voltage on V

pins plus 0.3 V.

IHQ

DDQ

Recommended Operating Temperatures

Parameter

Symbol

Min.

Typ.

Max.

Unit

°C

Notes

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

–40

°C

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

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GS881E18/36AT-250/225/200/166/150/133

Undershoot Measurement and Timing

Overshoot Measurement and Timing

50% tKC

+ 2.0 V

50%

– 2.0 V

50% tKC

Capacitance

(T = 25 C, f = 1 MHZ, V = 2.5 V)

Parameter

Symbol

Test conditions

Typ.

Max.

Unit

V = 0 V

Input Capacitance

= 0 V

OUT

Input/Output Capacitance

I/O

Note:

These parameters are sample tested.

AC Test Conditions

Parameter

Conditions

– 0.2 V

Input high level

Input low level

0.2 V

1 V/ns

Input slew rate

Input reference level

Output reference level

Output load

DDQ

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

Output Load 1

50Ω

30pF

DDQ/2

* Distributed Test Jig Capacitance

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GS881E18/36AT-250/225/200/166/150/133

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

V = 0 to V

–1 uA

1 uA

≥ V ≥ V

–1 uA

1 uA

100 uA

ZZ Input Current

FT Input Current

IN1

0 V ≤ V ≤ V

≥ V ≥ V

–100 uA

–1 uA

1 uA

IN2

0 V ≤ V ≤ V

Output Disable, V

= 0 to V

Output Leakage Current

Output High Voltage

Output Low Voltage

–1 uA

1.7 V

2.4 V

—

1 uA

—

OUT

DDQ

= –8 mA, V

= 2.375 V

= 3.135 V

OH2

—

OH3

= 8 mA

0.4 V

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GS881E18/36AT-250/225/200/166/150/133

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GS881E18/36AT-250/225/200/166/150/133

AC Electrical Characteristics

-250

-225

-200

-166

-150

-133

Parameter

Symbol

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Clock Cycle Time

tKC

tKQ

4.0

—

2.5

—

5.5

—

4.4

—

2.7

—

6.0

—

5.0

—

3.0

—

6.5

—

6.0

—

3.4

—

7.0

—

6.7

—

3.8

—

7.5

—

7.5

—

1.5

0.5

8.5

—

3.0

1.5

0.5

1.7

—

4.0

—

8.5

—

Clock to Output Valid

Clock to Output Invalid

Pipeline

tKQX

1.5

1.2

0.2

5.5

—

1.5

1.3

0.3

6.0

—

1.5

1.4

0.4

6.5

—

1.5

0.5

7.0

—

1.5

0.5

7.5

—

Clock to Output in Low-Z

tLZ

Setup time

Hold time

Clock Cycle Time

Clock to Output Valid

tKC

tKQ

tKQX

Clock to Output Invalid

3.0

1.5

0.5

1.3

1.5

3.0

1.5

0.5

1.3

1.5

3.0

1.5

0.5

1.3

1.5

3.0

1.5

0.5

1.3

1.5

3.0

1.5

0.5

1.5

1.7

Flow

Through

Clock to Output in Low-Z

tLZ

Setup time

Hold time

Clock HIGH Time

Clock LOW Time

tKH

tKL

Clock to Output in

High-Z

1.5

2.3

1.5

2.5

1.5

3.0

1.5

3.0 1.5 3.0 1.5 3.0

tHZ

G to Output Valid

G to output in Low-Z

G to output in High-Z

ZZ setup time

tOE

—

2.3

—

2.3

—

2.5

—

2.5

—

3.2

—

3.0

—

3.5

—

3.0

—

3.8

—

3.0

—

4.0

—

3.0

—

tOLZ

—

tOHZ

tZZS

ZZ hold time

tZZH

ZZ recovery

tZZR

Notes:

1. These parameters are sampled and are not 100% tested

2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

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GS881E18/36AT-250/225/200/166/150/133

Pipeline Mode Timing

Begin

Read A Cont

Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont

tKL

Deselect Deselect

tKH

tKC

ADSP

ADSC initiated read

ADSC

ADV

Ao–An

Ba–Bd

Deselected with E1

E2 and E3 only sampled with ADSC

D(B)

tKQ

tHZ

tOE

tOHZ

Q(A)

tLZ

tKQX

Hi-Z

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

DQa–DQd

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GS881E18/36AT-250/225/200/166/150/133

Flow Through Mode Timing

Begin

Read A Cont

tKH

Deselect Write B

Read C Read C+1 Read C+2 Read C+3 Read C Deselect

tKL

tKC

Fixed High

ADSP

ADSC initiated read

ADSC

ADV

Ao–An

Ba–Bd

Deselected with E1

E1 masks ADSP

E2 and E3 only sampled with ADSP and ADSC

E1 masks ADSP

tOE

tKQ

tKQX

tHZ

tOHZ

D(B)

tLZ

Q(A)

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

Q(C)

DQa–DQd

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Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKH

tKC

tKL

Setup

Hold

ADSP

ADSC

tZZR

tZZS

tZZH

Application Tips

Single and Dual Cycle Deselect

SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with

the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually

assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste

bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at

bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output

drivers are powered by V

DDQ

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.

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JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TCK

Test Clock

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

TMS

TDI

Test Mode Select

Test Data In

In controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in

Out response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

TDO

Test Data Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

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GS881E18/36AT-250/225/200/166/150/133

JTAG TAP Block Diagram

Boundary Scan Register

Bypass Register

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1

· · ·

Control Signals

Test Access Port (TAP) Controller

TMS

TCK

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

Die

Revision

Code

GSI Technology

JEDEC Vendor

ID Code

I/O

Not Used

Configuration

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

x36

x18

0 1 1 0 1 1 0 0 1

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GS881E18/36AT-250/225/200/166/150/133

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

JTAG Tap Controller State Diagram

Test Logic Reset

Run Test Idle

Select DR

Select IR

Capture DR

Capture IR

Shift DR

Shift IR

Exit1 DR

Exit1 IR

Pause DR

Pause IR

Exit2 DR

Exit2 IR

Update DR

Update IR

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This

occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-

tate testing of other devices in the scan path.

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SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is

loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and

I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and

are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because

the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will

not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the

TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP

operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then

places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with

all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is

still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.

Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output

drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-

tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-

ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR

state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-

ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

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GS881E18/36AT-250/225/200/166/150/133

JTAG TAP Instruction Set Summary

Instruction

EXTEST

IDCODE

Code

000

001

Description

Notes

1, 2

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z

010

011

TDO.

Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

GSI private instruction.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

100

101

110

111

GSI

RFU

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

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JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

2.0

Max.

Unit Notes

+0.3

DD3

3.3 V Test Port Input High Voltage

3.3 V Test Port Input Low Voltage

2.5 V Test Port Input High Voltage

2.5 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

IHJ3

–0.3

0.8

+0.3

ILJ3

0.6 * V

IHJ2

DD2

0.3 * V

–0.3

–300

–1

ILJ2

DD2

INHJ

100

INLJ

–1

OLJ

Test Port Output High Voltage

1.7

—

5, 6

5, 7

5, 8

5, 9

OHJ

Test Port Output Low Voltage

—

0.4

OLJ

– 100 mV

DDQ

Test Port Output CMOS High

—

OHJC

Test Port Output CMOS Low

—

100 mV

OLJC

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < V

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

≤ V ≤ V

ILJ

DDn

3. 0 V ≤ V ≤ V

ILJn

4. Output Disable, V

= 0 to V

DDn

OUT

5. The TDO output driver is served by the V

supply.

DDQ

= –4 mA

OHJ

= + 4 mA

OLJ

= –100 uA

= +100 uA

OHJC

JTAG Port AC Test Conditions

Parameter

Conditions

JTAG Port AC Test Load

– 0.2 V

Input high level

Input low level

0.2 V

1 V/ns

50Ω

Input slew rate

30pF

Input reference level

DDQ

Output reference level

DDQ

* Distributed Test Jig Capacitance

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

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GS881E18/36AT-250/225/200/166/150/133

JTAG Port Timing Diagram

tTKC

tTKH

tTKL

TCK

TDI

tTH

tTS

TMS

TDO

tTKQ

tTH

tTS

Parallel SRAM input

JTAG Port AC Electrical Characteristics

Parameter

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

Max

—

Unit

TCK Cycle Time

—

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

—

tTH

—

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications

Engineering Department at: apps@gsitechnology.com.

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GS881E18/36AT-250/225/200/166/150/133

TQFP Package Drawing (Package T)

Symbol

Description

Standoff

Min. Nom. Max

0.05

1.35

0.20

0.09

0.10

1.40

0.30

—

0.15

1.45

0.40

0.20

22.1

20.1

16.1

14.1

—

Body Thickness

Lead Width

Lead Thickness

Terminal Dimension 21.9

Package Body 19.9

Terminal Dimension 15.9

22.0

20.0

16.0

14.0

0.65

0.60

1.00

Package Body

Lead Pitch

13.9

—

Foot Length

Lead Length

Coplanarity

Lead Angle

0.45

—

0.75

—

0.10

7°

0°

—

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

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GS881E18/36AT-250/225/200/166/150/133

Ordering Information for GSI Synchronous Burst RAMs

Speed

Org

Type

Package

Status

Part Number

(MHz/ns)

512K x 18

256K x 36

512K x 18

256K x 36

GS881E18AT-250

GS881E18AT-225

GS881E18AT-200

GS881E18AT-166

GS881E18AT-150

GS881E18AT-133

GS881E36AT-250

GS881E36AT-225

GS881E36AT-200

GS881E36AT-166

GS881E36AT-150

GS881E36AT-133

GS881E18AT-250I

GS881E18AT-225I

GS881E18AT-200I

GS881E18AT-166I

GS881E18AT-150I

GS881E18AT-133I

GS881E36AT-250I

GS881E36AT-225I

GS881E36AT-200I

GS881E36AT-166I

GS881E36AT-150I

GS881E36AT-133I

DCD Pipeline/Flow Through

TQFP

250/5.5

225/6

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

200/6.5

166/7

150/7.5

133/8.5

250/5.5

225/6

200/6.5

166/7

150/7.5

133/8.5

256K x 36

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS881E18AT-150IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

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GS881E18/36AT-250/225/200/166/150/133

9Mb Sync SRAM Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Page;Revisions;Reason

Format or Content

• Creation of new datasheet

881E18A_r1

• Updated AC Characteristics table

• Updated FT power numbers

• Updated Mb references from 8Mb to 9Mb

• Removed ByteSafe references

881E18A_r1;

Content

• Changed DP pin to NC

881E18A_r1_01

• Updated ZZ recovery time diagram

• Added E2 to pinout (pin 97) and pin description table

• Updated AC Test Conditions table and removed Output Load

2 diagram

• Removed Preliminary banner

881E18A_r1_01;

881E18A_r1_02

Content

• Removed pin locations from pin description table

• Removed BSR table

• Updated format

881E18A_r1_02;

881E18A_r1_03

Format/Content

• Updated timing diagrams

• Updated mechanical drawings

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS881E32AD-200IT [GSI]

相关型号：

GS881E32AD-200T

GS881E32AD-225

GS881E32AD-225I

GS881E32AD-225IT

GS881E32AD-225T

GS881E32AD-250

GS881E32AD-250I

GS881E32AD-250IT

GS881E32AD-250T

GS881E32BD-133I

GS881E32BD-150

GS881E32BD-150I