GS881E32BD-150IT [GSI]
Cache SRAM, 256KX32, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165;型号: | GS881E32BD-150IT |
厂家: | GSI TECHNOLOGY |
描述: | Cache SRAM, 256KX32, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165 静态存储器 内存集成电路 |
文件: | 总39页 (文件大小:1352K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
250 MHz–150 MHz
100-Pin TQFP & 165-bump BGA
Commercial Temp
Industrial Temp
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Features
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP and 165-bump BGA
packages
• RoHS-compliant 100-lead TQFP and 165-bump BGA
packages available
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipelie mode, activating the rising-
edge-triggered Data Outegister.
DCD Pipelined Reads
The GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
is a DCD (Dual ycle Deselect) pipelined synchronous
SRAM. SCD (Single Cycle Deselect) versions are also
available. DCD SRAMs pipeline disable commands to the
same degree as read commands. DCD RAMs hold the deselect
comnd for one full cycle and then begin turning off their
outputs just after the second rising edge of clock.
Functional Description
Byte Write and Global Write
Applications
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
The GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
is a 9,437,184-bit high performance synchronous SRAM wh
a 2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supportinhigh
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) anwrite control inputs (Bx,
BW, GW) are synchronous nd are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with eitheADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Core and Interface Voltages
The GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V
and 2.5 V compatible. Separate output power (V
) pins are
DDQ
used to decouple output noise from the internal circuits and are
3.3 V and 2.5 V compatible.
Paramter Synopsis
-333
-300
-250
-200
-150
Unit
tKQ
2.5
3.0
2.5
3.3
2.5
4.0
3.0
5.0
3.8
6.7
ns
ns
tCycle
Pipeline
3-1-1-1
Curr (x18)
Curr (x32/x36)
250
290
230
265
200
230
170
195
140
160
mA
mA
tKQ
4.5
4.5
5.0
5.0
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
tCycle
Flow Through
2-1-1-1
Curr (x18)
Curr (x32/x36)
200
230
185
210
160
185
140
160
128
145
mA
mA
Rev: 1.04a 3/2009
1/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
GS881E18B 100-Pin TQFP Pinout (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
NC
NC
NC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
V
V
NC
DQPA
DQA
DQA
V
V
DQA
DQA
V
NC
VDD
ZZ
DQA
DQA
V
V
DQA
DQA
NC
V
DDQ
DDQ
V
SS
SS
NC
NC
DQB
DQB
512K x 18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
6
7
28
29
30
V
SS
SS
Top View
V
DDQ
DDQ
DQB
DQB
FT
VDD
NC
SS
V
SS
DQB
DQB
V
DDQ
DDQ
V
SS
SS
DQB
DQB
DQPB
NC
NC
V
V
NC
NC
NC
V
SS
SS
V
DDQ
DDQ
NC
N
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either V or V . These pins can also be left floating.
DD
SS
Rev: 1.04a 3/2009
2/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
GS881E32B 100-Pin TQFP Pinout (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
DQB
DQB
V
NC
DQC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
DDQ
DDQ
V
V
SS
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
256K x 32
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
6
7
28
29
30
V
SS
SS
V
Top View
V
DDQ
DDQ
DQB
DQB
DQC
DQC
FT
V
SS
NC
V
DD
V
NC
DD
ZZ
V
SS
DQA
DQA
V
DQD
DQD
V
DDQ
DDQ
V
V
SS
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
SS
V
V
DDQ
DDQ
DQA
DQA
NC
DQD
DQ
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either V or V . These pins can also be left floating.
DD
SS
Rev: 1.04a 3/2009
3/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
GS881E36B 100-Pin TQFP Pinout (Package T)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPB
DQB
DQB
DQPC
DQC
DQC
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
V
DDQ
DDQ
V
V
SS
SS
DQB
DQB
DQB
DQB
DQC
DQC
DQC
DQC
256K x 36
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
6
7
28
29
30
V
SS
SS
V
Top View
V
DDQ
DDQ
DQB
DQB
DQC
DQC
FT
V
SS
NC
V
DD
V
NC
DD
ZZ
DQA
DQA
V
SS
DQD
DQD
V
V
DDQ
DDQ
V
V
SS
SS
DQA
DQA
DQA
DQA
DQD
DQD
DQD
DQD
V
V
SS
SS
V
V
DDQ
DDQ
DQA
DQA
DQPA
DQD
DQ
DQPD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either V or V . These pins can also be left floating.
DD
SS
Rev: 1.04a 3/2009
4/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
TQFP Pin Description
Symbol
A0, A1
A
Type
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
I
I
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
NC
—
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ Data I/Os; active low
No Connect
BW
I
BA, BB, BC, BD
I
NC
—
CK
I
I
I
I
I
I
I
I
I
I
Clock Input Signal; active high
GW
Global Write Enable—Writes all bytes; active low
Chip Enable; active high
E2
E1
Chip Enable; active low
G
ADV
Output Enable; active low
Burst addrecounter advance enable; active low
AddresStrobe (Processor, Cache Controller); active low
Sleep Mode control; active high
ADSP, ADSC
ZZ
LBO
Linear Burst Order mode; active low
Core power supply
V
DD
V
I
I
I/O and Core Ground
SS
V
Output driver power supply
DDQ
Rev: 1.04a 3/2009
5/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
E1
BB
NC
E3
BW
ADSC
ADV
A
A
A
B
C
D
E
F
NC
NC
A
E2
NC
BA
CK
GW
G
ADSP
A
NC
NC
NC
NC
NC
NC
DQA
DQA
DQA
DQA
NC
A
NC
DQA
DQA
DQA
DQA
DQA
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
D
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DQB
DQB
DQB
DQB
MCL
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
NC
G
H
J
NC
G
H
J
FT
NC
NC
DQB
DQB
DQB
DQB
DQB
NC
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
NC
V
V
V
V
V
V
V
V
NC
K
L
NC
NC
M
N
P
R
NC
NC
M
N
P
R
NC
V
NC
TDI
NC
A1
A0
NC
V
NC
DDQ
SS
SS
DDQ
NC
A
A
A
TDO
TCK
A
A
A
A
LBO
NC
A
TMS
A
A
A
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.04a 3/2009
6/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
165 Bump BGA—x32 Common I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
E1
BC
BB
E3
BW
ADSC
ADV
A
NC
A
B
C
D
E
F
NC
NC
A
E2
BD
BA
CK
GW
G
ADSP
A
NC
NC
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
D
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
DQC
DQC
DQC
DQC
FT
DQC
DQC
DQC
DQC
MCL
DQD
DQD
DQD
DQD
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQB
DQB
DQB
DQB
NC
DQB
DQB
DQB
DQB
ZZ
G
H
J
G
H
J
NC
NC
DQD
DQD
DQD
DQD
NC
V
V
DQA
DQA
DQA
DQA
NC
DQA
DQA
DQA
DQA
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
V
V
V
V
V
V
V
V
K
L
M
N
P
R
M
N
P
R
V
NC
TDI
NC
A1
A0
NC
V
SS
DDQ
SS
DDQ
NC
NC
A
A
A
TDO
TCK
A
A
A
A
A
LBO
NC
A
TMS
A
A
A
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.04a 3/2009
7/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
165 Bump BGA—x36 Common I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
A
E1
BC
BB
E3
BW
ADSC
ADV
A
NC
A
B
C
D
E
F
NC
DQPC
DQC
DQC
DQC
DQC
FT
A
E2
BD
BA
CK
GW
G
ADSP
A
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
D
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
DQC
DQC
DQC
DQC
MCL
DQD
DQD
DQD
DQD
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQB
DQB
DQB
DQB
NC
G
H
J
G
H
J
NC
NC
DQD
DQD
DQD
DQD
DQPD
NC
V
V
DQA
DQA
DQA
DQA
NC
DQA
DQA
DQA
DQA
DQPA
A
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
V
V
V
V
V
V
V
V
K
L
M
N
P
R
M
N
P
R
V
NC
TDI
NC
A1
A0
NC
V
SS
DDQ
SS
DDQ
NC
A
A
A
TDO
TCK
A
A
A
A
LBO
NC
A
TMS
A
A
A
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.04a 3/2009
8/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
GS881E18/32/36BD 165-Bump BGA Pin Description
Symbol
A0, A1
A
Type
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I
I
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA, BB, BC, BD
I
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active ow
No Connect
NC
CK
Clock Input Signal; active h
Byte Write—Writes all enabled bytes; ctive low
Global Write Enable—Writes all bytes; active low
Chip Enable; ctive low
BW
I
GW
I
E1
I
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Out Enable; active low
ADV
ADSC, ADSP
ZZ
I
Burst address counter advance enable; active l0w
Address obe (Processor, Cache Controller); active low
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Scan Test Mode Select
I
I
FT
I
LBO
TMS
TDI
I
I
I
Scan Test Data In
O
I
Scan Test Data Out
TDO
TCK
MCL
Scan Test Clock
—
I
Must Connect Low
V
Core power supply
DD
V
I
I
I/O and Core Ground
SS
V
Output driver power supply
DDQ
Rev: 1.04a 3/2009
9/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
GS881E18/32/36B Block Diagram
Register
A0–An
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
36
36
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E2
E3
D
Q
Register
D
Q
FT
G
1
Power Down
Control
DQx1–DQx9
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.04a 3/2009
10/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Mode Pin Functions
Mode Name
Pin Name
State
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
L
Burst Order Control
LBO
H
L
H or NC
L or NC
H
Output Register Control
FT
ZZ
Active
Power Down Control
Standby, I = I
DD SB
L
Dual Cycle Dselect
Single Cycle Deselect
Single/Dual Cycle Deselect Control
FLXDrive Output Impedance Control
9th Bit Enable
SCD
ZQ
H or NC
L
Drive (Low Impedance)
H or NC
L or NC
H
Low Drive (High Impedance)
Activate DQPx I/Os (x18/x3672 mode)
Deactivate DQPx I/Os (x16/x3272 mode)
PE
Note:
There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note:
The burst counter wraps to initil state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.04a 3/2009
11/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
BA
X
BB
X
BC
X
BD
X
Notes
1
Write No Bytes
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
H
H
L
H
H
L
H
H
H
L
H
H
H
L
1
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
Write all bytes
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.04a 3/2009
12/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Synchronous Truth Table
Operation
State
Diagram
Address
Used
3
E1
E2
E3
ADSP ADSC ADV
W
DQ
Key
X
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
None
None
L
L
L
L
H
L
X
L
H
X
H
X
X
L
X
X
L
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
X
High-Z
None
X
X
L
X
X
L
High-Z
None
X
L
High-Z
None
X
X
H
H
H
X
X
X
X
X
X
X
X
X
L
High-Z
External
External
External
Next
R
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
R
L
L
X
H
X
H
X
H
X
H
L
L
X
X
X
X
X
X
X
X
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
Write Cycle, Suspend Burst
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous inG can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronour synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.04a 3/2009
13/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.04a 3/2009
14/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.04a 3/2009
15/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 4.6
DD
DD
V
Voltage in V
Pins
DDQ
–0.5 to 4.6
V
DDQ
V
–0.5 to V
+0.5 ( 4.6 V max.)
DDQ
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
I/O
V
–0.5 to V +0.5 ( 4.6 V max.)
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 1
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter
Symbol
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
V
3.3 V Supply Voltage
2.5 V Supply Voltage
V
V
V
V
DD3
V
2.3
2.5
2.7
DD2
3.3 V V
I/O Supply Voltage
V
3.0
3.3
3.6
DDQ
DDQ
DDQ3
2.5 V V
I/O Supply Voltage
V
2.3
2.5
2.7
DDQ2
Notes:
1. The part numbers of Industrial emperature Range versions end the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for orst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Rev: 1.04a 3/2009
16/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
V
Range Logic Levels
Parameter
DDQ3
Symbol
Min.
2.0
Typ.
—
Max.
Unit
Notes
V
Input High Voltage
V
V
+ 0.3
DD
V
V
V
V
1
DD
IH
V
Input Low Voltage
V
–0.3
2.0
—
0.8
+ 0.3
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
V
—
1,3
1,3
DDQ
IHQ
DDQ
V
V
–0.3
—
0.8
DDQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, witulse width not to exceed 20% tKC.
DDn
3.
V
(max) is voltage on V
pins plus 0.3 V.
DDQ
IHQ
V
Range Logic Levels
Parameter
DDQ2
Symbol
Min.
Typ.
—
Max.
Unit
Notes
V
Input High Voltage
V
0.6*V
V
+ 0.3
DD
V
V
V
V
1
DD
IH
DD
V
Input Low Voltage
V
0.3*V
DD
–0.3
—
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
0.6*V
V
+ 0.3
DDQ
—
1,3
1,3
DDQ
IHQ
DD
V
V
0.3*V
DD
–0.3
—
DDQ
LQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case n the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
3.
V
(max) is voltage on V
pins plus 0.3 V.
DDQ
IHQ
Recommended Operating Temperatures
Paameter
Symbol
Min.
0
Typ.
25
Max.
70
Unit
C
Notes
T
Ambient Temperature (Commercial Range Versions)
2
2
A
T
Ambient Temperature (Industrial Range Versions)
–40
25
85
C
A
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
Rev: 1.04a 3/2009
17/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
50% tKC
V
+ 2.0 V
50%
DD
V
SS
50%
V
DD
V
– 2.0 V
SS
50% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V
= 0 V
Input Capacitance
4
6
5
7
IN
IN
C
V
OUT
= 0 V
Input/Output Capacitance
pF
I/O
Note:
These parameters are sample tested.
AC Test Conditions
Parameter
Conditions
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
/2
Input slew rate
V
Input reference level
DD
V
/2
Output reference level
Output load
DDQ
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specifiwith output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
*
50
30pF
V
DDQ/2
* Distributed Test Jig Capacitance
Rev: 1.04a 3/2009
18/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
V
V V
IN
–1 uA
–1 uA
1 uA
100 uA
DD
IH
IH
I
ZZ Input Current
IN1
0 V V V
IN
V
V V
IN
–100 uA
–1 uA
1 uA
1 uA
DD
IL
IL
I
FT, SCD, ZQ Input Current
IN2
0 V V V
IN
I
Output Disable, V
= 0 to V
DD
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
–1 uA
1.7 V
2.4 V
—
1 uA
—
OL
OUT
DDQ
DDQ
V
I
I
= –8 mA, V
= –8 mA, V
= 2.375 V
= 3.135
OH2
OH
OH
V
—
OH3
V
I
= 8 mA
OL
0.4 V
OL
Rev: 1.04a 3/2009
19/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Operating Currents
-333
–40
to
-300
–40
to
-250
–40
to
-200
–40
to
-150
–40
to
0
to
0
to
0
to
0
to
0
to
Parameter
Test Conditions
Mode
Symbol
Unit
70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C
IDD
250
40
270
40
230
35
250
35
200
30
220
30
170
25
190
25
140
20
160
20
Pipeline
mA
mA
mA
mA
IDDQ
(x32/
x36)
IDD
Flow
Through
205
25
225
25
185
25
205
25
160
25
180
25
140
20
160
20
130
15
150
15
Device Selected;
All other inputs
VIH or VIL
IDDQ
Operating
Current
IDD
230
20
250
20
210
20
230
20
185
15
205
15
155
15
175
130
10
150
10
Pipeline
Output open
IDDQ
(x18)
IDD
Flow
Through
185
15
205
15
170
15
190
15
145
15
165
130
10
150
10
120
8
140
8
IDDQ
ISB
ISB
IDD
IDD
Pipeline
40
40
95
65
50
50
40
40
90
60
50
50
95
65
40
40
85
60
5
50
90
65
40
40
75
50
50
50
80
55
40
40
60
50
50
50
65
55
mA
mA
mA
mA
Standby
Current
ZZ VDD – 0.2 V
—
—
Flow
Through
Pipeline
100
60
Device Deselected;
All other inputs
VIH or VIL
Deselect
Current
Flow
Through
Notes:
1.
2. All parameters listed are worst case scenario.
I
and I
apply to any combination of V , V , V
, and V
operation.
DDQ2
DD
DDQ
DD3 DD2 DDQ3
Rev: 1.04a 3/2009
20/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
AC Electrical Characteristics
-333
-300
-250
-200
-150
Parameter
Symbol
Unit
Min
3.0
—
Max
—
2.5
—
—
—
—
—
4.5
—
—
—
—
—
Min
3.3
—
Max
—
2.5
—
—
—
—
—
5.0
—
—
—
—
—
Min
4.0
—
Max
—
2.5
—
—
—
—
—
—
—
—
—
—
Min
5.0
—
Max
—
3.0
—
—
—
—
—
6.5
—
—
—
—
—
Min
6.7
—
Max
—
3.8
—
—
—
—
—
7.5
—
—
—
—
—
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
tKC
tKQ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
1.5
1.5
1.0
0.1
4.5
—
1.5
1.5
1.0
0.1
5.0
—
1.5
1.5
1.2
0.2
5.5
—
1.5
1.5
1.4
0.4
6.5
—
1.5
1.5
1.5
0.5
7.5
—
Pipeline
tLZ1
tS
Clock to Output in Low-Z
Setup time
Hold time
tH
Clock Cycle Time
Clock to Output Valid
tKC
tKQ
tKQX
Clock to Output Invalid
2.0
2.0
1.3
0.3
1.0
2.0
2.0
1.4
0.4
1.0
2.0
2.0
1.5
0.5
1.3
2.0
2.0
1.5
0.5
1.3
2.0
2.0
1.5
0.5
1.5
Flow
Through
tLZ1
tS
Clock to Output in Low-Z
Setup time
Hold time
tH
Clock HIGH Time
tKH
Clock LOW Time
tKL
1.2
1.5
—
1.2
1.5
—
1.5
1.5
—
1.5
1.5
—
1.7
1.5
—
ns
ns
Clock to Output in
High-Z
tHZ1
2.5
2.5
2.5
3.0
3.0
G to Output Valid
G to output in Low-Z
G to output in High-Z
ZZ setup time
tOE
—
0
.5
—
2.5
—
—
—
—
0
2.5
—
2.5
—
—
—
—
0
2.5
—
2.5
—
—
—
—
0
3.0
—
3.0
—
—
—
—
0
3.8
—
3.8
—
—
—
ns
ns
ns
ns
ns
ns
tOLZ1
tOHZ1
tZZS2
tZZH2
tZZR
—
5
—
5
—
5
—
5
—
5
ZZ hold time
1
1
1
1
1
ZZ recovery
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. owever, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above
Rev: 1.04a 3/2009
21/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Pipeline Mode Timing (DCD)
Begin
Read A Cont
Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont
tKL
Deselect Deselect
tKH
tKC
CK
ADSP
tS
tS
ADSC initiated read
tH
ADSC
ADV
tS
tH
tH
A
B
C
Ao–An
GW
tS
tS
tH
tH
BW
tS
Ba–Bd
E1
tS
tS
tS
Deselected with E1
tH
E2 and E3 oy sampled with ADSC
tH
tH
E2
E3
G
tS
D(B)
tKQ
tHZ
tOE
tOHZ
Q(A)
tH
tLZ
tKQX
Hi-Z
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
DQa–DQd
Rev: 1.04a 3/2009
22/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Flow Through Mode Timing (DCD)
Begin
Read A Cont
tKH
Deselect Write B
tKC
Read C Read C+1 Read C+2 Read C+3 Read C Deselect
tKL
CK
Fixed High
ADSP
tS
tH
tS
tH
ADSC initiated read
ADSC
ADV
Ao–An
GW
tH
tS
tS
tH
tS
tH
A
B
C
tS
tH
tS
tH
BW
tH
tS
Ba–Bd
E1
tS
Deselected with E1
tH
E1 masks ADSP
tS
tH
E2 and E3 nly sampled with ADSP and ADSC
E1 masks ADSP
E2
tS
tH
E3
G
tH
tS
tOE
tKQ
tKQX
tHZ
tOHZ
D(B)
tLZ
Q(A)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
Q(C)
DQa–DQd
Rev: 1.04a 3/2009
23/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Delect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
Setup
Hold
ADSP
ADSC
tZZR
tZZS
tZZH
ZZ
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy ad cycles” (read cycles that are launched normally but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there
will be no bus contention in ansitions from reads to writes or between banks of RAMs. DCD SRAMs (like this one) do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DDQ
Rev: 1.04a 3/2009
24/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
JTAG Port Registers
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is tut side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional iEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-gic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Poto another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Rev: 1.04a 3/2009
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© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
JTAG TAP Block Diagram
·
·
·
·
·
·
·
·
Boundary Scan Register
·
·
·
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1
0
·
· · ·
Control Sig
Test Access rt (TAP) Controller
TMS
TCK
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR stateBit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.04a 3/2009
26/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Tap Controller Instruction Set
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
Configuration
ID Code
I/O
Not Used
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
1
1
1
x36
x32
x18
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
X
0
1
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
X
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Registes placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controllemoved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.04a 3/2009
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© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
Exit1 DR
xit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
UpdaDR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is oved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into thBoundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Rev: 1.04a 3/2009
28/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction ihe default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are fd to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 1.04a 3/2009
29/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
V
– 0.2 V
Input high level
Input low level
DQ
DD
0.2 V
1 V/ns
*
50
Input slew rate
30pF
V
V
/2
Input reference level
DDQ
V
/2
DDQ
/2
Output reference level
DDQ
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG TAP Instruction Set Summary
Instruction
EXTEST
Code
000
Description
Notes
1
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it betwn TDI and TDO.
IDCODE
001
1, 2
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
010
011
TDO.
1
1
Forces all RAM output drives to High-Z.
Do not use this instructioReserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
SAMPLE/
PRELOAD
Captures I/O ring cntents. Places the Boundary Scan Register between TDI and
TDO.
100
101
110
111
1
1
1
1
GSI
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Reples BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.04a 3/2009
30/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
2.0
Max.
Unit Notes
V
V
V
+0.3
DD3
3.3 V Test Port Input High Voltage
3.3 V Test Port Input Low Voltage
2.5 V Test Port Input High Voltage
2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
V
V
1
1
IHJ3
V
–0.3
0.8
+0.3
ILJ3
V
0.6 * V
V
1
IHJ2
DD2
DD2
V
0.3 * V
1
–0.3
–300
–1
V
1
ILJ2
DD2
I
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
Test Port Output High Voltage
1.7
—
5, 6
5, 7
5, 8
5, 9
OHJ
V
Test Port Output Low Voltage
—
0.4
V
OLJ
V
V
– 100 mV
DDQ
Test Port Output CMOS High
—
V
OHJC
V
Test Port Output CMOS Low
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
V V
ILJ
IN
DDn
ILJn
3. 0 V V V
IN
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V
supply.
DDQ
6.
7.
8.
9.
I
I
I
I
= –4 mA
OHJ
= + 4 mA
OLJ
= –100 uA
= +100 uA
OHJC
OLJC
Rev: 1.04a 3/2009
31/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
TDI
tTH
tTH
tTS
tTS
TMS
TDO
tTKQ
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
Max
Unit
ns
TCK Cycle Time
50
—
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
ns
20
20
10
10
ns
—
ns
—
ns
tT
—
ns
Boundary Scan (BSDL Files)
For information regarding Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
Rev: 1.04a 3/2009
32/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
TQFP Package Drawing (Package T)
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
0.10
7
0
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protusion.
Rev: 1.04a 3/2009
33/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Package Dimensions—165-Bump FPBGA (Package D)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.60 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
1.0
13±0.05
B
0.20(4x)
SEATING PLANE
C
Rev: 1.04a 3/2009
34/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
333/4.5
300/5
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 32
256K x 32
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 32
256K x 32
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
GS881E18BT-333
GS881E18BT-300
GS881E18BT-250
GS881E18BT-200
GS881E18BT-150
GS881E32BT-333
GS881E32BT-300
GS881E32BT-250
GS881E32BT-200
GS881E32BT-150
GS881E36BT-333
GS881E36BT-300
GS881E36BT-250
GS881E36BT-200
GS881E36BT-150
GS881E18BT-333I
GS881E18BT-230I
GS881E18BT-250I
GS881E18BT-200I
GS881E18BT-150I
GS881E32BT-333I
GS881E32BT-300I
GS881E32BT-250I
GS881E32BT-200I
GS881E3T-150I
GS881E36BT-333I
GS881E36BT-300I
GS881E36BT-250I
GS881E36BT-200I
GS881E36BT-150I
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Though
DCD Pipeline/Flow Through
DCD Pipeline/Fw Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQ
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
250/5.5
200/6.5
150/7.5
333/4.5
300/5
250/5.5
200/6.5
150/7.5
333/4.5
300/5
250/5.5
200/6.5
150/7.5
333/4.5
300/5
I
250/5.5
200/6.5
150/7.5
333/4.5
300/5
I
I
I
I
I
250/5.5
200/6.5
150/7.5
333/4.5
300/5
I
I
I
I
I
250/5.5
200/6.5
150/7.5
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS881E18BT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.04a 3/2009
35/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Ordering Information for GSI Synchronous Burst RAMs (Continued)
2
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
333/4.5
300/5
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 32
256K x 32
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 32
256K x 32
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
GS881E18BGT-333
GS881E18BGT-300
GS881E18BGT-250
GS881E18BGT-200
GS881E18BGT-150
GS881E32BGT-333
GS881E32BGT-300
GS881E32BGT-250
GS881E32BGT-200
GS881E32BGT-150
GS881E36BGT-333
GS881E36BGT-300
GS881E36BGT-250
GS881E36BGT-200
GS881E36BGT-150
GS881E18BGT-333I
GS881E18BGT-230I
GS881E18BGT-250I
GS881E18BGT-200I
GS881E18BGT-150I
GS881E32BGT-333I
GS881E32BGT-300I
GS881E32BGT-250I
GS881E32BGT-200I
GS881E32GT-150I
GS881E36BGT-333I
GS881E36BGT-300I
GS881E36BGT-250I
GS881E36BGT-200I
GS881E36BGT-150I
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Though
DCD Pipeline/Flow Through
DCD Pipeline/Fw Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-ComTQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
RoHS-Compliant TQFP
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
250/5.5
200/6.5
150/7.5
333/4.5
300/5
250/5.5
200/6.5
150/7.5
333/4.5
300/5
250/5.5
200/6.5
150/7.5
333/4.5
300/5
I
250/5.5
200/6.5
150/7.5
333/4.5
300/5
I
I
I
I
I
250/5.5
200/6.5
150/7.5
333/4.5
300/5
I
I
I
I
I
250/5.5
200/6.5
150/7.5
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS881E18BT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.04a 3/2009
36/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Ordering Information for GSI Synchronous Burst RAMs (Continued)
2
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
333/4.5
300/5
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 32
256K x 32
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 32
256K x 32
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
GS881E18BD-333
GS881E18BD-300
GS881E18BD-250
GS881E18BD-200
GS881E18BD-150
GS881E32BD-333
GS881E32BD-300
GS881E32BD-250
GS881E32BD-200
GS881E32BD-150
GS881E36BD-333
GS881E36BD-300
GS881E36BD-250
GS881E36BD-200
GS881E36BD-150
GS881E18BD-333I
GS881E18BD-300I
GS881E18BD-250I
GS881E18BD-200I
GS881E18BD-150I
GS881E32BD-333I
GS881E32BD-300I
GS881E32BD-250I
GS881E32BD-200I
GS881E3D-150I
GS881E36BD-333I
GS881E36BD-300I
GS881E36BD-250I
GS881E36BD-200I
GS881E36BD-150I
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Though
DCD Pipeline/Flow Through
DCD Pipeline/Fw Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
165 BGA (var. 1)
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
250/5.5
200/6.5
150/7.5
333/4.5
300/5
250/5.5
200/6.5
150/7.5
333/4.5
300/5
250/5.5
200/6.5
150/7.5
333/4.5
300/5
I
250/5.5
200/6.5
150/7.5
333/4.5
300/5
I
I
I
I
I
250/5.5
200/6.5
150/7.5
333/4.5
300/5
I
I
I
I
I
250/5.5
200/6.5
150/7.5
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS881E18BT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.04a 3/2009
37/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Ordering Information for GSI Synchronous Burst RAMs (Continued)
2
Speed
3
1
Org
Type
Package
T
Part Number
A
(MHz/ns)
333/4.5
300/5
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 32
256K x 32
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 32
256K x 32
256K x 32
256K x 32
256K x 32
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
GS881E18BGD-333
GS881E18BGD-300
GS881E18BGD-250
GS881E18BGD-200
GS881E18BGD-150
GS881E32BGD-333
GS881E32BGD-300
GS881E32BGD-250
GS881E32BGD-200
GS881E32BGD-150
GS881E36BGD-333
GS881E36BGD-300
GS881E36BGD-250
GS881E36BGD-200
GS881E36BGD-150
GS881E18BGD-333I
GS881E18BGD-300I
GS881E18BGD-250I
GS881E18BGD-200I
GS881E18BGD-150I
GS881E32BGD-333I
GS881E32BGD-300I
GS881E32BGD-250I
GS881E32BGD-200I
GS881E32D-150I
GS881E36BGD-333I
GS881E36BGD-300I
GS881E36BGD-250I
GS881E36BGD-200I
GS881E36BGD-150I
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Though
DCD Pipeline/Flow Through
DCD Pipeline/Fw Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
DCD Pipeline/Flow Through
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant GA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
RoHS-Compliant 165 BGA (var. 1)
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
250/5.5
200/6.5
150/7.5
333/4.5
300/5
250/5.5
200/6.5
150/7.5
333/4.5
300/5
250/5.5
200/6.5
150/7.5
333/4.5
300/5
I
250/5.5
200/6.5
150/7.5
333/4.5
300/5
I
I
I
I
I
250/5.5
200/6.5
150/7.5
333/4.5
300/5
I
I
I
I
I
250/5.5
200/6.5
150/7.5
I
I
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS881E18BT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.04a 3/2009
38/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
9Mb Sync SRAM Datasheet Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Page;Revisions;Reason
New
• Creation of new datasheet
881E18B_r1
• Added x32 TQFP
• Removed address and DQ number designations
881E18B_r1;
881E18B_r1_01
Content
• Removed erroneous speed bins
881E18B_r1_01;
881E18B_r1_02
• Added 333/300 MHz speed bins
• Basic format updates
Content/Format
• Removed Preliminary banner due to qualification of parts
• Added Pb-free information to QFP
• Added variation information 65 BGA
881E18B_r1_02;
881E18B_r1_03
Content/Format
Content
• Added Pb-free information for 165 BGA
• (Rev1_04a) Updated nomenclature from Pb-free to RoHS-
Compliant, Updated 165-FPBGA Mechanical Drawing
881E18B_r1_03;
881E18B_r1_04
Rev: 1.04a 3/2009
39/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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